1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/align.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma/edma.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/ioport.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/sizes.h> 21 #include <linux/types.h> 22 23 #include "../../pci.h" 24 #include "pcie-designware.h" 25 26 static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = { 27 [DW_PCIE_DBI_CLK] = "dbi", 28 [DW_PCIE_MSTR_CLK] = "mstr", 29 [DW_PCIE_SLV_CLK] = "slv", 30 }; 31 32 static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = { 33 [DW_PCIE_PIPE_CLK] = "pipe", 34 [DW_PCIE_CORE_CLK] = "core", 35 [DW_PCIE_AUX_CLK] = "aux", 36 [DW_PCIE_REF_CLK] = "ref", 37 }; 38 39 static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = { 40 [DW_PCIE_DBI_RST] = "dbi", 41 [DW_PCIE_MSTR_RST] = "mstr", 42 [DW_PCIE_SLV_RST] = "slv", 43 }; 44 45 static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = { 46 [DW_PCIE_NON_STICKY_RST] = "non-sticky", 47 [DW_PCIE_STICKY_RST] = "sticky", 48 [DW_PCIE_CORE_RST] = "core", 49 [DW_PCIE_PIPE_RST] = "pipe", 50 [DW_PCIE_PHY_RST] = "phy", 51 [DW_PCIE_HOT_RST] = "hot", 52 [DW_PCIE_PWR_RST] = "pwr", 53 }; 54 55 static int dw_pcie_get_clocks(struct dw_pcie *pci) 56 { 57 int i, ret; 58 59 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++) 60 pci->app_clks[i].id = dw_pcie_app_clks[i]; 61 62 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++) 63 pci->core_clks[i].id = dw_pcie_core_clks[i]; 64 65 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS, 66 pci->app_clks); 67 if (ret) 68 return ret; 69 70 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS, 71 pci->core_clks); 72 } 73 74 static int dw_pcie_get_resets(struct dw_pcie *pci) 75 { 76 int i, ret; 77 78 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++) 79 pci->app_rsts[i].id = dw_pcie_app_rsts[i]; 80 81 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++) 82 pci->core_rsts[i].id = dw_pcie_core_rsts[i]; 83 84 ret = devm_reset_control_bulk_get_optional_shared(pci->dev, 85 DW_PCIE_NUM_APP_RSTS, 86 pci->app_rsts); 87 if (ret) 88 return ret; 89 90 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev, 91 DW_PCIE_NUM_CORE_RSTS, 92 pci->core_rsts); 93 if (ret) 94 return ret; 95 96 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH); 97 if (IS_ERR(pci->pe_rst)) 98 return PTR_ERR(pci->pe_rst); 99 100 return 0; 101 } 102 103 int dw_pcie_get_resources(struct dw_pcie *pci) 104 { 105 struct platform_device *pdev = to_platform_device(pci->dev); 106 struct device_node *np = dev_of_node(pci->dev); 107 struct resource *res; 108 int ret; 109 110 if (!pci->dbi_base) { 111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 112 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); 113 if (IS_ERR(pci->dbi_base)) 114 return PTR_ERR(pci->dbi_base); 115 } 116 117 /* DBI2 is mainly useful for the endpoint controller */ 118 if (!pci->dbi_base2) { 119 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 120 if (res) { 121 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); 122 if (IS_ERR(pci->dbi_base2)) 123 return PTR_ERR(pci->dbi_base2); 124 } else { 125 pci->dbi_base2 = pci->dbi_base + SZ_4K; 126 } 127 } 128 129 /* For non-unrolled iATU/eDMA platforms this range will be ignored */ 130 if (!pci->atu_base) { 131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 132 if (res) { 133 pci->atu_size = resource_size(res); 134 pci->atu_base = devm_ioremap_resource(pci->dev, res); 135 if (IS_ERR(pci->atu_base)) 136 return PTR_ERR(pci->atu_base); 137 } else { 138 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 139 } 140 } 141 142 /* Set a default value suitable for at most 8 in and 8 out windows */ 143 if (!pci->atu_size) 144 pci->atu_size = SZ_4K; 145 146 /* eDMA region can be mapped to a custom base address */ 147 if (!pci->edma.reg_base) { 148 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 149 if (res) { 150 pci->edma.reg_base = devm_ioremap_resource(pci->dev, res); 151 if (IS_ERR(pci->edma.reg_base)) 152 return PTR_ERR(pci->edma.reg_base); 153 } else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) { 154 pci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET; 155 } 156 } 157 158 /* LLDD is supposed to manually switch the clocks and resets state */ 159 if (dw_pcie_cap_is(pci, REQ_RES)) { 160 ret = dw_pcie_get_clocks(pci); 161 if (ret) 162 return ret; 163 164 ret = dw_pcie_get_resets(pci); 165 if (ret) 166 return ret; 167 } 168 169 if (pci->link_gen < 1) 170 pci->link_gen = of_pci_get_max_link_speed(np); 171 172 of_property_read_u32(np, "num-lanes", &pci->num_lanes); 173 174 if (of_property_read_bool(np, "snps,enable-cdm-check")) 175 dw_pcie_cap_set(pci, CDM_CHECK); 176 177 return 0; 178 } 179 180 void dw_pcie_version_detect(struct dw_pcie *pci) 181 { 182 u32 ver; 183 184 /* The content of the CSR is zero on DWC PCIe older than v4.70a */ 185 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER); 186 if (!ver) 187 return; 188 189 if (pci->version && pci->version != ver) 190 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n", 191 pci->version, ver); 192 else 193 pci->version = ver; 194 195 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE); 196 197 if (pci->type && pci->type != ver) 198 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n", 199 pci->type, ver); 200 else 201 pci->type = ver; 202 } 203 204 /* 205 * These interfaces resemble the pci_find_*capability() interfaces, but these 206 * are for configuring host controllers, which are bridges *to* PCI devices but 207 * are not PCI devices themselves. 208 */ 209 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, 210 u8 cap) 211 { 212 u8 cap_id, next_cap_ptr; 213 u16 reg; 214 215 if (!cap_ptr) 216 return 0; 217 218 reg = dw_pcie_readw_dbi(pci, cap_ptr); 219 cap_id = (reg & 0x00ff); 220 221 if (cap_id > PCI_CAP_ID_MAX) 222 return 0; 223 224 if (cap_id == cap) 225 return cap_ptr; 226 227 next_cap_ptr = (reg & 0xff00) >> 8; 228 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); 229 } 230 231 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) 232 { 233 u8 next_cap_ptr; 234 u16 reg; 235 236 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); 237 next_cap_ptr = (reg & 0x00ff); 238 239 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); 240 } 241 EXPORT_SYMBOL_GPL(dw_pcie_find_capability); 242 243 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, 244 u8 cap) 245 { 246 u32 header; 247 int ttl; 248 int pos = PCI_CFG_SPACE_SIZE; 249 250 /* minimum 8 bytes per capability */ 251 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 252 253 if (start) 254 pos = start; 255 256 header = dw_pcie_readl_dbi(pci, pos); 257 /* 258 * If we have no capabilities, this is indicated by cap ID, 259 * cap version and next pointer all being 0. 260 */ 261 if (header == 0) 262 return 0; 263 264 while (ttl-- > 0) { 265 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 266 return pos; 267 268 pos = PCI_EXT_CAP_NEXT(header); 269 if (pos < PCI_CFG_SPACE_SIZE) 270 break; 271 272 header = dw_pcie_readl_dbi(pci, pos); 273 } 274 275 return 0; 276 } 277 278 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) 279 { 280 return dw_pcie_find_next_ext_capability(pci, 0, cap); 281 } 282 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); 283 284 int dw_pcie_read(void __iomem *addr, int size, u32 *val) 285 { 286 if (!IS_ALIGNED((uintptr_t)addr, size)) { 287 *val = 0; 288 return PCIBIOS_BAD_REGISTER_NUMBER; 289 } 290 291 if (size == 4) { 292 *val = readl(addr); 293 } else if (size == 2) { 294 *val = readw(addr); 295 } else if (size == 1) { 296 *val = readb(addr); 297 } else { 298 *val = 0; 299 return PCIBIOS_BAD_REGISTER_NUMBER; 300 } 301 302 return PCIBIOS_SUCCESSFUL; 303 } 304 EXPORT_SYMBOL_GPL(dw_pcie_read); 305 306 int dw_pcie_write(void __iomem *addr, int size, u32 val) 307 { 308 if (!IS_ALIGNED((uintptr_t)addr, size)) 309 return PCIBIOS_BAD_REGISTER_NUMBER; 310 311 if (size == 4) 312 writel(val, addr); 313 else if (size == 2) 314 writew(val, addr); 315 else if (size == 1) 316 writeb(val, addr); 317 else 318 return PCIBIOS_BAD_REGISTER_NUMBER; 319 320 return PCIBIOS_SUCCESSFUL; 321 } 322 EXPORT_SYMBOL_GPL(dw_pcie_write); 323 324 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) 325 { 326 int ret; 327 u32 val; 328 329 if (pci->ops && pci->ops->read_dbi) 330 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); 331 332 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); 333 if (ret) 334 dev_err(pci->dev, "Read DBI address failed\n"); 335 336 return val; 337 } 338 EXPORT_SYMBOL_GPL(dw_pcie_read_dbi); 339 340 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 341 { 342 int ret; 343 344 if (pci->ops && pci->ops->write_dbi) { 345 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); 346 return; 347 } 348 349 ret = dw_pcie_write(pci->dbi_base + reg, size, val); 350 if (ret) 351 dev_err(pci->dev, "Write DBI address failed\n"); 352 } 353 EXPORT_SYMBOL_GPL(dw_pcie_write_dbi); 354 355 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) 356 { 357 int ret; 358 359 if (pci->ops && pci->ops->write_dbi2) { 360 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); 361 return; 362 } 363 364 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); 365 if (ret) 366 dev_err(pci->dev, "write DBI address failed\n"); 367 } 368 369 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir, 370 u32 index) 371 { 372 if (dw_pcie_cap_is(pci, IATU_UNROLL)) 373 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index); 374 375 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index); 376 return pci->atu_base; 377 } 378 379 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg) 380 { 381 void __iomem *base; 382 int ret; 383 u32 val; 384 385 base = dw_pcie_select_atu(pci, dir, index); 386 387 if (pci->ops && pci->ops->read_dbi) 388 return pci->ops->read_dbi(pci, base, reg, 4); 389 390 ret = dw_pcie_read(base + reg, 4, &val); 391 if (ret) 392 dev_err(pci->dev, "Read ATU address failed\n"); 393 394 return val; 395 } 396 397 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index, 398 u32 reg, u32 val) 399 { 400 void __iomem *base; 401 int ret; 402 403 base = dw_pcie_select_atu(pci, dir, index); 404 405 if (pci->ops && pci->ops->write_dbi) { 406 pci->ops->write_dbi(pci, base, reg, 4, val); 407 return; 408 } 409 410 ret = dw_pcie_write(base + reg, 4, val); 411 if (ret) 412 dev_err(pci->dev, "Write ATU address failed\n"); 413 } 414 415 static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg) 416 { 417 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg); 418 } 419 420 static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg, 421 u32 val) 422 { 423 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val); 424 } 425 426 static inline u32 dw_pcie_enable_ecrc(u32 val) 427 { 428 /* 429 * DesignWare core version 4.90A has a design issue where the 'TD' 430 * bit in the Control register-1 of the ATU outbound region acts 431 * like an override for the ECRC setting, i.e., the presence of TLP 432 * Digest (ECRC) in the outgoing TLPs is solely determined by this 433 * bit. This is contrary to the PCIe spec which says that the 434 * enablement of the ECRC is solely determined by the AER 435 * registers. 436 * 437 * Because of this, even when the ECRC is enabled through AER 438 * registers, the transactions going through ATU won't have TLP 439 * Digest as there is no way the PCI core AER code could program 440 * the TD bit which is specific to the DesignWare core. 441 * 442 * The best way to handle this scenario is to program the TD bit 443 * always. It affects only the traffic from root port to downstream 444 * devices. 445 * 446 * At this point, 447 * When ECRC is enabled in AER registers, everything works normally 448 * When ECRC is NOT enabled in AER registers, then, 449 * on Root Port:- TLP Digest (DWord size) gets appended to each packet 450 * even through it is not required. Since downstream 451 * TLPs are mostly for configuration accesses and BAR 452 * accesses, they are not in critical path and won't 453 * have much negative effect on the performance. 454 * on End Point:- TLP Digest is received for some/all the packets coming 455 * from the root port. TLP Digest is ignored because, 456 * as per the PCIe Spec r5.0 v1.0 section 2.2.3 457 * "TLP Digest Rules", when an endpoint receives TLP 458 * Digest when its ECRC check functionality is disabled 459 * in AER registers, received TLP Digest is just ignored. 460 * Since there is no issue or error reported either side, best way to 461 * handle the scenario is to program TD bit by default. 462 */ 463 464 return val | PCIE_ATU_TD; 465 } 466 467 static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, 468 int index, int type, u64 cpu_addr, 469 u64 pci_addr, u64 size) 470 { 471 u32 retries, val; 472 u64 limit_addr; 473 474 if (pci->ops && pci->ops->cpu_addr_fixup) 475 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); 476 477 limit_addr = cpu_addr + size - 1; 478 479 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || 480 !IS_ALIGNED(cpu_addr, pci->region_align) || 481 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 482 return -EINVAL; 483 } 484 485 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE, 486 lower_32_bits(cpu_addr)); 487 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE, 488 upper_32_bits(cpu_addr)); 489 490 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT, 491 lower_32_bits(limit_addr)); 492 if (dw_pcie_ver_is_ge(pci, 460A)) 493 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT, 494 upper_32_bits(limit_addr)); 495 496 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET, 497 lower_32_bits(pci_addr)); 498 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET, 499 upper_32_bits(pci_addr)); 500 501 val = type | PCIE_ATU_FUNC_NUM(func_no); 502 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && 503 dw_pcie_ver_is_ge(pci, 460A)) 504 val |= PCIE_ATU_INCREASE_REGION_SIZE; 505 if (dw_pcie_ver_is(pci, 490A)) 506 val = dw_pcie_enable_ecrc(val); 507 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val); 508 509 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 510 511 /* 512 * Make sure ATU enable takes effect before any subsequent config 513 * and I/O accesses. 514 */ 515 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 516 val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2); 517 if (val & PCIE_ATU_ENABLE) 518 return 0; 519 520 mdelay(LINK_WAIT_IATU); 521 } 522 523 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); 524 525 return -ETIMEDOUT; 526 } 527 528 int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, 529 u64 cpu_addr, u64 pci_addr, u64 size) 530 { 531 return __dw_pcie_prog_outbound_atu(pci, 0, index, type, 532 cpu_addr, pci_addr, size); 533 } 534 535 int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, 536 int type, u64 cpu_addr, u64 pci_addr, 537 u64 size) 538 { 539 return __dw_pcie_prog_outbound_atu(pci, func_no, index, type, 540 cpu_addr, pci_addr, size); 541 } 542 543 static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) 544 { 545 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); 546 } 547 548 static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg, 549 u32 val) 550 { 551 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val); 552 } 553 554 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, 555 u64 cpu_addr, u64 pci_addr, u64 size) 556 { 557 u64 limit_addr = pci_addr + size - 1; 558 u32 retries, val; 559 560 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || 561 !IS_ALIGNED(cpu_addr, pci->region_align) || 562 !IS_ALIGNED(pci_addr, pci->region_align) || !size) { 563 return -EINVAL; 564 } 565 566 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE, 567 lower_32_bits(pci_addr)); 568 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE, 569 upper_32_bits(pci_addr)); 570 571 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT, 572 lower_32_bits(limit_addr)); 573 if (dw_pcie_ver_is_ge(pci, 460A)) 574 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT, 575 upper_32_bits(limit_addr)); 576 577 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 578 lower_32_bits(cpu_addr)); 579 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 580 upper_32_bits(cpu_addr)); 581 582 val = type; 583 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && 584 dw_pcie_ver_is_ge(pci, 460A)) 585 val |= PCIE_ATU_INCREASE_REGION_SIZE; 586 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val); 587 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); 588 589 /* 590 * Make sure ATU enable takes effect before any subsequent config 591 * and I/O accesses. 592 */ 593 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 594 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 595 if (val & PCIE_ATU_ENABLE) 596 return 0; 597 598 mdelay(LINK_WAIT_IATU); 599 } 600 601 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 602 603 return -ETIMEDOUT; 604 } 605 606 int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, 607 int type, u64 cpu_addr, u8 bar) 608 { 609 u32 retries, val; 610 611 if (!IS_ALIGNED(cpu_addr, pci->region_align)) 612 return -EINVAL; 613 614 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, 615 lower_32_bits(cpu_addr)); 616 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, 617 upper_32_bits(cpu_addr)); 618 619 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type | 620 PCIE_ATU_FUNC_NUM(func_no)); 621 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, 622 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN | 623 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); 624 625 /* 626 * Make sure ATU enable takes effect before any subsequent config 627 * and I/O accesses. 628 */ 629 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 630 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2); 631 if (val & PCIE_ATU_ENABLE) 632 return 0; 633 634 mdelay(LINK_WAIT_IATU); 635 } 636 637 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); 638 639 return -ETIMEDOUT; 640 } 641 642 void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) 643 { 644 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); 645 } 646 647 void dw_pcie_print_link_status(struct dw_pcie *pci) 648 { 649 u32 offset, val; 650 651 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 652 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 653 654 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", 655 FIELD_GET(PCI_EXP_LNKSTA_CLS, val), 656 FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); 657 } 658 659 int dw_pcie_wait_for_link(struct dw_pcie *pci) 660 { 661 int retries; 662 663 /* Check if the link is up or not */ 664 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 665 if (dw_pcie_link_up(pci)) 666 break; 667 668 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 669 } 670 671 if (retries >= LINK_WAIT_MAX_RETRIES) { 672 dev_info(pci->dev, "Phy link never came up\n"); 673 return -ETIMEDOUT; 674 } 675 676 dw_pcie_print_link_status(pci); 677 678 return 0; 679 } 680 EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); 681 682 int dw_pcie_link_up(struct dw_pcie *pci) 683 { 684 u32 val; 685 686 if (pci->ops && pci->ops->link_up) 687 return pci->ops->link_up(pci); 688 689 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1); 690 return ((val & PCIE_PORT_DEBUG1_LINK_UP) && 691 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING))); 692 } 693 EXPORT_SYMBOL_GPL(dw_pcie_link_up); 694 695 void dw_pcie_upconfig_setup(struct dw_pcie *pci) 696 { 697 u32 val; 698 699 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); 700 val |= PORT_MLTI_UPCFG_SUPPORT; 701 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); 702 } 703 EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); 704 705 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) 706 { 707 u32 cap, ctrl2, link_speed; 708 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 709 710 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 711 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); 712 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; 713 714 switch (pcie_link_speed[link_gen]) { 715 case PCIE_SPEED_2_5GT: 716 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; 717 break; 718 case PCIE_SPEED_5_0GT: 719 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 720 break; 721 case PCIE_SPEED_8_0GT: 722 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; 723 break; 724 case PCIE_SPEED_16_0GT: 725 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; 726 break; 727 default: 728 /* Use hardware capability */ 729 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); 730 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; 731 break; 732 } 733 734 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); 735 736 cap &= ~((u32)PCI_EXP_LNKCAP_SLS); 737 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); 738 739 } 740 741 void dw_pcie_iatu_detect(struct dw_pcie *pci) 742 { 743 int max_region, ob, ib; 744 u32 val, min, dir; 745 u64 max; 746 747 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 748 if (val == 0xFFFFFFFF) { 749 dw_pcie_cap_set(pci, IATU_UNROLL); 750 751 max_region = min((int)pci->atu_size / 512, 256); 752 } else { 753 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; 754 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; 755 756 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); 757 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; 758 } 759 760 for (ob = 0; ob < max_region; ob++) { 761 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000); 762 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET); 763 if (val != 0x11110000) 764 break; 765 } 766 767 for (ib = 0; ib < max_region; ib++) { 768 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000); 769 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET); 770 if (val != 0x11110000) 771 break; 772 } 773 774 if (ob) { 775 dir = PCIE_ATU_REGION_DIR_OB; 776 } else if (ib) { 777 dir = PCIE_ATU_REGION_DIR_IB; 778 } else { 779 dev_err(pci->dev, "No iATU regions found\n"); 780 return; 781 } 782 783 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0); 784 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT); 785 786 if (dw_pcie_ver_is_ge(pci, 460A)) { 787 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF); 788 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT); 789 } else { 790 max = 0; 791 } 792 793 pci->num_ob_windows = ob; 794 pci->num_ib_windows = ib; 795 pci->region_align = 1 << fls(min); 796 pci->region_limit = (max << 32) | (SZ_4G - 1); 797 798 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", 799 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", 800 pci->num_ob_windows, pci->num_ib_windows, 801 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G); 802 } 803 804 static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) 805 { 806 u32 val = 0; 807 int ret; 808 809 if (pci->ops && pci->ops->read_dbi) 810 return pci->ops->read_dbi(pci, pci->edma.reg_base, reg, 4); 811 812 ret = dw_pcie_read(pci->edma.reg_base + reg, 4, &val); 813 if (ret) 814 dev_err(pci->dev, "Read DMA address failed\n"); 815 816 return val; 817 } 818 819 static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) 820 { 821 struct platform_device *pdev = to_platform_device(dev); 822 char name[6]; 823 int ret; 824 825 if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) 826 return -EINVAL; 827 828 ret = platform_get_irq_byname_optional(pdev, "dma"); 829 if (ret > 0) 830 return ret; 831 832 snprintf(name, sizeof(name), "dma%u", nr); 833 834 return platform_get_irq_byname_optional(pdev, name); 835 } 836 837 static struct dw_edma_plat_ops dw_pcie_edma_ops = { 838 .irq_vector = dw_pcie_edma_irq_vector, 839 }; 840 841 static int dw_pcie_edma_find_chip(struct dw_pcie *pci) 842 { 843 u32 val; 844 845 /* 846 * Indirect eDMA CSRs access has been completely removed since v5.40a 847 * thus no space is now reserved for the eDMA channels viewport and 848 * former DMA CTRL register is no longer fixed to FFs. 849 */ 850 if (dw_pcie_ver_is_ge(pci, 540A)) 851 val = 0xFFFFFFFF; 852 else 853 val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 854 855 if (val == 0xFFFFFFFF && pci->edma.reg_base) { 856 pci->edma.mf = EDMA_MF_EDMA_UNROLL; 857 858 val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); 859 } else if (val != 0xFFFFFFFF) { 860 pci->edma.mf = EDMA_MF_EDMA_LEGACY; 861 862 pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; 863 } else { 864 return -ENODEV; 865 } 866 867 pci->edma.dev = pci->dev; 868 869 if (!pci->edma.ops) 870 pci->edma.ops = &dw_pcie_edma_ops; 871 872 pci->edma.flags |= DW_EDMA_CHIP_LOCAL; 873 874 pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); 875 pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); 876 877 /* Sanity check the channels count if the mapping was incorrect */ 878 if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || 879 !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) 880 return -EINVAL; 881 882 return 0; 883 } 884 885 static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) 886 { 887 struct platform_device *pdev = to_platform_device(pci->dev); 888 u16 ch_cnt = pci->edma.ll_wr_cnt + pci->edma.ll_rd_cnt; 889 char name[6]; 890 int ret; 891 892 if (pci->edma.nr_irqs == 1) 893 return 0; 894 else if (pci->edma.nr_irqs > 1) 895 return pci->edma.nr_irqs != ch_cnt ? -EINVAL : 0; 896 897 ret = platform_get_irq_byname_optional(pdev, "dma"); 898 if (ret > 0) { 899 pci->edma.nr_irqs = 1; 900 return 0; 901 } 902 903 for (; pci->edma.nr_irqs < ch_cnt; pci->edma.nr_irqs++) { 904 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs); 905 906 ret = platform_get_irq_byname_optional(pdev, name); 907 if (ret <= 0) 908 return -EINVAL; 909 } 910 911 return 0; 912 } 913 914 static int dw_pcie_edma_ll_alloc(struct dw_pcie *pci) 915 { 916 struct dw_edma_region *ll; 917 dma_addr_t paddr; 918 int i; 919 920 for (i = 0; i < pci->edma.ll_wr_cnt; i++) { 921 ll = &pci->edma.ll_region_wr[i]; 922 ll->sz = DMA_LLP_MEM_SIZE; 923 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 924 &paddr, GFP_KERNEL); 925 if (!ll->vaddr.mem) 926 return -ENOMEM; 927 928 ll->paddr = paddr; 929 } 930 931 for (i = 0; i < pci->edma.ll_rd_cnt; i++) { 932 ll = &pci->edma.ll_region_rd[i]; 933 ll->sz = DMA_LLP_MEM_SIZE; 934 ll->vaddr.mem = dmam_alloc_coherent(pci->dev, ll->sz, 935 &paddr, GFP_KERNEL); 936 if (!ll->vaddr.mem) 937 return -ENOMEM; 938 939 ll->paddr = paddr; 940 } 941 942 return 0; 943 } 944 945 int dw_pcie_edma_detect(struct dw_pcie *pci) 946 { 947 int ret; 948 949 /* Don't fail if no eDMA was found (for the backward compatibility) */ 950 ret = dw_pcie_edma_find_chip(pci); 951 if (ret) 952 return 0; 953 954 /* Don't fail on the IRQs verification (for the backward compatibility) */ 955 ret = dw_pcie_edma_irq_verify(pci); 956 if (ret) { 957 dev_err(pci->dev, "Invalid eDMA IRQs found\n"); 958 return 0; 959 } 960 961 ret = dw_pcie_edma_ll_alloc(pci); 962 if (ret) { 963 dev_err(pci->dev, "Couldn't allocate LLP memory\n"); 964 return ret; 965 } 966 967 /* Don't fail if the DW eDMA driver can't find the device */ 968 ret = dw_edma_probe(&pci->edma); 969 if (ret && ret != -ENODEV) { 970 dev_err(pci->dev, "Couldn't register eDMA device\n"); 971 return ret; 972 } 973 974 dev_info(pci->dev, "eDMA: unroll %s, %hu wr, %hu rd\n", 975 pci->edma.mf == EDMA_MF_EDMA_UNROLL ? "T" : "F", 976 pci->edma.ll_wr_cnt, pci->edma.ll_rd_cnt); 977 978 return 0; 979 } 980 981 void dw_pcie_edma_remove(struct dw_pcie *pci) 982 { 983 dw_edma_remove(&pci->edma); 984 } 985 986 void dw_pcie_setup(struct dw_pcie *pci) 987 { 988 u32 val; 989 990 if (pci->link_gen > 0) 991 dw_pcie_link_set_max_speed(pci, pci->link_gen); 992 993 /* Configure Gen1 N_FTS */ 994 if (pci->n_fts[0]) { 995 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); 996 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); 997 val |= PORT_AFR_N_FTS(pci->n_fts[0]); 998 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); 999 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); 1000 } 1001 1002 /* Configure Gen2+ N_FTS */ 1003 if (pci->n_fts[1]) { 1004 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1005 val &= ~PORT_LOGIC_N_FTS_MASK; 1006 val |= pci->n_fts[1]; 1007 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1008 } 1009 1010 if (dw_pcie_cap_is(pci, CDM_CHECK)) { 1011 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); 1012 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | 1013 PCIE_PL_CHK_REG_CHK_REG_START; 1014 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); 1015 } 1016 1017 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); 1018 val &= ~PORT_LINK_FAST_LINK_MODE; 1019 val |= PORT_LINK_DLL_LINK_EN; 1020 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1021 1022 if (!pci->num_lanes) { 1023 dev_dbg(pci->dev, "Using h/w default number of lanes\n"); 1024 return; 1025 } 1026 1027 /* Set the number of lanes */ 1028 val &= ~PORT_LINK_FAST_LINK_MODE; 1029 val &= ~PORT_LINK_MODE_MASK; 1030 switch (pci->num_lanes) { 1031 case 1: 1032 val |= PORT_LINK_MODE_1_LANES; 1033 break; 1034 case 2: 1035 val |= PORT_LINK_MODE_2_LANES; 1036 break; 1037 case 4: 1038 val |= PORT_LINK_MODE_4_LANES; 1039 break; 1040 case 8: 1041 val |= PORT_LINK_MODE_8_LANES; 1042 break; 1043 default: 1044 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); 1045 return; 1046 } 1047 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); 1048 1049 /* Set link width speed control register */ 1050 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 1051 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 1052 switch (pci->num_lanes) { 1053 case 1: 1054 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 1055 break; 1056 case 2: 1057 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 1058 break; 1059 case 4: 1060 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 1061 break; 1062 case 8: 1063 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 1064 break; 1065 } 1066 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 1067 } 1068