1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/msi.h> 14 #include <linux/of_address.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci_regs.h> 17 #include <linux/platform_device.h> 18 19 #include "../../pci.h" 20 #include "pcie-designware.h" 21 22 static struct pci_ops dw_pcie_ops; 23 static struct pci_ops dw_child_pcie_ops; 24 25 static void dw_msi_ack_irq(struct irq_data *d) 26 { 27 irq_chip_ack_parent(d); 28 } 29 30 static void dw_msi_mask_irq(struct irq_data *d) 31 { 32 pci_msi_mask_irq(d); 33 irq_chip_mask_parent(d); 34 } 35 36 static void dw_msi_unmask_irq(struct irq_data *d) 37 { 38 pci_msi_unmask_irq(d); 39 irq_chip_unmask_parent(d); 40 } 41 42 static struct irq_chip dw_pcie_msi_irq_chip = { 43 .name = "PCI-MSI", 44 .irq_ack = dw_msi_ack_irq, 45 .irq_mask = dw_msi_mask_irq, 46 .irq_unmask = dw_msi_unmask_irq, 47 }; 48 49 static struct msi_domain_info dw_pcie_msi_domain_info = { 50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 52 .chip = &dw_pcie_msi_irq_chip, 53 }; 54 55 /* MSI int handler */ 56 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 57 { 58 int i, pos; 59 unsigned long val; 60 u32 status, num_ctrls; 61 irqreturn_t ret = IRQ_NONE; 62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 63 64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 65 66 for (i = 0; i < num_ctrls; i++) { 67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 68 (i * MSI_REG_CTRL_BLOCK_SIZE)); 69 if (!status) 70 continue; 71 72 ret = IRQ_HANDLED; 73 val = status; 74 pos = 0; 75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 76 pos)) != MAX_MSI_IRQS_PER_CTRL) { 77 generic_handle_domain_irq(pp->irq_domain, 78 (i * MAX_MSI_IRQS_PER_CTRL) + 79 pos); 80 pos++; 81 } 82 } 83 84 return ret; 85 } 86 87 /* Chained MSI interrupt service routine */ 88 static void dw_chained_msi_isr(struct irq_desc *desc) 89 { 90 struct irq_chip *chip = irq_desc_get_chip(desc); 91 struct pcie_port *pp; 92 93 chained_irq_enter(chip, desc); 94 95 pp = irq_desc_get_handler_data(desc); 96 dw_handle_msi_irq(pp); 97 98 chained_irq_exit(chip, desc); 99 } 100 101 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 102 { 103 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 104 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 105 u64 msi_target; 106 107 msi_target = (u64)pp->msi_data; 108 109 msg->address_lo = lower_32_bits(msi_target); 110 msg->address_hi = upper_32_bits(msi_target); 111 112 msg->data = d->hwirq; 113 114 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 115 (int)d->hwirq, msg->address_hi, msg->address_lo); 116 } 117 118 static int dw_pci_msi_set_affinity(struct irq_data *d, 119 const struct cpumask *mask, bool force) 120 { 121 return -EINVAL; 122 } 123 124 static void dw_pci_bottom_mask(struct irq_data *d) 125 { 126 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 128 unsigned int res, bit, ctrl; 129 unsigned long flags; 130 131 raw_spin_lock_irqsave(&pp->lock, flags); 132 133 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 134 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 135 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 136 137 pp->irq_mask[ctrl] |= BIT(bit); 138 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 139 140 raw_spin_unlock_irqrestore(&pp->lock, flags); 141 } 142 143 static void dw_pci_bottom_unmask(struct irq_data *d) 144 { 145 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 146 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 147 unsigned int res, bit, ctrl; 148 unsigned long flags; 149 150 raw_spin_lock_irqsave(&pp->lock, flags); 151 152 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 153 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 154 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 155 156 pp->irq_mask[ctrl] &= ~BIT(bit); 157 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 158 159 raw_spin_unlock_irqrestore(&pp->lock, flags); 160 } 161 162 static void dw_pci_bottom_ack(struct irq_data *d) 163 { 164 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 166 unsigned int res, bit, ctrl; 167 168 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 169 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 170 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 171 172 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 173 } 174 175 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 176 .name = "DWPCI-MSI", 177 .irq_ack = dw_pci_bottom_ack, 178 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 179 .irq_set_affinity = dw_pci_msi_set_affinity, 180 .irq_mask = dw_pci_bottom_mask, 181 .irq_unmask = dw_pci_bottom_unmask, 182 }; 183 184 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 185 unsigned int virq, unsigned int nr_irqs, 186 void *args) 187 { 188 struct pcie_port *pp = domain->host_data; 189 unsigned long flags; 190 u32 i; 191 int bit; 192 193 raw_spin_lock_irqsave(&pp->lock, flags); 194 195 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 196 order_base_2(nr_irqs)); 197 198 raw_spin_unlock_irqrestore(&pp->lock, flags); 199 200 if (bit < 0) 201 return -ENOSPC; 202 203 for (i = 0; i < nr_irqs; i++) 204 irq_domain_set_info(domain, virq + i, bit + i, 205 pp->msi_irq_chip, 206 pp, handle_edge_irq, 207 NULL, NULL); 208 209 return 0; 210 } 211 212 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 213 unsigned int virq, unsigned int nr_irqs) 214 { 215 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 216 struct pcie_port *pp = domain->host_data; 217 unsigned long flags; 218 219 raw_spin_lock_irqsave(&pp->lock, flags); 220 221 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 222 order_base_2(nr_irqs)); 223 224 raw_spin_unlock_irqrestore(&pp->lock, flags); 225 } 226 227 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 228 .alloc = dw_pcie_irq_domain_alloc, 229 .free = dw_pcie_irq_domain_free, 230 }; 231 232 int dw_pcie_allocate_domains(struct pcie_port *pp) 233 { 234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 235 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 236 237 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 238 &dw_pcie_msi_domain_ops, pp); 239 if (!pp->irq_domain) { 240 dev_err(pci->dev, "Failed to create IRQ domain\n"); 241 return -ENOMEM; 242 } 243 244 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 245 246 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 247 &dw_pcie_msi_domain_info, 248 pp->irq_domain); 249 if (!pp->msi_domain) { 250 dev_err(pci->dev, "Failed to create MSI domain\n"); 251 irq_domain_remove(pp->irq_domain); 252 return -ENOMEM; 253 } 254 255 return 0; 256 } 257 258 static void dw_pcie_free_msi(struct pcie_port *pp) 259 { 260 if (pp->msi_irq) 261 irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); 262 263 irq_domain_remove(pp->msi_domain); 264 irq_domain_remove(pp->irq_domain); 265 266 if (pp->msi_data) { 267 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 268 struct device *dev = pci->dev; 269 270 dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg), 271 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 272 } 273 } 274 275 static void dw_pcie_msi_init(struct pcie_port *pp) 276 { 277 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 278 u64 msi_target = (u64)pp->msi_data; 279 280 if (!pci_msi_enabled() || !pp->has_msi_ctrl) 281 return; 282 283 /* Program the msi_data */ 284 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 285 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 286 } 287 288 int dw_pcie_host_init(struct pcie_port *pp) 289 { 290 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 291 struct device *dev = pci->dev; 292 struct device_node *np = dev->of_node; 293 struct platform_device *pdev = to_platform_device(dev); 294 struct resource_entry *win; 295 struct pci_host_bridge *bridge; 296 struct resource *cfg_res; 297 int ret; 298 299 raw_spin_lock_init(&pci->pp.lock); 300 301 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 302 if (cfg_res) { 303 pp->cfg0_size = resource_size(cfg_res); 304 pp->cfg0_base = cfg_res->start; 305 306 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res); 307 if (IS_ERR(pp->va_cfg0_base)) 308 return PTR_ERR(pp->va_cfg0_base); 309 } else { 310 dev_err(dev, "Missing *config* reg space\n"); 311 return -ENODEV; 312 } 313 314 if (!pci->dbi_base) { 315 struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 316 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); 317 if (IS_ERR(pci->dbi_base)) 318 return PTR_ERR(pci->dbi_base); 319 } 320 321 bridge = devm_pci_alloc_host_bridge(dev, 0); 322 if (!bridge) 323 return -ENOMEM; 324 325 pp->bridge = bridge; 326 327 /* Get the I/O range from DT */ 328 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 329 if (win) { 330 pp->io_size = resource_size(win->res); 331 pp->io_bus_addr = win->res->start - win->offset; 332 pp->io_base = pci_pio_to_address(win->res->start); 333 } 334 335 if (pci->link_gen < 1) 336 pci->link_gen = of_pci_get_max_link_speed(np); 337 338 /* Set default bus ops */ 339 bridge->ops = &dw_pcie_ops; 340 bridge->child_ops = &dw_child_pcie_ops; 341 342 if (pp->ops->host_init) { 343 ret = pp->ops->host_init(pp); 344 if (ret) 345 return ret; 346 } 347 348 if (pci_msi_enabled()) { 349 pp->has_msi_ctrl = !(pp->ops->msi_host_init || 350 of_property_read_bool(np, "msi-parent") || 351 of_property_read_bool(np, "msi-map")); 352 353 if (!pp->num_vectors) { 354 pp->num_vectors = MSI_DEF_NUM_VECTORS; 355 } else if (pp->num_vectors > MAX_MSI_IRQS) { 356 dev_err(dev, "Invalid number of vectors\n"); 357 return -EINVAL; 358 } 359 360 if (pp->ops->msi_host_init) { 361 ret = pp->ops->msi_host_init(pp); 362 if (ret < 0) 363 return ret; 364 } else if (pp->has_msi_ctrl) { 365 u32 ctrl, num_ctrls; 366 367 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 368 for (ctrl = 0; ctrl < num_ctrls; ctrl++) 369 pp->irq_mask[ctrl] = ~0; 370 371 if (!pp->msi_irq) { 372 pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); 373 if (pp->msi_irq < 0) { 374 pp->msi_irq = platform_get_irq(pdev, 0); 375 if (pp->msi_irq < 0) 376 return pp->msi_irq; 377 } 378 } 379 380 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 381 382 ret = dw_pcie_allocate_domains(pp); 383 if (ret) 384 return ret; 385 386 if (pp->msi_irq > 0) 387 irq_set_chained_handler_and_data(pp->msi_irq, 388 dw_chained_msi_isr, 389 pp); 390 391 ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); 392 if (ret) 393 dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); 394 395 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, 396 sizeof(pp->msi_msg), 397 DMA_FROM_DEVICE, 398 DMA_ATTR_SKIP_CPU_SYNC); 399 if (dma_mapping_error(pci->dev, pp->msi_data)) { 400 dev_err(pci->dev, "Failed to map MSI data\n"); 401 pp->msi_data = 0; 402 goto err_free_msi; 403 } 404 } 405 } 406 407 dw_pcie_iatu_detect(pci); 408 409 dw_pcie_setup_rc(pp); 410 411 if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) { 412 ret = pci->ops->start_link(pci); 413 if (ret) 414 goto err_free_msi; 415 } 416 417 /* Ignore errors, the link may come up later */ 418 dw_pcie_wait_for_link(pci); 419 420 bridge->sysdata = pp; 421 422 ret = pci_host_probe(bridge); 423 if (!ret) 424 return 0; 425 426 err_free_msi: 427 if (pp->has_msi_ctrl) 428 dw_pcie_free_msi(pp); 429 return ret; 430 } 431 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 432 433 void dw_pcie_host_deinit(struct pcie_port *pp) 434 { 435 pci_stop_root_bus(pp->bridge->bus); 436 pci_remove_root_bus(pp->bridge->bus); 437 if (pp->has_msi_ctrl) 438 dw_pcie_free_msi(pp); 439 } 440 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 441 442 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 443 unsigned int devfn, int where) 444 { 445 int type; 446 u32 busdev; 447 struct pcie_port *pp = bus->sysdata; 448 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 449 450 /* 451 * Checking whether the link is up here is a last line of defense 452 * against platforms that forward errors on the system bus as 453 * SError upon PCI configuration transactions issued when the link 454 * is down. This check is racy by definition and does not stop 455 * the system from triggering an SError if the link goes down 456 * after this check is performed. 457 */ 458 if (!dw_pcie_link_up(pci)) 459 return NULL; 460 461 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 462 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 463 464 if (pci_is_root_bus(bus->parent)) 465 type = PCIE_ATU_TYPE_CFG0; 466 else 467 type = PCIE_ATU_TYPE_CFG1; 468 469 470 dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size); 471 472 return pp->va_cfg0_base + where; 473 } 474 475 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 476 int where, int size, u32 *val) 477 { 478 int ret; 479 struct pcie_port *pp = bus->sysdata; 480 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 481 482 ret = pci_generic_config_read(bus, devfn, where, size, val); 483 484 if (!ret && pci->io_cfg_atu_shared) 485 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base, 486 pp->io_bus_addr, pp->io_size); 487 488 return ret; 489 } 490 491 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 492 int where, int size, u32 val) 493 { 494 int ret; 495 struct pcie_port *pp = bus->sysdata; 496 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 497 498 ret = pci_generic_config_write(bus, devfn, where, size, val); 499 500 if (!ret && pci->io_cfg_atu_shared) 501 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base, 502 pp->io_bus_addr, pp->io_size); 503 504 return ret; 505 } 506 507 static struct pci_ops dw_child_pcie_ops = { 508 .map_bus = dw_pcie_other_conf_map_bus, 509 .read = dw_pcie_rd_other_conf, 510 .write = dw_pcie_wr_other_conf, 511 }; 512 513 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 514 { 515 struct pcie_port *pp = bus->sysdata; 516 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 517 518 if (PCI_SLOT(devfn) > 0) 519 return NULL; 520 521 return pci->dbi_base + where; 522 } 523 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 524 525 static struct pci_ops dw_pcie_ops = { 526 .map_bus = dw_pcie_own_conf_map_bus, 527 .read = pci_generic_config_read, 528 .write = pci_generic_config_write, 529 }; 530 531 void dw_pcie_setup_rc(struct pcie_port *pp) 532 { 533 int i; 534 u32 val, ctrl, num_ctrls; 535 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 536 537 /* 538 * Enable DBI read-only registers for writing/updating configuration. 539 * Write permission gets disabled towards the end of this function. 540 */ 541 dw_pcie_dbi_ro_wr_en(pci); 542 543 dw_pcie_setup(pci); 544 545 if (pp->has_msi_ctrl) { 546 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 547 548 /* Initialize IRQ Status array */ 549 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 550 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 551 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 552 pp->irq_mask[ctrl]); 553 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 554 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 555 ~0); 556 } 557 } 558 559 dw_pcie_msi_init(pp); 560 561 /* Setup RC BARs */ 562 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 563 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 564 565 /* Setup interrupt pins */ 566 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 567 val &= 0xffff00ff; 568 val |= 0x00000100; 569 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 570 571 /* Setup bus numbers */ 572 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 573 val &= 0xff000000; 574 val |= 0x00ff0100; 575 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 576 577 /* Setup command register */ 578 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 579 val &= 0xffff0000; 580 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 581 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 582 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 583 584 /* Ensure all outbound windows are disabled so there are multiple matches */ 585 for (i = 0; i < pci->num_ob_windows; i++) 586 dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); 587 588 /* 589 * If the platform provides its own child bus config accesses, it means 590 * the platform uses its own address translation component rather than 591 * ATU, so we should not program the ATU here. 592 */ 593 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 594 int atu_idx = 0; 595 struct resource_entry *entry; 596 597 /* Get last memory resource entry */ 598 resource_list_for_each_entry(entry, &pp->bridge->windows) { 599 if (resource_type(entry->res) != IORESOURCE_MEM) 600 continue; 601 602 if (pci->num_ob_windows <= ++atu_idx) 603 break; 604 605 dw_pcie_prog_outbound_atu(pci, atu_idx, 606 PCIE_ATU_TYPE_MEM, entry->res->start, 607 entry->res->start - entry->offset, 608 resource_size(entry->res)); 609 } 610 611 if (pp->io_size) { 612 if (pci->num_ob_windows > ++atu_idx) 613 dw_pcie_prog_outbound_atu(pci, atu_idx, 614 PCIE_ATU_TYPE_IO, pp->io_base, 615 pp->io_bus_addr, pp->io_size); 616 else 617 pci->io_cfg_atu_shared = true; 618 } 619 620 if (pci->num_ob_windows <= atu_idx) 621 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)", 622 pci->num_ob_windows); 623 } 624 625 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 626 627 /* Program correct class for RC */ 628 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 629 630 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 631 val |= PORT_LOGIC_SPEED_CHANGE; 632 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 633 634 dw_pcie_dbi_ro_wr_dis(pci); 635 } 636 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 637