1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/msi.h> 14 #include <linux/of_address.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci_regs.h> 17 #include <linux/platform_device.h> 18 19 #include "../../pci.h" 20 #include "pcie-designware.h" 21 22 static struct pci_ops dw_pcie_ops; 23 static struct pci_ops dw_child_pcie_ops; 24 25 static void dw_msi_ack_irq(struct irq_data *d) 26 { 27 irq_chip_ack_parent(d); 28 } 29 30 static void dw_msi_mask_irq(struct irq_data *d) 31 { 32 pci_msi_mask_irq(d); 33 irq_chip_mask_parent(d); 34 } 35 36 static void dw_msi_unmask_irq(struct irq_data *d) 37 { 38 pci_msi_unmask_irq(d); 39 irq_chip_unmask_parent(d); 40 } 41 42 static struct irq_chip dw_pcie_msi_irq_chip = { 43 .name = "PCI-MSI", 44 .irq_ack = dw_msi_ack_irq, 45 .irq_mask = dw_msi_mask_irq, 46 .irq_unmask = dw_msi_unmask_irq, 47 }; 48 49 static struct msi_domain_info dw_pcie_msi_domain_info = { 50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 52 .chip = &dw_pcie_msi_irq_chip, 53 }; 54 55 /* MSI int handler */ 56 irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) 57 { 58 int i, pos; 59 unsigned long val; 60 u32 status, num_ctrls; 61 irqreturn_t ret = IRQ_NONE; 62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 63 64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 65 66 for (i = 0; i < num_ctrls; i++) { 67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 68 (i * MSI_REG_CTRL_BLOCK_SIZE)); 69 if (!status) 70 continue; 71 72 ret = IRQ_HANDLED; 73 val = status; 74 pos = 0; 75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 76 pos)) != MAX_MSI_IRQS_PER_CTRL) { 77 generic_handle_domain_irq(pp->irq_domain, 78 (i * MAX_MSI_IRQS_PER_CTRL) + 79 pos); 80 pos++; 81 } 82 } 83 84 return ret; 85 } 86 87 /* Chained MSI interrupt service routine */ 88 static void dw_chained_msi_isr(struct irq_desc *desc) 89 { 90 struct irq_chip *chip = irq_desc_get_chip(desc); 91 struct dw_pcie_rp *pp; 92 93 chained_irq_enter(chip, desc); 94 95 pp = irq_desc_get_handler_data(desc); 96 dw_handle_msi_irq(pp); 97 98 chained_irq_exit(chip, desc); 99 } 100 101 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 102 { 103 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 104 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 105 u64 msi_target; 106 107 msi_target = (u64)pp->msi_data; 108 109 msg->address_lo = lower_32_bits(msi_target); 110 msg->address_hi = upper_32_bits(msi_target); 111 112 msg->data = d->hwirq; 113 114 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 115 (int)d->hwirq, msg->address_hi, msg->address_lo); 116 } 117 118 static int dw_pci_msi_set_affinity(struct irq_data *d, 119 const struct cpumask *mask, bool force) 120 { 121 return -EINVAL; 122 } 123 124 static void dw_pci_bottom_mask(struct irq_data *d) 125 { 126 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 128 unsigned int res, bit, ctrl; 129 unsigned long flags; 130 131 raw_spin_lock_irqsave(&pp->lock, flags); 132 133 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 134 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 135 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 136 137 pp->irq_mask[ctrl] |= BIT(bit); 138 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 139 140 raw_spin_unlock_irqrestore(&pp->lock, flags); 141 } 142 143 static void dw_pci_bottom_unmask(struct irq_data *d) 144 { 145 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 146 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 147 unsigned int res, bit, ctrl; 148 unsigned long flags; 149 150 raw_spin_lock_irqsave(&pp->lock, flags); 151 152 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 153 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 154 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 155 156 pp->irq_mask[ctrl] &= ~BIT(bit); 157 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 158 159 raw_spin_unlock_irqrestore(&pp->lock, flags); 160 } 161 162 static void dw_pci_bottom_ack(struct irq_data *d) 163 { 164 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 166 unsigned int res, bit, ctrl; 167 168 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 169 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 170 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 171 172 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 173 } 174 175 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 176 .name = "DWPCI-MSI", 177 .irq_ack = dw_pci_bottom_ack, 178 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 179 .irq_set_affinity = dw_pci_msi_set_affinity, 180 .irq_mask = dw_pci_bottom_mask, 181 .irq_unmask = dw_pci_bottom_unmask, 182 }; 183 184 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 185 unsigned int virq, unsigned int nr_irqs, 186 void *args) 187 { 188 struct dw_pcie_rp *pp = domain->host_data; 189 unsigned long flags; 190 u32 i; 191 int bit; 192 193 raw_spin_lock_irqsave(&pp->lock, flags); 194 195 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 196 order_base_2(nr_irqs)); 197 198 raw_spin_unlock_irqrestore(&pp->lock, flags); 199 200 if (bit < 0) 201 return -ENOSPC; 202 203 for (i = 0; i < nr_irqs; i++) 204 irq_domain_set_info(domain, virq + i, bit + i, 205 pp->msi_irq_chip, 206 pp, handle_edge_irq, 207 NULL, NULL); 208 209 return 0; 210 } 211 212 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 213 unsigned int virq, unsigned int nr_irqs) 214 { 215 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 216 struct dw_pcie_rp *pp = domain->host_data; 217 unsigned long flags; 218 219 raw_spin_lock_irqsave(&pp->lock, flags); 220 221 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 222 order_base_2(nr_irqs)); 223 224 raw_spin_unlock_irqrestore(&pp->lock, flags); 225 } 226 227 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 228 .alloc = dw_pcie_irq_domain_alloc, 229 .free = dw_pcie_irq_domain_free, 230 }; 231 232 int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) 233 { 234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 235 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 236 237 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 238 &dw_pcie_msi_domain_ops, pp); 239 if (!pp->irq_domain) { 240 dev_err(pci->dev, "Failed to create IRQ domain\n"); 241 return -ENOMEM; 242 } 243 244 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 245 246 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 247 &dw_pcie_msi_domain_info, 248 pp->irq_domain); 249 if (!pp->msi_domain) { 250 dev_err(pci->dev, "Failed to create MSI domain\n"); 251 irq_domain_remove(pp->irq_domain); 252 return -ENOMEM; 253 } 254 255 return 0; 256 } 257 258 static void dw_pcie_free_msi(struct dw_pcie_rp *pp) 259 { 260 u32 ctrl; 261 262 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 263 if (pp->msi_irq[ctrl] > 0) 264 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 265 NULL, NULL); 266 } 267 268 irq_domain_remove(pp->msi_domain); 269 irq_domain_remove(pp->irq_domain); 270 } 271 272 static void dw_pcie_msi_init(struct dw_pcie_rp *pp) 273 { 274 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 275 u64 msi_target = (u64)pp->msi_data; 276 277 if (!pci_msi_enabled() || !pp->has_msi_ctrl) 278 return; 279 280 /* Program the msi_data */ 281 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 282 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 283 } 284 285 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) 286 { 287 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 288 struct device *dev = pci->dev; 289 struct platform_device *pdev = to_platform_device(dev); 290 u32 ctrl, max_vectors; 291 int irq; 292 293 /* Parse any "msiX" IRQs described in the devicetree */ 294 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 295 char msi_name[] = "msiX"; 296 297 msi_name[3] = '0' + ctrl; 298 irq = platform_get_irq_byname_optional(pdev, msi_name); 299 if (irq == -ENXIO) 300 break; 301 if (irq < 0) 302 return dev_err_probe(dev, irq, 303 "Failed to parse MSI IRQ '%s'\n", 304 msi_name); 305 306 pp->msi_irq[ctrl] = irq; 307 } 308 309 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */ 310 if (ctrl == 0) 311 return -ENXIO; 312 313 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; 314 if (pp->num_vectors > max_vectors) { 315 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n", 316 max_vectors); 317 pp->num_vectors = max_vectors; 318 } 319 if (!pp->num_vectors) 320 pp->num_vectors = max_vectors; 321 322 return 0; 323 } 324 325 static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) 326 { 327 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 328 struct device *dev = pci->dev; 329 struct platform_device *pdev = to_platform_device(dev); 330 u64 *msi_vaddr; 331 int ret; 332 u32 ctrl, num_ctrls; 333 334 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) 335 pp->irq_mask[ctrl] = ~0; 336 337 if (!pp->msi_irq[0]) { 338 ret = dw_pcie_parse_split_msi_irq(pp); 339 if (ret < 0 && ret != -ENXIO) 340 return ret; 341 } 342 343 if (!pp->num_vectors) 344 pp->num_vectors = MSI_DEF_NUM_VECTORS; 345 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 346 347 if (!pp->msi_irq[0]) { 348 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); 349 if (pp->msi_irq[0] < 0) { 350 pp->msi_irq[0] = platform_get_irq(pdev, 0); 351 if (pp->msi_irq[0] < 0) 352 return pp->msi_irq[0]; 353 } 354 } 355 356 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); 357 358 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 359 360 ret = dw_pcie_allocate_domains(pp); 361 if (ret) 362 return ret; 363 364 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 365 if (pp->msi_irq[ctrl] > 0) 366 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 367 dw_chained_msi_isr, pp); 368 } 369 370 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 371 if (ret) 372 dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); 373 374 msi_vaddr = dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, 375 GFP_KERNEL); 376 if (!msi_vaddr) { 377 dev_err(dev, "Failed to alloc and map MSI data\n"); 378 dw_pcie_free_msi(pp); 379 return -ENOMEM; 380 } 381 382 return 0; 383 } 384 385 int dw_pcie_host_init(struct dw_pcie_rp *pp) 386 { 387 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 388 struct device *dev = pci->dev; 389 struct device_node *np = dev->of_node; 390 struct platform_device *pdev = to_platform_device(dev); 391 struct resource_entry *win; 392 struct pci_host_bridge *bridge; 393 struct resource *res; 394 int ret; 395 396 raw_spin_lock_init(&pp->lock); 397 398 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 399 if (res) { 400 pp->cfg0_size = resource_size(res); 401 pp->cfg0_base = res->start; 402 403 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 404 if (IS_ERR(pp->va_cfg0_base)) 405 return PTR_ERR(pp->va_cfg0_base); 406 } else { 407 dev_err(dev, "Missing *config* reg space\n"); 408 return -ENODEV; 409 } 410 411 if (!pci->dbi_base) { 412 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 413 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 414 if (IS_ERR(pci->dbi_base)) 415 return PTR_ERR(pci->dbi_base); 416 } 417 418 bridge = devm_pci_alloc_host_bridge(dev, 0); 419 if (!bridge) 420 return -ENOMEM; 421 422 pp->bridge = bridge; 423 424 /* Get the I/O range from DT */ 425 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 426 if (win) { 427 pp->io_size = resource_size(win->res); 428 pp->io_bus_addr = win->res->start - win->offset; 429 pp->io_base = pci_pio_to_address(win->res->start); 430 } 431 432 if (pci->link_gen < 1) 433 pci->link_gen = of_pci_get_max_link_speed(np); 434 435 /* Set default bus ops */ 436 bridge->ops = &dw_pcie_ops; 437 bridge->child_ops = &dw_child_pcie_ops; 438 439 if (pp->ops->host_init) { 440 ret = pp->ops->host_init(pp); 441 if (ret) 442 return ret; 443 } 444 445 if (pci_msi_enabled()) { 446 pp->has_msi_ctrl = !(pp->ops->msi_host_init || 447 of_property_read_bool(np, "msi-parent") || 448 of_property_read_bool(np, "msi-map")); 449 450 /* 451 * For the has_msi_ctrl case the default assignment is handled 452 * in the dw_pcie_msi_host_init(). 453 */ 454 if (!pp->has_msi_ctrl && !pp->num_vectors) { 455 pp->num_vectors = MSI_DEF_NUM_VECTORS; 456 } else if (pp->num_vectors > MAX_MSI_IRQS) { 457 dev_err(dev, "Invalid number of vectors\n"); 458 ret = -EINVAL; 459 goto err_deinit_host; 460 } 461 462 if (pp->ops->msi_host_init) { 463 ret = pp->ops->msi_host_init(pp); 464 if (ret < 0) 465 goto err_deinit_host; 466 } else if (pp->has_msi_ctrl) { 467 ret = dw_pcie_msi_host_init(pp); 468 if (ret < 0) 469 goto err_deinit_host; 470 } 471 } 472 473 dw_pcie_version_detect(pci); 474 475 dw_pcie_iatu_detect(pci); 476 477 ret = dw_pcie_setup_rc(pp); 478 if (ret) 479 goto err_free_msi; 480 481 if (!dw_pcie_link_up(pci)) { 482 ret = dw_pcie_start_link(pci); 483 if (ret) 484 goto err_free_msi; 485 } 486 487 /* Ignore errors, the link may come up later */ 488 dw_pcie_wait_for_link(pci); 489 490 bridge->sysdata = pp; 491 492 ret = pci_host_probe(bridge); 493 if (ret) 494 goto err_stop_link; 495 496 return 0; 497 498 err_stop_link: 499 dw_pcie_stop_link(pci); 500 501 err_free_msi: 502 if (pp->has_msi_ctrl) 503 dw_pcie_free_msi(pp); 504 505 err_deinit_host: 506 if (pp->ops->host_deinit) 507 pp->ops->host_deinit(pp); 508 509 return ret; 510 } 511 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 512 513 void dw_pcie_host_deinit(struct dw_pcie_rp *pp) 514 { 515 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 516 517 pci_stop_root_bus(pp->bridge->bus); 518 pci_remove_root_bus(pp->bridge->bus); 519 520 dw_pcie_stop_link(pci); 521 522 if (pp->has_msi_ctrl) 523 dw_pcie_free_msi(pp); 524 525 if (pp->ops->host_deinit) 526 pp->ops->host_deinit(pp); 527 } 528 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 529 530 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 531 unsigned int devfn, int where) 532 { 533 struct dw_pcie_rp *pp = bus->sysdata; 534 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 535 int type, ret; 536 u32 busdev; 537 538 /* 539 * Checking whether the link is up here is a last line of defense 540 * against platforms that forward errors on the system bus as 541 * SError upon PCI configuration transactions issued when the link 542 * is down. This check is racy by definition and does not stop 543 * the system from triggering an SError if the link goes down 544 * after this check is performed. 545 */ 546 if (!dw_pcie_link_up(pci)) 547 return NULL; 548 549 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 550 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 551 552 if (pci_is_root_bus(bus->parent)) 553 type = PCIE_ATU_TYPE_CFG0; 554 else 555 type = PCIE_ATU_TYPE_CFG1; 556 557 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, 558 pp->cfg0_size); 559 if (ret) 560 return NULL; 561 562 return pp->va_cfg0_base + where; 563 } 564 565 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 566 int where, int size, u32 *val) 567 { 568 struct dw_pcie_rp *pp = bus->sysdata; 569 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 570 int ret; 571 572 ret = pci_generic_config_read(bus, devfn, where, size, val); 573 if (ret != PCIBIOS_SUCCESSFUL) 574 return ret; 575 576 if (pp->cfg0_io_shared) { 577 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, 578 pp->io_base, pp->io_bus_addr, 579 pp->io_size); 580 if (ret) 581 return PCIBIOS_SET_FAILED; 582 } 583 584 return PCIBIOS_SUCCESSFUL; 585 } 586 587 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 588 int where, int size, u32 val) 589 { 590 struct dw_pcie_rp *pp = bus->sysdata; 591 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 592 int ret; 593 594 ret = pci_generic_config_write(bus, devfn, where, size, val); 595 if (ret != PCIBIOS_SUCCESSFUL) 596 return ret; 597 598 if (pp->cfg0_io_shared) { 599 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, 600 pp->io_base, pp->io_bus_addr, 601 pp->io_size); 602 if (ret) 603 return PCIBIOS_SET_FAILED; 604 } 605 606 return PCIBIOS_SUCCESSFUL; 607 } 608 609 static struct pci_ops dw_child_pcie_ops = { 610 .map_bus = dw_pcie_other_conf_map_bus, 611 .read = dw_pcie_rd_other_conf, 612 .write = dw_pcie_wr_other_conf, 613 }; 614 615 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 616 { 617 struct dw_pcie_rp *pp = bus->sysdata; 618 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 619 620 if (PCI_SLOT(devfn) > 0) 621 return NULL; 622 623 return pci->dbi_base + where; 624 } 625 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 626 627 static struct pci_ops dw_pcie_ops = { 628 .map_bus = dw_pcie_own_conf_map_bus, 629 .read = pci_generic_config_read, 630 .write = pci_generic_config_write, 631 }; 632 633 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) 634 { 635 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 636 struct resource_entry *entry; 637 int i, ret; 638 639 /* Note the very first outbound ATU is used for CFG IOs */ 640 if (!pci->num_ob_windows) { 641 dev_err(pci->dev, "No outbound iATU found\n"); 642 return -EINVAL; 643 } 644 645 /* 646 * Ensure all outbound windows are disabled before proceeding with 647 * the MEM/IO ranges setups. 648 */ 649 for (i = 0; i < pci->num_ob_windows; i++) 650 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i); 651 652 i = 0; 653 resource_list_for_each_entry(entry, &pp->bridge->windows) { 654 if (resource_type(entry->res) != IORESOURCE_MEM) 655 continue; 656 657 if (pci->num_ob_windows <= ++i) 658 break; 659 660 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, 661 entry->res->start, 662 entry->res->start - entry->offset, 663 resource_size(entry->res)); 664 if (ret) { 665 dev_err(pci->dev, "Failed to set MEM range %pr\n", 666 entry->res); 667 return ret; 668 } 669 } 670 671 if (pp->io_size) { 672 if (pci->num_ob_windows > ++i) { 673 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, 674 pp->io_base, 675 pp->io_bus_addr, 676 pp->io_size); 677 if (ret) { 678 dev_err(pci->dev, "Failed to set IO range %pr\n", 679 entry->res); 680 return ret; 681 } 682 } else { 683 pp->cfg0_io_shared = true; 684 } 685 } 686 687 if (pci->num_ob_windows <= i) 688 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n", 689 pci->num_ob_windows); 690 691 return 0; 692 } 693 694 int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 695 { 696 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 697 u32 val, ctrl, num_ctrls; 698 int ret; 699 700 /* 701 * Enable DBI read-only registers for writing/updating configuration. 702 * Write permission gets disabled towards the end of this function. 703 */ 704 dw_pcie_dbi_ro_wr_en(pci); 705 706 dw_pcie_setup(pci); 707 708 if (pp->has_msi_ctrl) { 709 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 710 711 /* Initialize IRQ Status array */ 712 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 713 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 714 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 715 pp->irq_mask[ctrl]); 716 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 717 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 718 ~0); 719 } 720 } 721 722 dw_pcie_msi_init(pp); 723 724 /* Setup RC BARs */ 725 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 726 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 727 728 /* Setup interrupt pins */ 729 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 730 val &= 0xffff00ff; 731 val |= 0x00000100; 732 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 733 734 /* Setup bus numbers */ 735 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 736 val &= 0xff000000; 737 val |= 0x00ff0100; 738 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 739 740 /* Setup command register */ 741 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 742 val &= 0xffff0000; 743 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 744 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 745 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 746 747 /* 748 * If the platform provides its own child bus config accesses, it means 749 * the platform uses its own address translation component rather than 750 * ATU, so we should not program the ATU here. 751 */ 752 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 753 ret = dw_pcie_iatu_setup(pp); 754 if (ret) 755 return ret; 756 } 757 758 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 759 760 /* Program correct class for RC */ 761 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 762 763 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 764 val |= PORT_LOGIC_SPEED_CHANGE; 765 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 766 767 dw_pcie_dbi_ro_wr_dis(pci); 768 769 return 0; 770 } 771 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 772