1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/msi.h> 14 #include <linux/of_address.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci_regs.h> 17 #include <linux/platform_device.h> 18 19 #include "../../pci.h" 20 #include "pcie-designware.h" 21 22 static struct pci_ops dw_pcie_ops; 23 static struct pci_ops dw_child_pcie_ops; 24 25 static void dw_msi_ack_irq(struct irq_data *d) 26 { 27 irq_chip_ack_parent(d); 28 } 29 30 static void dw_msi_mask_irq(struct irq_data *d) 31 { 32 pci_msi_mask_irq(d); 33 irq_chip_mask_parent(d); 34 } 35 36 static void dw_msi_unmask_irq(struct irq_data *d) 37 { 38 pci_msi_unmask_irq(d); 39 irq_chip_unmask_parent(d); 40 } 41 42 static struct irq_chip dw_pcie_msi_irq_chip = { 43 .name = "PCI-MSI", 44 .irq_ack = dw_msi_ack_irq, 45 .irq_mask = dw_msi_mask_irq, 46 .irq_unmask = dw_msi_unmask_irq, 47 }; 48 49 static struct msi_domain_info dw_pcie_msi_domain_info = { 50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 52 .chip = &dw_pcie_msi_irq_chip, 53 }; 54 55 /* MSI int handler */ 56 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 57 { 58 int i, pos, irq; 59 unsigned long val; 60 u32 status, num_ctrls; 61 irqreturn_t ret = IRQ_NONE; 62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 63 64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 65 66 for (i = 0; i < num_ctrls; i++) { 67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 68 (i * MSI_REG_CTRL_BLOCK_SIZE)); 69 if (!status) 70 continue; 71 72 ret = IRQ_HANDLED; 73 val = status; 74 pos = 0; 75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 76 pos)) != MAX_MSI_IRQS_PER_CTRL) { 77 irq = irq_find_mapping(pp->irq_domain, 78 (i * MAX_MSI_IRQS_PER_CTRL) + 79 pos); 80 generic_handle_irq(irq); 81 pos++; 82 } 83 } 84 85 return ret; 86 } 87 88 /* Chained MSI interrupt service routine */ 89 static void dw_chained_msi_isr(struct irq_desc *desc) 90 { 91 struct irq_chip *chip = irq_desc_get_chip(desc); 92 struct pcie_port *pp; 93 94 chained_irq_enter(chip, desc); 95 96 pp = irq_desc_get_handler_data(desc); 97 dw_handle_msi_irq(pp); 98 99 chained_irq_exit(chip, desc); 100 } 101 102 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 103 { 104 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 105 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 106 u64 msi_target; 107 108 msi_target = (u64)pp->msi_data; 109 110 msg->address_lo = lower_32_bits(msi_target); 111 msg->address_hi = upper_32_bits(msi_target); 112 113 msg->data = d->hwirq; 114 115 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 116 (int)d->hwirq, msg->address_hi, msg->address_lo); 117 } 118 119 static int dw_pci_msi_set_affinity(struct irq_data *d, 120 const struct cpumask *mask, bool force) 121 { 122 return -EINVAL; 123 } 124 125 static void dw_pci_bottom_mask(struct irq_data *d) 126 { 127 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 129 unsigned int res, bit, ctrl; 130 unsigned long flags; 131 132 raw_spin_lock_irqsave(&pp->lock, flags); 133 134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 136 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 137 138 pp->irq_mask[ctrl] |= BIT(bit); 139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 140 141 raw_spin_unlock_irqrestore(&pp->lock, flags); 142 } 143 144 static void dw_pci_bottom_unmask(struct irq_data *d) 145 { 146 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 147 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 148 unsigned int res, bit, ctrl; 149 unsigned long flags; 150 151 raw_spin_lock_irqsave(&pp->lock, flags); 152 153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 155 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 156 157 pp->irq_mask[ctrl] &= ~BIT(bit); 158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 159 160 raw_spin_unlock_irqrestore(&pp->lock, flags); 161 } 162 163 static void dw_pci_bottom_ack(struct irq_data *d) 164 { 165 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 166 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 167 unsigned int res, bit, ctrl; 168 169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 171 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 172 173 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 174 } 175 176 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 177 .name = "DWPCI-MSI", 178 .irq_ack = dw_pci_bottom_ack, 179 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 180 .irq_set_affinity = dw_pci_msi_set_affinity, 181 .irq_mask = dw_pci_bottom_mask, 182 .irq_unmask = dw_pci_bottom_unmask, 183 }; 184 185 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 186 unsigned int virq, unsigned int nr_irqs, 187 void *args) 188 { 189 struct pcie_port *pp = domain->host_data; 190 unsigned long flags; 191 u32 i; 192 int bit; 193 194 raw_spin_lock_irqsave(&pp->lock, flags); 195 196 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 197 order_base_2(nr_irqs)); 198 199 raw_spin_unlock_irqrestore(&pp->lock, flags); 200 201 if (bit < 0) 202 return -ENOSPC; 203 204 for (i = 0; i < nr_irqs; i++) 205 irq_domain_set_info(domain, virq + i, bit + i, 206 pp->msi_irq_chip, 207 pp, handle_edge_irq, 208 NULL, NULL); 209 210 return 0; 211 } 212 213 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 214 unsigned int virq, unsigned int nr_irqs) 215 { 216 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 217 struct pcie_port *pp = domain->host_data; 218 unsigned long flags; 219 220 raw_spin_lock_irqsave(&pp->lock, flags); 221 222 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 223 order_base_2(nr_irqs)); 224 225 raw_spin_unlock_irqrestore(&pp->lock, flags); 226 } 227 228 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 229 .alloc = dw_pcie_irq_domain_alloc, 230 .free = dw_pcie_irq_domain_free, 231 }; 232 233 int dw_pcie_allocate_domains(struct pcie_port *pp) 234 { 235 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 236 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 237 238 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 239 &dw_pcie_msi_domain_ops, pp); 240 if (!pp->irq_domain) { 241 dev_err(pci->dev, "Failed to create IRQ domain\n"); 242 return -ENOMEM; 243 } 244 245 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 246 247 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 248 &dw_pcie_msi_domain_info, 249 pp->irq_domain); 250 if (!pp->msi_domain) { 251 dev_err(pci->dev, "Failed to create MSI domain\n"); 252 irq_domain_remove(pp->irq_domain); 253 return -ENOMEM; 254 } 255 256 return 0; 257 } 258 259 static void dw_pcie_free_msi(struct pcie_port *pp) 260 { 261 if (pp->msi_irq) 262 irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); 263 264 irq_domain_remove(pp->msi_domain); 265 irq_domain_remove(pp->irq_domain); 266 267 if (pp->msi_data) { 268 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 269 struct device *dev = pci->dev; 270 271 dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg), 272 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 273 } 274 } 275 276 static void dw_pcie_msi_init(struct pcie_port *pp) 277 { 278 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 279 u64 msi_target = (u64)pp->msi_data; 280 281 if (!pci_msi_enabled() || !pp->has_msi_ctrl) 282 return; 283 284 /* Program the msi_data */ 285 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 286 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 287 } 288 289 int dw_pcie_host_init(struct pcie_port *pp) 290 { 291 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 292 struct device *dev = pci->dev; 293 struct device_node *np = dev->of_node; 294 struct platform_device *pdev = to_platform_device(dev); 295 struct resource_entry *win; 296 struct pci_host_bridge *bridge; 297 struct resource *cfg_res; 298 int ret; 299 300 raw_spin_lock_init(&pci->pp.lock); 301 302 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 303 if (cfg_res) { 304 pp->cfg0_size = resource_size(cfg_res); 305 pp->cfg0_base = cfg_res->start; 306 307 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res); 308 if (IS_ERR(pp->va_cfg0_base)) 309 return PTR_ERR(pp->va_cfg0_base); 310 } else { 311 dev_err(dev, "Missing *config* reg space\n"); 312 return -ENODEV; 313 } 314 315 if (!pci->dbi_base) { 316 struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 317 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); 318 if (IS_ERR(pci->dbi_base)) 319 return PTR_ERR(pci->dbi_base); 320 } 321 322 bridge = devm_pci_alloc_host_bridge(dev, 0); 323 if (!bridge) 324 return -ENOMEM; 325 326 pp->bridge = bridge; 327 328 /* Get the I/O range from DT */ 329 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 330 if (win) { 331 pp->io_size = resource_size(win->res); 332 pp->io_bus_addr = win->res->start - win->offset; 333 pp->io_base = pci_pio_to_address(win->res->start); 334 } 335 336 if (pci->link_gen < 1) 337 pci->link_gen = of_pci_get_max_link_speed(np); 338 339 if (pci_msi_enabled()) { 340 pp->has_msi_ctrl = !(pp->ops->msi_host_init || 341 of_property_read_bool(np, "msi-parent") || 342 of_property_read_bool(np, "msi-map")); 343 344 if (!pp->num_vectors) { 345 pp->num_vectors = MSI_DEF_NUM_VECTORS; 346 } else if (pp->num_vectors > MAX_MSI_IRQS) { 347 dev_err(dev, "Invalid number of vectors\n"); 348 return -EINVAL; 349 } 350 351 if (pp->ops->msi_host_init) { 352 ret = pp->ops->msi_host_init(pp); 353 if (ret < 0) 354 return ret; 355 } else if (pp->has_msi_ctrl) { 356 if (!pp->msi_irq) { 357 pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi"); 358 if (pp->msi_irq < 0) { 359 pp->msi_irq = platform_get_irq(pdev, 0); 360 if (pp->msi_irq < 0) 361 return pp->msi_irq; 362 } 363 } 364 365 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 366 367 ret = dw_pcie_allocate_domains(pp); 368 if (ret) 369 return ret; 370 371 if (pp->msi_irq > 0) 372 irq_set_chained_handler_and_data(pp->msi_irq, 373 dw_chained_msi_isr, 374 pp); 375 376 ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); 377 if (ret) 378 dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); 379 380 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, 381 sizeof(pp->msi_msg), 382 DMA_FROM_DEVICE, 383 DMA_ATTR_SKIP_CPU_SYNC); 384 if (dma_mapping_error(pci->dev, pp->msi_data)) { 385 dev_err(pci->dev, "Failed to map MSI data\n"); 386 pp->msi_data = 0; 387 goto err_free_msi; 388 } 389 } 390 } 391 392 /* Set default bus ops */ 393 bridge->ops = &dw_pcie_ops; 394 bridge->child_ops = &dw_child_pcie_ops; 395 396 if (pp->ops->host_init) { 397 ret = pp->ops->host_init(pp); 398 if (ret) 399 goto err_free_msi; 400 } 401 402 dw_pcie_setup_rc(pp); 403 dw_pcie_msi_init(pp); 404 405 if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) { 406 ret = pci->ops->start_link(pci); 407 if (ret) 408 goto err_free_msi; 409 } 410 411 /* Ignore errors, the link may come up later */ 412 dw_pcie_wait_for_link(pci); 413 414 bridge->sysdata = pp; 415 416 ret = pci_host_probe(bridge); 417 if (!ret) 418 return 0; 419 420 err_free_msi: 421 if (pp->has_msi_ctrl) 422 dw_pcie_free_msi(pp); 423 return ret; 424 } 425 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 426 427 void dw_pcie_host_deinit(struct pcie_port *pp) 428 { 429 pci_stop_root_bus(pp->bridge->bus); 430 pci_remove_root_bus(pp->bridge->bus); 431 if (pp->has_msi_ctrl) 432 dw_pcie_free_msi(pp); 433 } 434 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 435 436 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 437 unsigned int devfn, int where) 438 { 439 int type; 440 u32 busdev; 441 struct pcie_port *pp = bus->sysdata; 442 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 443 444 /* 445 * Checking whether the link is up here is a last line of defense 446 * against platforms that forward errors on the system bus as 447 * SError upon PCI configuration transactions issued when the link 448 * is down. This check is racy by definition and does not stop 449 * the system from triggering an SError if the link goes down 450 * after this check is performed. 451 */ 452 if (!dw_pcie_link_up(pci)) 453 return NULL; 454 455 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 456 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 457 458 if (pci_is_root_bus(bus->parent)) 459 type = PCIE_ATU_TYPE_CFG0; 460 else 461 type = PCIE_ATU_TYPE_CFG1; 462 463 464 dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size); 465 466 return pp->va_cfg0_base + where; 467 } 468 469 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 470 int where, int size, u32 *val) 471 { 472 int ret; 473 struct pcie_port *pp = bus->sysdata; 474 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 475 476 ret = pci_generic_config_read(bus, devfn, where, size, val); 477 478 if (!ret && pci->io_cfg_atu_shared) 479 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base, 480 pp->io_bus_addr, pp->io_size); 481 482 return ret; 483 } 484 485 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 486 int where, int size, u32 val) 487 { 488 int ret; 489 struct pcie_port *pp = bus->sysdata; 490 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 491 492 ret = pci_generic_config_write(bus, devfn, where, size, val); 493 494 if (!ret && pci->io_cfg_atu_shared) 495 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base, 496 pp->io_bus_addr, pp->io_size); 497 498 return ret; 499 } 500 501 static struct pci_ops dw_child_pcie_ops = { 502 .map_bus = dw_pcie_other_conf_map_bus, 503 .read = dw_pcie_rd_other_conf, 504 .write = dw_pcie_wr_other_conf, 505 }; 506 507 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 508 { 509 struct pcie_port *pp = bus->sysdata; 510 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 511 512 if (PCI_SLOT(devfn) > 0) 513 return NULL; 514 515 return pci->dbi_base + where; 516 } 517 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 518 519 static struct pci_ops dw_pcie_ops = { 520 .map_bus = dw_pcie_own_conf_map_bus, 521 .read = pci_generic_config_read, 522 .write = pci_generic_config_write, 523 }; 524 525 void dw_pcie_setup_rc(struct pcie_port *pp) 526 { 527 int i; 528 u32 val, ctrl, num_ctrls; 529 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 530 531 /* 532 * Enable DBI read-only registers for writing/updating configuration. 533 * Write permission gets disabled towards the end of this function. 534 */ 535 dw_pcie_dbi_ro_wr_en(pci); 536 537 dw_pcie_setup(pci); 538 539 if (pp->has_msi_ctrl) { 540 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 541 542 /* Initialize IRQ Status array */ 543 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 544 pp->irq_mask[ctrl] = ~0; 545 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 546 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 547 pp->irq_mask[ctrl]); 548 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 549 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 550 ~0); 551 } 552 } 553 554 /* Setup RC BARs */ 555 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 556 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 557 558 /* Setup interrupt pins */ 559 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 560 val &= 0xffff00ff; 561 val |= 0x00000100; 562 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 563 564 /* Setup bus numbers */ 565 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 566 val &= 0xff000000; 567 val |= 0x00ff0100; 568 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 569 570 /* Setup command register */ 571 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 572 val &= 0xffff0000; 573 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 574 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 575 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 576 577 /* Ensure all outbound windows are disabled so there are multiple matches */ 578 for (i = 0; i < pci->num_ob_windows; i++) 579 dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND); 580 581 /* 582 * If the platform provides its own child bus config accesses, it means 583 * the platform uses its own address translation component rather than 584 * ATU, so we should not program the ATU here. 585 */ 586 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 587 int atu_idx = 0; 588 struct resource_entry *entry; 589 590 /* Get last memory resource entry */ 591 resource_list_for_each_entry(entry, &pp->bridge->windows) { 592 if (resource_type(entry->res) != IORESOURCE_MEM) 593 continue; 594 595 if (pci->num_ob_windows <= ++atu_idx) 596 break; 597 598 dw_pcie_prog_outbound_atu(pci, atu_idx, 599 PCIE_ATU_TYPE_MEM, entry->res->start, 600 entry->res->start - entry->offset, 601 resource_size(entry->res)); 602 } 603 604 if (pp->io_size) { 605 if (pci->num_ob_windows > ++atu_idx) 606 dw_pcie_prog_outbound_atu(pci, atu_idx, 607 PCIE_ATU_TYPE_IO, pp->io_base, 608 pp->io_bus_addr, pp->io_size); 609 else 610 pci->io_cfg_atu_shared = true; 611 } 612 613 if (pci->num_ob_windows <= atu_idx) 614 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)", 615 pci->num_ob_windows); 616 } 617 618 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 619 620 /* Program correct class for RC */ 621 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 622 623 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 624 val |= PORT_LOGIC_SPEED_CHANGE; 625 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 626 627 dw_pcie_dbi_ro_wr_dis(pci); 628 } 629 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 630