1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/msi.h> 14 #include <linux/of_address.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci_regs.h> 17 #include <linux/platform_device.h> 18 19 #include "../../pci.h" 20 #include "pcie-designware.h" 21 22 static struct pci_ops dw_pcie_ops; 23 static struct pci_ops dw_child_pcie_ops; 24 25 static void dw_msi_ack_irq(struct irq_data *d) 26 { 27 irq_chip_ack_parent(d); 28 } 29 30 static void dw_msi_mask_irq(struct irq_data *d) 31 { 32 pci_msi_mask_irq(d); 33 irq_chip_mask_parent(d); 34 } 35 36 static void dw_msi_unmask_irq(struct irq_data *d) 37 { 38 pci_msi_unmask_irq(d); 39 irq_chip_unmask_parent(d); 40 } 41 42 static struct irq_chip dw_pcie_msi_irq_chip = { 43 .name = "PCI-MSI", 44 .irq_ack = dw_msi_ack_irq, 45 .irq_mask = dw_msi_mask_irq, 46 .irq_unmask = dw_msi_unmask_irq, 47 }; 48 49 static struct msi_domain_info dw_pcie_msi_domain_info = { 50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 52 .chip = &dw_pcie_msi_irq_chip, 53 }; 54 55 /* MSI int handler */ 56 irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) 57 { 58 int i, pos; 59 unsigned long val; 60 u32 status, num_ctrls; 61 irqreturn_t ret = IRQ_NONE; 62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 63 64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 65 66 for (i = 0; i < num_ctrls; i++) { 67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 68 (i * MSI_REG_CTRL_BLOCK_SIZE)); 69 if (!status) 70 continue; 71 72 ret = IRQ_HANDLED; 73 val = status; 74 pos = 0; 75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 76 pos)) != MAX_MSI_IRQS_PER_CTRL) { 77 generic_handle_domain_irq(pp->irq_domain, 78 (i * MAX_MSI_IRQS_PER_CTRL) + 79 pos); 80 pos++; 81 } 82 } 83 84 return ret; 85 } 86 87 /* Chained MSI interrupt service routine */ 88 static void dw_chained_msi_isr(struct irq_desc *desc) 89 { 90 struct irq_chip *chip = irq_desc_get_chip(desc); 91 struct dw_pcie_rp *pp; 92 93 chained_irq_enter(chip, desc); 94 95 pp = irq_desc_get_handler_data(desc); 96 dw_handle_msi_irq(pp); 97 98 chained_irq_exit(chip, desc); 99 } 100 101 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 102 { 103 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 104 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 105 u64 msi_target; 106 107 msi_target = (u64)pp->msi_data; 108 109 msg->address_lo = lower_32_bits(msi_target); 110 msg->address_hi = upper_32_bits(msi_target); 111 112 msg->data = d->hwirq; 113 114 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 115 (int)d->hwirq, msg->address_hi, msg->address_lo); 116 } 117 118 static int dw_pci_msi_set_affinity(struct irq_data *d, 119 const struct cpumask *mask, bool force) 120 { 121 return -EINVAL; 122 } 123 124 static void dw_pci_bottom_mask(struct irq_data *d) 125 { 126 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 128 unsigned int res, bit, ctrl; 129 unsigned long flags; 130 131 raw_spin_lock_irqsave(&pp->lock, flags); 132 133 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 134 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 135 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 136 137 pp->irq_mask[ctrl] |= BIT(bit); 138 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 139 140 raw_spin_unlock_irqrestore(&pp->lock, flags); 141 } 142 143 static void dw_pci_bottom_unmask(struct irq_data *d) 144 { 145 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 146 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 147 unsigned int res, bit, ctrl; 148 unsigned long flags; 149 150 raw_spin_lock_irqsave(&pp->lock, flags); 151 152 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 153 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 154 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 155 156 pp->irq_mask[ctrl] &= ~BIT(bit); 157 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); 158 159 raw_spin_unlock_irqrestore(&pp->lock, flags); 160 } 161 162 static void dw_pci_bottom_ack(struct irq_data *d) 163 { 164 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d); 165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 166 unsigned int res, bit, ctrl; 167 168 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 169 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 170 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 171 172 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); 173 } 174 175 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 176 .name = "DWPCI-MSI", 177 .irq_ack = dw_pci_bottom_ack, 178 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 179 .irq_set_affinity = dw_pci_msi_set_affinity, 180 .irq_mask = dw_pci_bottom_mask, 181 .irq_unmask = dw_pci_bottom_unmask, 182 }; 183 184 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 185 unsigned int virq, unsigned int nr_irqs, 186 void *args) 187 { 188 struct dw_pcie_rp *pp = domain->host_data; 189 unsigned long flags; 190 u32 i; 191 int bit; 192 193 raw_spin_lock_irqsave(&pp->lock, flags); 194 195 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 196 order_base_2(nr_irqs)); 197 198 raw_spin_unlock_irqrestore(&pp->lock, flags); 199 200 if (bit < 0) 201 return -ENOSPC; 202 203 for (i = 0; i < nr_irqs; i++) 204 irq_domain_set_info(domain, virq + i, bit + i, 205 pp->msi_irq_chip, 206 pp, handle_edge_irq, 207 NULL, NULL); 208 209 return 0; 210 } 211 212 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 213 unsigned int virq, unsigned int nr_irqs) 214 { 215 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 216 struct dw_pcie_rp *pp = domain->host_data; 217 unsigned long flags; 218 219 raw_spin_lock_irqsave(&pp->lock, flags); 220 221 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 222 order_base_2(nr_irqs)); 223 224 raw_spin_unlock_irqrestore(&pp->lock, flags); 225 } 226 227 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 228 .alloc = dw_pcie_irq_domain_alloc, 229 .free = dw_pcie_irq_domain_free, 230 }; 231 232 int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) 233 { 234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 235 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 236 237 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 238 &dw_pcie_msi_domain_ops, pp); 239 if (!pp->irq_domain) { 240 dev_err(pci->dev, "Failed to create IRQ domain\n"); 241 return -ENOMEM; 242 } 243 244 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 245 246 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 247 &dw_pcie_msi_domain_info, 248 pp->irq_domain); 249 if (!pp->msi_domain) { 250 dev_err(pci->dev, "Failed to create MSI domain\n"); 251 irq_domain_remove(pp->irq_domain); 252 return -ENOMEM; 253 } 254 255 return 0; 256 } 257 258 static void dw_pcie_free_msi(struct dw_pcie_rp *pp) 259 { 260 u32 ctrl; 261 262 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 263 if (pp->msi_irq[ctrl] > 0) 264 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 265 NULL, NULL); 266 } 267 268 irq_domain_remove(pp->msi_domain); 269 irq_domain_remove(pp->irq_domain); 270 271 if (pp->msi_data) { 272 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 273 struct device *dev = pci->dev; 274 275 dma_unmap_page(dev, pp->msi_data, PAGE_SIZE, DMA_FROM_DEVICE); 276 if (pp->msi_page) 277 __free_page(pp->msi_page); 278 } 279 } 280 281 static void dw_pcie_msi_init(struct dw_pcie_rp *pp) 282 { 283 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 284 u64 msi_target = (u64)pp->msi_data; 285 286 if (!pci_msi_enabled() || !pp->has_msi_ctrl) 287 return; 288 289 /* Program the msi_data */ 290 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); 291 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); 292 } 293 294 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) 295 { 296 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 297 struct device *dev = pci->dev; 298 struct platform_device *pdev = to_platform_device(dev); 299 u32 ctrl, max_vectors; 300 int irq; 301 302 /* Parse any "msiX" IRQs described in the devicetree */ 303 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { 304 char msi_name[] = "msiX"; 305 306 msi_name[3] = '0' + ctrl; 307 irq = platform_get_irq_byname_optional(pdev, msi_name); 308 if (irq == -ENXIO) 309 break; 310 if (irq < 0) 311 return dev_err_probe(dev, irq, 312 "Failed to parse MSI IRQ '%s'\n", 313 msi_name); 314 315 pp->msi_irq[ctrl] = irq; 316 } 317 318 /* If no "msiX" IRQs, caller should fallback to "msi" IRQ */ 319 if (ctrl == 0) 320 return -ENXIO; 321 322 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; 323 if (pp->num_vectors > max_vectors) { 324 dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n", 325 max_vectors); 326 pp->num_vectors = max_vectors; 327 } 328 if (!pp->num_vectors) 329 pp->num_vectors = max_vectors; 330 331 return 0; 332 } 333 334 static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) 335 { 336 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 337 struct device *dev = pci->dev; 338 struct platform_device *pdev = to_platform_device(dev); 339 int ret; 340 u32 ctrl, num_ctrls; 341 342 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) 343 pp->irq_mask[ctrl] = ~0; 344 345 if (!pp->msi_irq[0]) { 346 ret = dw_pcie_parse_split_msi_irq(pp); 347 if (ret < 0 && ret != -ENXIO) 348 return ret; 349 } 350 351 if (!pp->num_vectors) 352 pp->num_vectors = MSI_DEF_NUM_VECTORS; 353 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 354 355 if (!pp->msi_irq[0]) { 356 pp->msi_irq[0] = platform_get_irq_byname_optional(pdev, "msi"); 357 if (pp->msi_irq[0] < 0) { 358 pp->msi_irq[0] = platform_get_irq(pdev, 0); 359 if (pp->msi_irq[0] < 0) 360 return pp->msi_irq[0]; 361 } 362 } 363 364 dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); 365 366 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 367 368 ret = dw_pcie_allocate_domains(pp); 369 if (ret) 370 return ret; 371 372 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 373 if (pp->msi_irq[ctrl] > 0) 374 irq_set_chained_handler_and_data(pp->msi_irq[ctrl], 375 dw_chained_msi_isr, pp); 376 } 377 378 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 379 if (ret) 380 dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); 381 382 pp->msi_page = alloc_page(GFP_DMA32); 383 pp->msi_data = dma_map_page(dev, pp->msi_page, 0, 384 PAGE_SIZE, DMA_FROM_DEVICE); 385 ret = dma_mapping_error(dev, pp->msi_data); 386 if (ret) { 387 dev_err(pci->dev, "Failed to map MSI data\n"); 388 __free_page(pp->msi_page); 389 pp->msi_page = NULL; 390 pp->msi_data = 0; 391 dw_pcie_free_msi(pp); 392 393 return ret; 394 } 395 396 return 0; 397 } 398 399 int dw_pcie_host_init(struct dw_pcie_rp *pp) 400 { 401 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 402 struct device *dev = pci->dev; 403 struct device_node *np = dev->of_node; 404 struct platform_device *pdev = to_platform_device(dev); 405 struct resource_entry *win; 406 struct pci_host_bridge *bridge; 407 struct resource *res; 408 int ret; 409 410 raw_spin_lock_init(&pp->lock); 411 412 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 413 if (res) { 414 pp->cfg0_size = resource_size(res); 415 pp->cfg0_base = res->start; 416 417 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 418 if (IS_ERR(pp->va_cfg0_base)) 419 return PTR_ERR(pp->va_cfg0_base); 420 } else { 421 dev_err(dev, "Missing *config* reg space\n"); 422 return -ENODEV; 423 } 424 425 if (!pci->dbi_base) { 426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 427 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 428 if (IS_ERR(pci->dbi_base)) 429 return PTR_ERR(pci->dbi_base); 430 } 431 432 bridge = devm_pci_alloc_host_bridge(dev, 0); 433 if (!bridge) 434 return -ENOMEM; 435 436 pp->bridge = bridge; 437 438 /* Get the I/O range from DT */ 439 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); 440 if (win) { 441 pp->io_size = resource_size(win->res); 442 pp->io_bus_addr = win->res->start - win->offset; 443 pp->io_base = pci_pio_to_address(win->res->start); 444 } 445 446 if (pci->link_gen < 1) 447 pci->link_gen = of_pci_get_max_link_speed(np); 448 449 /* Set default bus ops */ 450 bridge->ops = &dw_pcie_ops; 451 bridge->child_ops = &dw_child_pcie_ops; 452 453 if (pp->ops->host_init) { 454 ret = pp->ops->host_init(pp); 455 if (ret) 456 return ret; 457 } 458 459 if (pci_msi_enabled()) { 460 pp->has_msi_ctrl = !(pp->ops->msi_host_init || 461 of_property_read_bool(np, "msi-parent") || 462 of_property_read_bool(np, "msi-map")); 463 464 /* 465 * For the has_msi_ctrl case the default assignment is handled 466 * in the dw_pcie_msi_host_init(). 467 */ 468 if (!pp->has_msi_ctrl && !pp->num_vectors) { 469 pp->num_vectors = MSI_DEF_NUM_VECTORS; 470 } else if (pp->num_vectors > MAX_MSI_IRQS) { 471 dev_err(dev, "Invalid number of vectors\n"); 472 ret = -EINVAL; 473 goto err_deinit_host; 474 } 475 476 if (pp->ops->msi_host_init) { 477 ret = pp->ops->msi_host_init(pp); 478 if (ret < 0) 479 goto err_deinit_host; 480 } else if (pp->has_msi_ctrl) { 481 ret = dw_pcie_msi_host_init(pp); 482 if (ret < 0) 483 goto err_deinit_host; 484 } 485 } 486 487 dw_pcie_version_detect(pci); 488 489 dw_pcie_iatu_detect(pci); 490 491 ret = dw_pcie_setup_rc(pp); 492 if (ret) 493 goto err_free_msi; 494 495 if (!dw_pcie_link_up(pci)) { 496 ret = dw_pcie_start_link(pci); 497 if (ret) 498 goto err_free_msi; 499 } 500 501 /* Ignore errors, the link may come up later */ 502 dw_pcie_wait_for_link(pci); 503 504 bridge->sysdata = pp; 505 506 ret = pci_host_probe(bridge); 507 if (ret) 508 goto err_stop_link; 509 510 return 0; 511 512 err_stop_link: 513 dw_pcie_stop_link(pci); 514 515 err_free_msi: 516 if (pp->has_msi_ctrl) 517 dw_pcie_free_msi(pp); 518 519 err_deinit_host: 520 if (pp->ops->host_deinit) 521 pp->ops->host_deinit(pp); 522 523 return ret; 524 } 525 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 526 527 void dw_pcie_host_deinit(struct dw_pcie_rp *pp) 528 { 529 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 530 531 pci_stop_root_bus(pp->bridge->bus); 532 pci_remove_root_bus(pp->bridge->bus); 533 534 dw_pcie_stop_link(pci); 535 536 if (pp->has_msi_ctrl) 537 dw_pcie_free_msi(pp); 538 539 if (pp->ops->host_deinit) 540 pp->ops->host_deinit(pp); 541 } 542 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 543 544 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, 545 unsigned int devfn, int where) 546 { 547 struct dw_pcie_rp *pp = bus->sysdata; 548 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 549 int type, ret; 550 u32 busdev; 551 552 /* 553 * Checking whether the link is up here is a last line of defense 554 * against platforms that forward errors on the system bus as 555 * SError upon PCI configuration transactions issued when the link 556 * is down. This check is racy by definition and does not stop 557 * the system from triggering an SError if the link goes down 558 * after this check is performed. 559 */ 560 if (!dw_pcie_link_up(pci)) 561 return NULL; 562 563 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 564 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 565 566 if (pci_is_root_bus(bus->parent)) 567 type = PCIE_ATU_TYPE_CFG0; 568 else 569 type = PCIE_ATU_TYPE_CFG1; 570 571 ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, 572 pp->cfg0_size); 573 if (ret) 574 return NULL; 575 576 return pp->va_cfg0_base + where; 577 } 578 579 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, 580 int where, int size, u32 *val) 581 { 582 struct dw_pcie_rp *pp = bus->sysdata; 583 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 584 int ret; 585 586 ret = pci_generic_config_read(bus, devfn, where, size, val); 587 if (ret != PCIBIOS_SUCCESSFUL) 588 return ret; 589 590 if (pp->cfg0_io_shared) { 591 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, 592 pp->io_base, pp->io_bus_addr, 593 pp->io_size); 594 if (ret) 595 return PCIBIOS_SET_FAILED; 596 } 597 598 return PCIBIOS_SUCCESSFUL; 599 } 600 601 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, 602 int where, int size, u32 val) 603 { 604 struct dw_pcie_rp *pp = bus->sysdata; 605 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 606 int ret; 607 608 ret = pci_generic_config_write(bus, devfn, where, size, val); 609 if (ret != PCIBIOS_SUCCESSFUL) 610 return ret; 611 612 if (pp->cfg0_io_shared) { 613 ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, 614 pp->io_base, pp->io_bus_addr, 615 pp->io_size); 616 if (ret) 617 return PCIBIOS_SET_FAILED; 618 } 619 620 return PCIBIOS_SUCCESSFUL; 621 } 622 623 static struct pci_ops dw_child_pcie_ops = { 624 .map_bus = dw_pcie_other_conf_map_bus, 625 .read = dw_pcie_rd_other_conf, 626 .write = dw_pcie_wr_other_conf, 627 }; 628 629 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) 630 { 631 struct dw_pcie_rp *pp = bus->sysdata; 632 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 633 634 if (PCI_SLOT(devfn) > 0) 635 return NULL; 636 637 return pci->dbi_base + where; 638 } 639 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); 640 641 static struct pci_ops dw_pcie_ops = { 642 .map_bus = dw_pcie_own_conf_map_bus, 643 .read = pci_generic_config_read, 644 .write = pci_generic_config_write, 645 }; 646 647 static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) 648 { 649 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 650 struct resource_entry *entry; 651 int i, ret; 652 653 /* Note the very first outbound ATU is used for CFG IOs */ 654 if (!pci->num_ob_windows) { 655 dev_err(pci->dev, "No outbound iATU found\n"); 656 return -EINVAL; 657 } 658 659 /* 660 * Ensure all outbound windows are disabled before proceeding with 661 * the MEM/IO ranges setups. 662 */ 663 for (i = 0; i < pci->num_ob_windows; i++) 664 dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i); 665 666 i = 0; 667 resource_list_for_each_entry(entry, &pp->bridge->windows) { 668 if (resource_type(entry->res) != IORESOURCE_MEM) 669 continue; 670 671 if (pci->num_ob_windows <= ++i) 672 break; 673 674 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, 675 entry->res->start, 676 entry->res->start - entry->offset, 677 resource_size(entry->res)); 678 if (ret) { 679 dev_err(pci->dev, "Failed to set MEM range %pr\n", 680 entry->res); 681 return ret; 682 } 683 } 684 685 if (pp->io_size) { 686 if (pci->num_ob_windows > ++i) { 687 ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, 688 pp->io_base, 689 pp->io_bus_addr, 690 pp->io_size); 691 if (ret) { 692 dev_err(pci->dev, "Failed to set IO range %pr\n", 693 entry->res); 694 return ret; 695 } 696 } else { 697 pp->cfg0_io_shared = true; 698 } 699 } 700 701 if (pci->num_ob_windows <= i) 702 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n", 703 pci->num_ob_windows); 704 705 return 0; 706 } 707 708 int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 709 { 710 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 711 u32 val, ctrl, num_ctrls; 712 int ret; 713 714 /* 715 * Enable DBI read-only registers for writing/updating configuration. 716 * Write permission gets disabled towards the end of this function. 717 */ 718 dw_pcie_dbi_ro_wr_en(pci); 719 720 dw_pcie_setup(pci); 721 722 if (pp->has_msi_ctrl) { 723 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 724 725 /* Initialize IRQ Status array */ 726 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 727 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + 728 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 729 pp->irq_mask[ctrl]); 730 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + 731 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 732 ~0); 733 } 734 } 735 736 dw_pcie_msi_init(pp); 737 738 /* Setup RC BARs */ 739 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 740 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 741 742 /* Setup interrupt pins */ 743 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 744 val &= 0xffff00ff; 745 val |= 0x00000100; 746 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 747 748 /* Setup bus numbers */ 749 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 750 val &= 0xff000000; 751 val |= 0x00ff0100; 752 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 753 754 /* Setup command register */ 755 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 756 val &= 0xffff0000; 757 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 758 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 759 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 760 761 /* 762 * If the platform provides its own child bus config accesses, it means 763 * the platform uses its own address translation component rather than 764 * ATU, so we should not program the ATU here. 765 */ 766 if (pp->bridge->child_ops == &dw_child_pcie_ops) { 767 ret = dw_pcie_iatu_setup(pp); 768 if (ret) 769 return ret; 770 } 771 772 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 773 774 /* Program correct class for RC */ 775 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 776 777 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 778 val |= PORT_LOGIC_SPEED_CHANGE; 779 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 780 781 dw_pcie_dbi_ro_wr_dis(pci); 782 783 return 0; 784 } 785 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 786