1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/of_address.h> 14 #include <linux/of_pci.h> 15 #include <linux/pci_regs.h> 16 #include <linux/platform_device.h> 17 18 #include "../../pci.h" 19 #include "pcie-designware.h" 20 21 static struct pci_ops dw_pcie_ops; 22 23 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 24 u32 *val) 25 { 26 struct dw_pcie *pci; 27 28 if (pp->ops->rd_own_conf) 29 return pp->ops->rd_own_conf(pp, where, size, val); 30 31 pci = to_dw_pcie_from_pp(pp); 32 return dw_pcie_read(pci->dbi_base + where, size, val); 33 } 34 35 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 36 u32 val) 37 { 38 struct dw_pcie *pci; 39 40 if (pp->ops->wr_own_conf) 41 return pp->ops->wr_own_conf(pp, where, size, val); 42 43 pci = to_dw_pcie_from_pp(pp); 44 return dw_pcie_write(pci->dbi_base + where, size, val); 45 } 46 47 static void dw_msi_ack_irq(struct irq_data *d) 48 { 49 irq_chip_ack_parent(d); 50 } 51 52 static void dw_msi_mask_irq(struct irq_data *d) 53 { 54 pci_msi_mask_irq(d); 55 irq_chip_mask_parent(d); 56 } 57 58 static void dw_msi_unmask_irq(struct irq_data *d) 59 { 60 pci_msi_unmask_irq(d); 61 irq_chip_unmask_parent(d); 62 } 63 64 static struct irq_chip dw_pcie_msi_irq_chip = { 65 .name = "PCI-MSI", 66 .irq_ack = dw_msi_ack_irq, 67 .irq_mask = dw_msi_mask_irq, 68 .irq_unmask = dw_msi_unmask_irq, 69 }; 70 71 static struct msi_domain_info dw_pcie_msi_domain_info = { 72 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 73 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 74 .chip = &dw_pcie_msi_irq_chip, 75 }; 76 77 /* MSI int handler */ 78 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 79 { 80 int i, pos, irq; 81 u32 val, num_ctrls; 82 irqreturn_t ret = IRQ_NONE; 83 84 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 85 86 for (i = 0; i < num_ctrls; i++) { 87 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + 88 (i * MSI_REG_CTRL_BLOCK_SIZE), 89 4, &val); 90 if (!val) 91 continue; 92 93 ret = IRQ_HANDLED; 94 pos = 0; 95 while ((pos = find_next_bit((unsigned long *) &val, 96 MAX_MSI_IRQS_PER_CTRL, 97 pos)) != MAX_MSI_IRQS_PER_CTRL) { 98 irq = irq_find_mapping(pp->irq_domain, 99 (i * MAX_MSI_IRQS_PER_CTRL) + 100 pos); 101 generic_handle_irq(irq); 102 pos++; 103 } 104 } 105 106 return ret; 107 } 108 109 /* Chained MSI interrupt service routine */ 110 static void dw_chained_msi_isr(struct irq_desc *desc) 111 { 112 struct irq_chip *chip = irq_desc_get_chip(desc); 113 struct pcie_port *pp; 114 115 chained_irq_enter(chip, desc); 116 117 pp = irq_desc_get_handler_data(desc); 118 dw_handle_msi_irq(pp); 119 120 chained_irq_exit(chip, desc); 121 } 122 123 static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg) 124 { 125 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 126 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 127 u64 msi_target; 128 129 if (pp->ops->get_msi_addr) 130 msi_target = pp->ops->get_msi_addr(pp); 131 else 132 msi_target = (u64)pp->msi_data; 133 134 msg->address_lo = lower_32_bits(msi_target); 135 msg->address_hi = upper_32_bits(msi_target); 136 137 if (pp->ops->get_msi_data) 138 msg->data = pp->ops->get_msi_data(pp, data->hwirq); 139 else 140 msg->data = data->hwirq; 141 142 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 143 (int)data->hwirq, msg->address_hi, msg->address_lo); 144 } 145 146 static int dw_pci_msi_set_affinity(struct irq_data *irq_data, 147 const struct cpumask *mask, bool force) 148 { 149 return -EINVAL; 150 } 151 152 static void dw_pci_bottom_mask(struct irq_data *data) 153 { 154 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 155 unsigned int res, bit, ctrl; 156 unsigned long flags; 157 158 raw_spin_lock_irqsave(&pp->lock, flags); 159 160 if (pp->ops->msi_clear_irq) { 161 pp->ops->msi_clear_irq(pp, data->hwirq); 162 } else { 163 ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; 164 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 165 bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; 166 167 pp->irq_status[ctrl] &= ~(1 << bit); 168 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, 169 ~pp->irq_status[ctrl]); 170 } 171 172 raw_spin_unlock_irqrestore(&pp->lock, flags); 173 } 174 175 static void dw_pci_bottom_unmask(struct irq_data *data) 176 { 177 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 178 unsigned int res, bit, ctrl; 179 unsigned long flags; 180 181 raw_spin_lock_irqsave(&pp->lock, flags); 182 183 if (pp->ops->msi_set_irq) { 184 pp->ops->msi_set_irq(pp, data->hwirq); 185 } else { 186 ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; 187 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 188 bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; 189 190 pp->irq_status[ctrl] |= 1 << bit; 191 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, 192 ~pp->irq_status[ctrl]); 193 } 194 195 raw_spin_unlock_irqrestore(&pp->lock, flags); 196 } 197 198 static void dw_pci_bottom_ack(struct irq_data *d) 199 { 200 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 201 unsigned int res, bit, ctrl; 202 unsigned long flags; 203 204 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 205 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 206 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 207 208 raw_spin_lock_irqsave(&pp->lock, flags); 209 210 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit); 211 212 if (pp->ops->msi_irq_ack) 213 pp->ops->msi_irq_ack(d->hwirq, pp); 214 215 raw_spin_unlock_irqrestore(&pp->lock, flags); 216 } 217 218 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 219 .name = "DWPCI-MSI", 220 .irq_ack = dw_pci_bottom_ack, 221 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 222 .irq_set_affinity = dw_pci_msi_set_affinity, 223 .irq_mask = dw_pci_bottom_mask, 224 .irq_unmask = dw_pci_bottom_unmask, 225 }; 226 227 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 228 unsigned int virq, unsigned int nr_irqs, 229 void *args) 230 { 231 struct pcie_port *pp = domain->host_data; 232 unsigned long flags; 233 u32 i; 234 int bit; 235 236 raw_spin_lock_irqsave(&pp->lock, flags); 237 238 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 239 order_base_2(nr_irqs)); 240 241 raw_spin_unlock_irqrestore(&pp->lock, flags); 242 243 if (bit < 0) 244 return -ENOSPC; 245 246 for (i = 0; i < nr_irqs; i++) 247 irq_domain_set_info(domain, virq + i, bit + i, 248 &dw_pci_msi_bottom_irq_chip, 249 pp, handle_edge_irq, 250 NULL, NULL); 251 252 return 0; 253 } 254 255 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 256 unsigned int virq, unsigned int nr_irqs) 257 { 258 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 259 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 260 unsigned long flags; 261 262 raw_spin_lock_irqsave(&pp->lock, flags); 263 264 bitmap_release_region(pp->msi_irq_in_use, data->hwirq, 265 order_base_2(nr_irqs)); 266 267 raw_spin_unlock_irqrestore(&pp->lock, flags); 268 } 269 270 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 271 .alloc = dw_pcie_irq_domain_alloc, 272 .free = dw_pcie_irq_domain_free, 273 }; 274 275 int dw_pcie_allocate_domains(struct pcie_port *pp) 276 { 277 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 278 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 279 280 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 281 &dw_pcie_msi_domain_ops, pp); 282 if (!pp->irq_domain) { 283 dev_err(pci->dev, "Failed to create IRQ domain\n"); 284 return -ENOMEM; 285 } 286 287 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 288 &dw_pcie_msi_domain_info, 289 pp->irq_domain); 290 if (!pp->msi_domain) { 291 dev_err(pci->dev, "Failed to create MSI domain\n"); 292 irq_domain_remove(pp->irq_domain); 293 return -ENOMEM; 294 } 295 296 return 0; 297 } 298 299 void dw_pcie_free_msi(struct pcie_port *pp) 300 { 301 irq_set_chained_handler(pp->msi_irq, NULL); 302 irq_set_handler_data(pp->msi_irq, NULL); 303 304 irq_domain_remove(pp->msi_domain); 305 irq_domain_remove(pp->irq_domain); 306 } 307 308 void dw_pcie_msi_init(struct pcie_port *pp) 309 { 310 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 311 struct device *dev = pci->dev; 312 struct page *page; 313 u64 msi_target; 314 315 page = alloc_page(GFP_KERNEL); 316 pp->msi_data = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 317 if (dma_mapping_error(dev, pp->msi_data)) { 318 dev_err(dev, "Failed to map MSI data\n"); 319 __free_page(page); 320 return; 321 } 322 msi_target = (u64)pp->msi_data; 323 324 /* Program the msi_data */ 325 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, 326 lower_32_bits(msi_target)); 327 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 328 upper_32_bits(msi_target)); 329 } 330 331 int dw_pcie_host_init(struct pcie_port *pp) 332 { 333 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 334 struct device *dev = pci->dev; 335 struct device_node *np = dev->of_node; 336 struct platform_device *pdev = to_platform_device(dev); 337 struct resource_entry *win, *tmp; 338 struct pci_bus *bus, *child; 339 struct pci_host_bridge *bridge; 340 struct resource *cfg_res; 341 int ret; 342 343 raw_spin_lock_init(&pci->pp.lock); 344 345 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 346 if (cfg_res) { 347 pp->cfg0_size = resource_size(cfg_res) >> 1; 348 pp->cfg1_size = resource_size(cfg_res) >> 1; 349 pp->cfg0_base = cfg_res->start; 350 pp->cfg1_base = cfg_res->start + pp->cfg0_size; 351 } else if (!pp->va_cfg0_base) { 352 dev_err(dev, "Missing *config* reg space\n"); 353 } 354 355 bridge = pci_alloc_host_bridge(0); 356 if (!bridge) 357 return -ENOMEM; 358 359 ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 360 &bridge->windows, &pp->io_base); 361 if (ret) 362 return ret; 363 364 ret = devm_request_pci_bus_resources(dev, &bridge->windows); 365 if (ret) 366 goto error; 367 368 /* Get the I/O and memory ranges from DT */ 369 resource_list_for_each_entry_safe(win, tmp, &bridge->windows) { 370 switch (resource_type(win->res)) { 371 case IORESOURCE_IO: 372 ret = devm_pci_remap_iospace(dev, win->res, 373 pp->io_base); 374 if (ret) { 375 dev_warn(dev, "Error %d: failed to map resource %pR\n", 376 ret, win->res); 377 resource_list_destroy_entry(win); 378 } else { 379 pp->io = win->res; 380 pp->io->name = "I/O"; 381 pp->io_size = resource_size(pp->io); 382 pp->io_bus_addr = pp->io->start - win->offset; 383 } 384 break; 385 case IORESOURCE_MEM: 386 pp->mem = win->res; 387 pp->mem->name = "MEM"; 388 pp->mem_size = resource_size(pp->mem); 389 pp->mem_bus_addr = pp->mem->start - win->offset; 390 break; 391 case 0: 392 pp->cfg = win->res; 393 pp->cfg0_size = resource_size(pp->cfg) >> 1; 394 pp->cfg1_size = resource_size(pp->cfg) >> 1; 395 pp->cfg0_base = pp->cfg->start; 396 pp->cfg1_base = pp->cfg->start + pp->cfg0_size; 397 break; 398 case IORESOURCE_BUS: 399 pp->busn = win->res; 400 break; 401 } 402 } 403 404 if (!pci->dbi_base) { 405 pci->dbi_base = devm_pci_remap_cfgspace(dev, 406 pp->cfg->start, 407 resource_size(pp->cfg)); 408 if (!pci->dbi_base) { 409 dev_err(dev, "Error with ioremap\n"); 410 ret = -ENOMEM; 411 goto error; 412 } 413 } 414 415 pp->mem_base = pp->mem->start; 416 417 if (!pp->va_cfg0_base) { 418 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, 419 pp->cfg0_base, pp->cfg0_size); 420 if (!pp->va_cfg0_base) { 421 dev_err(dev, "Error with ioremap in function\n"); 422 ret = -ENOMEM; 423 goto error; 424 } 425 } 426 427 if (!pp->va_cfg1_base) { 428 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev, 429 pp->cfg1_base, 430 pp->cfg1_size); 431 if (!pp->va_cfg1_base) { 432 dev_err(dev, "Error with ioremap\n"); 433 ret = -ENOMEM; 434 goto error; 435 } 436 } 437 438 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); 439 if (ret) 440 pci->num_viewport = 2; 441 442 if (IS_ENABLED(CONFIG_PCI_MSI)) { 443 /* 444 * If a specific SoC driver needs to change the 445 * default number of vectors, it needs to implement 446 * the set_num_vectors callback. 447 */ 448 if (!pp->ops->set_num_vectors) { 449 pp->num_vectors = MSI_DEF_NUM_VECTORS; 450 } else { 451 pp->ops->set_num_vectors(pp); 452 453 if (pp->num_vectors > MAX_MSI_IRQS || 454 pp->num_vectors == 0) { 455 dev_err(dev, 456 "Invalid number of vectors\n"); 457 goto error; 458 } 459 } 460 461 if (!pp->ops->msi_host_init) { 462 ret = dw_pcie_allocate_domains(pp); 463 if (ret) 464 goto error; 465 466 if (pp->msi_irq) 467 irq_set_chained_handler_and_data(pp->msi_irq, 468 dw_chained_msi_isr, 469 pp); 470 } else { 471 ret = pp->ops->msi_host_init(pp); 472 if (ret < 0) 473 goto error; 474 } 475 } 476 477 if (pp->ops->host_init) { 478 ret = pp->ops->host_init(pp); 479 if (ret) 480 goto error; 481 } 482 483 pp->root_bus_nr = pp->busn->start; 484 485 bridge->dev.parent = dev; 486 bridge->sysdata = pp; 487 bridge->busnr = pp->root_bus_nr; 488 bridge->ops = &dw_pcie_ops; 489 bridge->map_irq = of_irq_parse_and_map_pci; 490 bridge->swizzle_irq = pci_common_swizzle; 491 492 ret = pci_scan_root_bus_bridge(bridge); 493 if (ret) 494 goto error; 495 496 bus = bridge->bus; 497 498 if (pp->ops->scan_bus) 499 pp->ops->scan_bus(pp); 500 501 pci_bus_size_bridges(bus); 502 pci_bus_assign_resources(bus); 503 504 list_for_each_entry(child, &bus->children, node) 505 pcie_bus_configure_settings(child); 506 507 pci_bus_add_devices(bus); 508 return 0; 509 510 error: 511 pci_free_host_bridge(bridge); 512 return ret; 513 } 514 515 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 516 u32 devfn, int where, int size, u32 *val) 517 { 518 int ret, type; 519 u32 busdev, cfg_size; 520 u64 cpu_addr; 521 void __iomem *va_cfg_base; 522 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 523 524 if (pp->ops->rd_other_conf) 525 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); 526 527 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 528 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 529 530 if (bus->parent->number == pp->root_bus_nr) { 531 type = PCIE_ATU_TYPE_CFG0; 532 cpu_addr = pp->cfg0_base; 533 cfg_size = pp->cfg0_size; 534 va_cfg_base = pp->va_cfg0_base; 535 } else { 536 type = PCIE_ATU_TYPE_CFG1; 537 cpu_addr = pp->cfg1_base; 538 cfg_size = pp->cfg1_size; 539 va_cfg_base = pp->va_cfg1_base; 540 } 541 542 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 543 type, cpu_addr, 544 busdev, cfg_size); 545 ret = dw_pcie_read(va_cfg_base + where, size, val); 546 if (pci->num_viewport <= 2) 547 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 548 PCIE_ATU_TYPE_IO, pp->io_base, 549 pp->io_bus_addr, pp->io_size); 550 551 return ret; 552 } 553 554 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 555 u32 devfn, int where, int size, u32 val) 556 { 557 int ret, type; 558 u32 busdev, cfg_size; 559 u64 cpu_addr; 560 void __iomem *va_cfg_base; 561 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 562 563 if (pp->ops->wr_other_conf) 564 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); 565 566 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 567 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 568 569 if (bus->parent->number == pp->root_bus_nr) { 570 type = PCIE_ATU_TYPE_CFG0; 571 cpu_addr = pp->cfg0_base; 572 cfg_size = pp->cfg0_size; 573 va_cfg_base = pp->va_cfg0_base; 574 } else { 575 type = PCIE_ATU_TYPE_CFG1; 576 cpu_addr = pp->cfg1_base; 577 cfg_size = pp->cfg1_size; 578 va_cfg_base = pp->va_cfg1_base; 579 } 580 581 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 582 type, cpu_addr, 583 busdev, cfg_size); 584 ret = dw_pcie_write(va_cfg_base + where, size, val); 585 if (pci->num_viewport <= 2) 586 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 587 PCIE_ATU_TYPE_IO, pp->io_base, 588 pp->io_bus_addr, pp->io_size); 589 590 return ret; 591 } 592 593 static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, 594 int dev) 595 { 596 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 597 598 /* If there is no link, then there is no device */ 599 if (bus->number != pp->root_bus_nr) { 600 if (!dw_pcie_link_up(pci)) 601 return 0; 602 } 603 604 /* Access only one slot on each root port */ 605 if (bus->number == pp->root_bus_nr && dev > 0) 606 return 0; 607 608 return 1; 609 } 610 611 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 612 int size, u32 *val) 613 { 614 struct pcie_port *pp = bus->sysdata; 615 616 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) { 617 *val = 0xffffffff; 618 return PCIBIOS_DEVICE_NOT_FOUND; 619 } 620 621 if (bus->number == pp->root_bus_nr) 622 return dw_pcie_rd_own_conf(pp, where, size, val); 623 624 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); 625 } 626 627 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 628 int where, int size, u32 val) 629 { 630 struct pcie_port *pp = bus->sysdata; 631 632 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) 633 return PCIBIOS_DEVICE_NOT_FOUND; 634 635 if (bus->number == pp->root_bus_nr) 636 return dw_pcie_wr_own_conf(pp, where, size, val); 637 638 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); 639 } 640 641 static struct pci_ops dw_pcie_ops = { 642 .read = dw_pcie_rd_conf, 643 .write = dw_pcie_wr_conf, 644 }; 645 646 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) 647 { 648 u32 val; 649 650 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); 651 if (val == 0xffffffff) 652 return 1; 653 654 return 0; 655 } 656 657 void dw_pcie_setup_rc(struct pcie_port *pp) 658 { 659 u32 val, ctrl, num_ctrls; 660 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 661 662 dw_pcie_setup(pci); 663 664 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 665 666 /* Initialize IRQ Status array */ 667 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 668 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + 669 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 670 4, ~0); 671 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + 672 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 673 4, ~0); 674 pp->irq_status[ctrl] = 0; 675 } 676 677 /* Setup RC BARs */ 678 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 679 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 680 681 /* Setup interrupt pins */ 682 dw_pcie_dbi_ro_wr_en(pci); 683 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 684 val &= 0xffff00ff; 685 val |= 0x00000100; 686 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 687 dw_pcie_dbi_ro_wr_dis(pci); 688 689 /* Setup bus numbers */ 690 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 691 val &= 0xff000000; 692 val |= 0x00ff0100; 693 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 694 695 /* Setup command register */ 696 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 697 val &= 0xffff0000; 698 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 699 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 700 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 701 702 /* 703 * If the platform provides ->rd_other_conf, it means the platform 704 * uses its own address translation component rather than ATU, so 705 * we should not program the ATU here. 706 */ 707 if (!pp->ops->rd_other_conf) { 708 /* Get iATU unroll support */ 709 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); 710 dev_dbg(pci->dev, "iATU unroll: %s\n", 711 pci->iatu_unroll_enabled ? "enabled" : "disabled"); 712 713 if (pci->iatu_unroll_enabled && !pci->atu_base) 714 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; 715 716 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, 717 PCIE_ATU_TYPE_MEM, pp->mem_base, 718 pp->mem_bus_addr, pp->mem_size); 719 if (pci->num_viewport > 2) 720 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, 721 PCIE_ATU_TYPE_IO, pp->io_base, 722 pp->io_bus_addr, pp->io_size); 723 } 724 725 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); 726 727 /* Enable write permission for the DBI read-only register */ 728 dw_pcie_dbi_ro_wr_en(pci); 729 /* Program correct class for RC */ 730 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); 731 /* Better disable write permission right after the update */ 732 dw_pcie_dbi_ro_wr_dis(pci); 733 734 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); 735 val |= PORT_LOGIC_SPEED_CHANGE; 736 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); 737 } 738