1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe Endpoint controller driver 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/of.h> 10 11 #include "pcie-designware.h" 12 #include <linux/pci-epc.h> 13 #include <linux/pci-epf.h> 14 15 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) 16 { 17 struct pci_epc *epc = ep->epc; 18 19 pci_epc_linkup(epc); 20 } 21 EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); 22 23 void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) 24 { 25 struct pci_epc *epc = ep->epc; 26 27 pci_epc_init_notify(epc); 28 } 29 EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); 30 31 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar, 32 int flags) 33 { 34 u32 reg; 35 36 reg = PCI_BASE_ADDRESS_0 + (4 * bar); 37 dw_pcie_dbi_ro_wr_en(pci); 38 dw_pcie_writel_dbi2(pci, reg, 0x0); 39 dw_pcie_writel_dbi(pci, reg, 0x0); 40 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { 41 dw_pcie_writel_dbi2(pci, reg + 4, 0x0); 42 dw_pcie_writel_dbi(pci, reg + 4, 0x0); 43 } 44 dw_pcie_dbi_ro_wr_dis(pci); 45 } 46 47 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) 48 { 49 __dw_pcie_ep_reset_bar(pci, bar, 0); 50 } 51 52 static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, 53 struct pci_epf_header *hdr) 54 { 55 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 56 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 57 58 dw_pcie_dbi_ro_wr_en(pci); 59 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid); 60 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid); 61 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid); 62 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code); 63 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, 64 hdr->subclass_code | hdr->baseclass_code << 8); 65 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE, 66 hdr->cache_line_size); 67 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID, 68 hdr->subsys_vendor_id); 69 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id); 70 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN, 71 hdr->interrupt_pin); 72 dw_pcie_dbi_ro_wr_dis(pci); 73 74 return 0; 75 } 76 77 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar, 78 dma_addr_t cpu_addr, 79 enum dw_pcie_as_type as_type) 80 { 81 int ret; 82 u32 free_win; 83 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 84 85 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); 86 if (free_win >= ep->num_ib_windows) { 87 dev_err(pci->dev, "No free inbound window\n"); 88 return -EINVAL; 89 } 90 91 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr, 92 as_type); 93 if (ret < 0) { 94 dev_err(pci->dev, "Failed to program IB window\n"); 95 return ret; 96 } 97 98 ep->bar_to_atu[bar] = free_win; 99 set_bit(free_win, ep->ib_window_map); 100 101 return 0; 102 } 103 104 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr, 105 u64 pci_addr, size_t size) 106 { 107 u32 free_win; 108 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 109 110 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); 111 if (free_win >= ep->num_ob_windows) { 112 dev_err(pci->dev, "No free outbound window\n"); 113 return -EINVAL; 114 } 115 116 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM, 117 phys_addr, pci_addr, size); 118 119 set_bit(free_win, ep->ob_window_map); 120 ep->outbound_addr[free_win] = phys_addr; 121 122 return 0; 123 } 124 125 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, 126 struct pci_epf_bar *epf_bar) 127 { 128 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 129 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 130 enum pci_barno bar = epf_bar->barno; 131 u32 atu_index = ep->bar_to_atu[bar]; 132 133 __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags); 134 135 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); 136 clear_bit(atu_index, ep->ib_window_map); 137 ep->epf_bar[bar] = NULL; 138 } 139 140 static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, 141 struct pci_epf_bar *epf_bar) 142 { 143 int ret; 144 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 145 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 146 enum pci_barno bar = epf_bar->barno; 147 size_t size = epf_bar->size; 148 int flags = epf_bar->flags; 149 enum dw_pcie_as_type as_type; 150 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); 151 152 if (!(flags & PCI_BASE_ADDRESS_SPACE)) 153 as_type = DW_PCIE_AS_MEM; 154 else 155 as_type = DW_PCIE_AS_IO; 156 157 ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type); 158 if (ret) 159 return ret; 160 161 dw_pcie_dbi_ro_wr_en(pci); 162 163 dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1)); 164 dw_pcie_writel_dbi(pci, reg, flags); 165 166 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { 167 dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1)); 168 dw_pcie_writel_dbi(pci, reg + 4, 0); 169 } 170 171 ep->epf_bar[bar] = epf_bar; 172 dw_pcie_dbi_ro_wr_dis(pci); 173 174 return 0; 175 } 176 177 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr, 178 u32 *atu_index) 179 { 180 u32 index; 181 182 for (index = 0; index < ep->num_ob_windows; index++) { 183 if (ep->outbound_addr[index] != addr) 184 continue; 185 *atu_index = index; 186 return 0; 187 } 188 189 return -EINVAL; 190 } 191 192 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, 193 phys_addr_t addr) 194 { 195 int ret; 196 u32 atu_index; 197 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 198 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 199 200 ret = dw_pcie_find_index(ep, addr, &atu_index); 201 if (ret < 0) 202 return; 203 204 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND); 205 clear_bit(atu_index, ep->ob_window_map); 206 } 207 208 static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, 209 phys_addr_t addr, 210 u64 pci_addr, size_t size) 211 { 212 int ret; 213 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 214 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 215 216 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size); 217 if (ret) { 218 dev_err(pci->dev, "Failed to enable address\n"); 219 return ret; 220 } 221 222 return 0; 223 } 224 225 static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no) 226 { 227 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 228 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 229 u32 val, reg; 230 231 if (!ep->msi_cap) 232 return -EINVAL; 233 234 reg = ep->msi_cap + PCI_MSI_FLAGS; 235 val = dw_pcie_readw_dbi(pci, reg); 236 if (!(val & PCI_MSI_FLAGS_ENABLE)) 237 return -EINVAL; 238 239 val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; 240 241 return val; 242 } 243 244 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) 245 { 246 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 247 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 248 u32 val, reg; 249 250 if (!ep->msi_cap) 251 return -EINVAL; 252 253 reg = ep->msi_cap + PCI_MSI_FLAGS; 254 val = dw_pcie_readw_dbi(pci, reg); 255 val &= ~PCI_MSI_FLAGS_QMASK; 256 val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; 257 dw_pcie_dbi_ro_wr_en(pci); 258 dw_pcie_writew_dbi(pci, reg, val); 259 dw_pcie_dbi_ro_wr_dis(pci); 260 261 return 0; 262 } 263 264 static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) 265 { 266 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 267 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 268 u32 val, reg; 269 270 if (!ep->msix_cap) 271 return -EINVAL; 272 273 reg = ep->msix_cap + PCI_MSIX_FLAGS; 274 val = dw_pcie_readw_dbi(pci, reg); 275 if (!(val & PCI_MSIX_FLAGS_ENABLE)) 276 return -EINVAL; 277 278 val &= PCI_MSIX_FLAGS_QSIZE; 279 280 return val; 281 } 282 283 static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts, 284 enum pci_barno bir, u32 offset) 285 { 286 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 287 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 288 u32 val, reg; 289 290 if (!ep->msix_cap) 291 return -EINVAL; 292 293 dw_pcie_dbi_ro_wr_en(pci); 294 295 reg = ep->msix_cap + PCI_MSIX_FLAGS; 296 val = dw_pcie_readw_dbi(pci, reg); 297 val &= ~PCI_MSIX_FLAGS_QSIZE; 298 val |= interrupts; 299 dw_pcie_writew_dbi(pci, reg, val); 300 301 reg = ep->msix_cap + PCI_MSIX_TABLE; 302 val = offset | bir; 303 dw_pcie_writel_dbi(pci, reg, val); 304 305 reg = ep->msix_cap + PCI_MSIX_PBA; 306 val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; 307 dw_pcie_writel_dbi(pci, reg, val); 308 309 dw_pcie_dbi_ro_wr_dis(pci); 310 311 return 0; 312 } 313 314 static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, 315 enum pci_epc_irq_type type, u16 interrupt_num) 316 { 317 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 318 319 if (!ep->ops->raise_irq) 320 return -EINVAL; 321 322 return ep->ops->raise_irq(ep, func_no, type, interrupt_num); 323 } 324 325 static void dw_pcie_ep_stop(struct pci_epc *epc) 326 { 327 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 328 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 329 330 if (!pci->ops->stop_link) 331 return; 332 333 pci->ops->stop_link(pci); 334 } 335 336 static int dw_pcie_ep_start(struct pci_epc *epc) 337 { 338 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 339 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 340 341 if (!pci->ops->start_link) 342 return -EINVAL; 343 344 return pci->ops->start_link(pci); 345 } 346 347 static const struct pci_epc_features* 348 dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no) 349 { 350 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 351 352 if (!ep->ops->get_features) 353 return NULL; 354 355 return ep->ops->get_features(ep); 356 } 357 358 static const struct pci_epc_ops epc_ops = { 359 .write_header = dw_pcie_ep_write_header, 360 .set_bar = dw_pcie_ep_set_bar, 361 .clear_bar = dw_pcie_ep_clear_bar, 362 .map_addr = dw_pcie_ep_map_addr, 363 .unmap_addr = dw_pcie_ep_unmap_addr, 364 .set_msi = dw_pcie_ep_set_msi, 365 .get_msi = dw_pcie_ep_get_msi, 366 .set_msix = dw_pcie_ep_set_msix, 367 .get_msix = dw_pcie_ep_get_msix, 368 .raise_irq = dw_pcie_ep_raise_irq, 369 .start = dw_pcie_ep_start, 370 .stop = dw_pcie_ep_stop, 371 .get_features = dw_pcie_ep_get_features, 372 }; 373 374 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) 375 { 376 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 377 struct device *dev = pci->dev; 378 379 dev_err(dev, "EP cannot trigger legacy IRQs\n"); 380 381 return -EINVAL; 382 } 383 384 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, 385 u8 interrupt_num) 386 { 387 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 388 struct pci_epc *epc = ep->epc; 389 unsigned int aligned_offset; 390 u16 msg_ctrl, msg_data; 391 u32 msg_addr_lower, msg_addr_upper, reg; 392 u64 msg_addr; 393 bool has_upper; 394 int ret; 395 396 if (!ep->msi_cap) 397 return -EINVAL; 398 399 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */ 400 reg = ep->msi_cap + PCI_MSI_FLAGS; 401 msg_ctrl = dw_pcie_readw_dbi(pci, reg); 402 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT); 403 reg = ep->msi_cap + PCI_MSI_ADDRESS_LO; 404 msg_addr_lower = dw_pcie_readl_dbi(pci, reg); 405 if (has_upper) { 406 reg = ep->msi_cap + PCI_MSI_ADDRESS_HI; 407 msg_addr_upper = dw_pcie_readl_dbi(pci, reg); 408 reg = ep->msi_cap + PCI_MSI_DATA_64; 409 msg_data = dw_pcie_readw_dbi(pci, reg); 410 } else { 411 msg_addr_upper = 0; 412 reg = ep->msi_cap + PCI_MSI_DATA_32; 413 msg_data = dw_pcie_readw_dbi(pci, reg); 414 } 415 aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); 416 msg_addr = ((u64)msg_addr_upper) << 32 | 417 (msg_addr_lower & ~aligned_offset); 418 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, 419 epc->mem->window.page_size); 420 if (ret) 421 return ret; 422 423 writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); 424 425 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); 426 427 return 0; 428 } 429 430 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, 431 u16 interrupt_num) 432 { 433 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 434 struct pci_epf_msix_tbl *msix_tbl; 435 struct pci_epc *epc = ep->epc; 436 u32 reg, msg_data, vec_ctrl; 437 unsigned int aligned_offset; 438 u32 tbl_offset; 439 u64 msg_addr; 440 int ret; 441 u8 bir; 442 443 reg = ep->msix_cap + PCI_MSIX_TABLE; 444 tbl_offset = dw_pcie_readl_dbi(pci, reg); 445 bir = (tbl_offset & PCI_MSIX_TABLE_BIR); 446 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 447 448 msix_tbl = ep->epf_bar[bir]->addr + tbl_offset; 449 msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr; 450 msg_data = msix_tbl[(interrupt_num - 1)].msg_data; 451 vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl; 452 453 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) { 454 dev_dbg(pci->dev, "MSI-X entry ctrl set\n"); 455 return -EPERM; 456 } 457 458 aligned_offset = msg_addr & (epc->mem->window.page_size - 1); 459 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, 460 epc->mem->window.page_size); 461 if (ret) 462 return ret; 463 464 writel(msg_data, ep->msi_mem + aligned_offset); 465 466 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); 467 468 return 0; 469 } 470 471 void dw_pcie_ep_exit(struct dw_pcie_ep *ep) 472 { 473 struct pci_epc *epc = ep->epc; 474 475 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, 476 epc->mem->window.page_size); 477 478 pci_epc_mem_exit(epc); 479 } 480 481 static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) 482 { 483 u32 header; 484 int pos = PCI_CFG_SPACE_SIZE; 485 486 while (pos) { 487 header = dw_pcie_readl_dbi(pci, pos); 488 if (PCI_EXT_CAP_ID(header) == cap) 489 return pos; 490 491 pos = PCI_EXT_CAP_NEXT(header); 492 if (!pos) 493 break; 494 } 495 496 return 0; 497 } 498 499 int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) 500 { 501 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 502 unsigned int offset; 503 unsigned int nbars; 504 u8 hdr_type; 505 u32 reg; 506 int i; 507 508 hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); 509 if (hdr_type != PCI_HEADER_TYPE_NORMAL) { 510 dev_err(pci->dev, 511 "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", 512 hdr_type); 513 return -EIO; 514 } 515 516 ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 517 518 ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); 519 520 offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); 521 if (offset) { 522 reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); 523 nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> 524 PCI_REBAR_CTRL_NBAR_SHIFT; 525 526 dw_pcie_dbi_ro_wr_en(pci); 527 for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) 528 dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); 529 dw_pcie_dbi_ro_wr_dis(pci); 530 } 531 532 dw_pcie_setup(pci); 533 534 return 0; 535 } 536 EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); 537 538 int dw_pcie_ep_init(struct dw_pcie_ep *ep) 539 { 540 int ret; 541 void *addr; 542 struct pci_epc *epc; 543 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 544 struct device *dev = pci->dev; 545 struct device_node *np = dev->of_node; 546 const struct pci_epc_features *epc_features; 547 548 if (!pci->dbi_base || !pci->dbi_base2) { 549 dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); 550 return -EINVAL; 551 } 552 553 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); 554 if (ret < 0) { 555 dev_err(dev, "Unable to read *num-ib-windows* property\n"); 556 return ret; 557 } 558 if (ep->num_ib_windows > MAX_IATU_IN) { 559 dev_err(dev, "Invalid *num-ib-windows*\n"); 560 return -EINVAL; 561 } 562 563 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); 564 if (ret < 0) { 565 dev_err(dev, "Unable to read *num-ob-windows* property\n"); 566 return ret; 567 } 568 if (ep->num_ob_windows > MAX_IATU_OUT) { 569 dev_err(dev, "Invalid *num-ob-windows*\n"); 570 return -EINVAL; 571 } 572 573 ep->ib_window_map = devm_kcalloc(dev, 574 BITS_TO_LONGS(ep->num_ib_windows), 575 sizeof(long), 576 GFP_KERNEL); 577 if (!ep->ib_window_map) 578 return -ENOMEM; 579 580 ep->ob_window_map = devm_kcalloc(dev, 581 BITS_TO_LONGS(ep->num_ob_windows), 582 sizeof(long), 583 GFP_KERNEL); 584 if (!ep->ob_window_map) 585 return -ENOMEM; 586 587 addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t), 588 GFP_KERNEL); 589 if (!addr) 590 return -ENOMEM; 591 ep->outbound_addr = addr; 592 593 epc = devm_pci_epc_create(dev, &epc_ops); 594 if (IS_ERR(epc)) { 595 dev_err(dev, "Failed to create epc device\n"); 596 return PTR_ERR(epc); 597 } 598 599 ep->epc = epc; 600 epc_set_drvdata(epc, ep); 601 602 if (ep->ops->ep_init) 603 ep->ops->ep_init(ep); 604 605 ret = of_property_read_u8(np, "max-functions", &epc->max_functions); 606 if (ret < 0) 607 epc->max_functions = 1; 608 609 ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, 610 ep->page_size); 611 if (ret < 0) { 612 dev_err(dev, "Failed to initialize address space\n"); 613 return ret; 614 } 615 616 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, 617 epc->mem->window.page_size); 618 if (!ep->msi_mem) { 619 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); 620 return -ENOMEM; 621 } 622 623 if (ep->ops->get_features) { 624 epc_features = ep->ops->get_features(ep); 625 if (epc_features->core_init_notifier) 626 return 0; 627 } 628 629 return dw_pcie_ep_init_complete(ep); 630 } 631 EXPORT_SYMBOL_GPL(dw_pcie_ep_init); 632