1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * Synopsys DesignWare PCIe Endpoint controller driver 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/of.h> 10 11 #include "pcie-designware.h" 12 #include <linux/pci-epc.h> 13 #include <linux/pci-epf.h> 14 15 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) 16 { 17 struct pci_epc *epc = ep->epc; 18 19 pci_epc_linkup(epc); 20 } 21 22 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar, 23 int flags) 24 { 25 u32 reg; 26 27 reg = PCI_BASE_ADDRESS_0 + (4 * bar); 28 dw_pcie_dbi_ro_wr_en(pci); 29 dw_pcie_writel_dbi2(pci, reg, 0x0); 30 dw_pcie_writel_dbi(pci, reg, 0x0); 31 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { 32 dw_pcie_writel_dbi2(pci, reg + 4, 0x0); 33 dw_pcie_writel_dbi(pci, reg + 4, 0x0); 34 } 35 dw_pcie_dbi_ro_wr_dis(pci); 36 } 37 38 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) 39 { 40 __dw_pcie_ep_reset_bar(pci, bar, 0); 41 } 42 43 static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, 44 u8 cap) 45 { 46 u8 cap_id, next_cap_ptr; 47 u16 reg; 48 49 reg = dw_pcie_readw_dbi(pci, cap_ptr); 50 next_cap_ptr = (reg & 0xff00) >> 8; 51 cap_id = (reg & 0x00ff); 52 53 if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) 54 return 0; 55 56 if (cap_id == cap) 57 return cap_ptr; 58 59 return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); 60 } 61 62 static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) 63 { 64 u8 next_cap_ptr; 65 u16 reg; 66 67 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); 68 next_cap_ptr = (reg & 0x00ff); 69 70 if (!next_cap_ptr) 71 return 0; 72 73 return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); 74 } 75 76 static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, 77 struct pci_epf_header *hdr) 78 { 79 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 80 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 81 82 dw_pcie_dbi_ro_wr_en(pci); 83 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid); 84 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid); 85 dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid); 86 dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code); 87 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, 88 hdr->subclass_code | hdr->baseclass_code << 8); 89 dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE, 90 hdr->cache_line_size); 91 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID, 92 hdr->subsys_vendor_id); 93 dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id); 94 dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN, 95 hdr->interrupt_pin); 96 dw_pcie_dbi_ro_wr_dis(pci); 97 98 return 0; 99 } 100 101 static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar, 102 dma_addr_t cpu_addr, 103 enum dw_pcie_as_type as_type) 104 { 105 int ret; 106 u32 free_win; 107 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 108 109 free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); 110 if (free_win >= ep->num_ib_windows) { 111 dev_err(pci->dev, "No free inbound window\n"); 112 return -EINVAL; 113 } 114 115 ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr, 116 as_type); 117 if (ret < 0) { 118 dev_err(pci->dev, "Failed to program IB window\n"); 119 return ret; 120 } 121 122 ep->bar_to_atu[bar] = free_win; 123 set_bit(free_win, ep->ib_window_map); 124 125 return 0; 126 } 127 128 static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr, 129 u64 pci_addr, size_t size) 130 { 131 u32 free_win; 132 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 133 134 free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); 135 if (free_win >= ep->num_ob_windows) { 136 dev_err(pci->dev, "No free outbound window\n"); 137 return -EINVAL; 138 } 139 140 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM, 141 phys_addr, pci_addr, size); 142 143 set_bit(free_win, ep->ob_window_map); 144 ep->outbound_addr[free_win] = phys_addr; 145 146 return 0; 147 } 148 149 static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, 150 struct pci_epf_bar *epf_bar) 151 { 152 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 153 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 154 enum pci_barno bar = epf_bar->barno; 155 u32 atu_index = ep->bar_to_atu[bar]; 156 157 __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags); 158 159 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); 160 clear_bit(atu_index, ep->ib_window_map); 161 } 162 163 static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, 164 struct pci_epf_bar *epf_bar) 165 { 166 int ret; 167 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 168 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 169 enum pci_barno bar = epf_bar->barno; 170 size_t size = epf_bar->size; 171 int flags = epf_bar->flags; 172 enum dw_pcie_as_type as_type; 173 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); 174 175 if (!(flags & PCI_BASE_ADDRESS_SPACE)) 176 as_type = DW_PCIE_AS_MEM; 177 else 178 as_type = DW_PCIE_AS_IO; 179 180 ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type); 181 if (ret) 182 return ret; 183 184 dw_pcie_dbi_ro_wr_en(pci); 185 186 dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1)); 187 dw_pcie_writel_dbi(pci, reg, flags); 188 189 if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { 190 dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1)); 191 dw_pcie_writel_dbi(pci, reg + 4, 0); 192 } 193 194 dw_pcie_dbi_ro_wr_dis(pci); 195 196 return 0; 197 } 198 199 static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr, 200 u32 *atu_index) 201 { 202 u32 index; 203 204 for (index = 0; index < ep->num_ob_windows; index++) { 205 if (ep->outbound_addr[index] != addr) 206 continue; 207 *atu_index = index; 208 return 0; 209 } 210 211 return -EINVAL; 212 } 213 214 static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no, 215 phys_addr_t addr) 216 { 217 int ret; 218 u32 atu_index; 219 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 220 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 221 222 ret = dw_pcie_find_index(ep, addr, &atu_index); 223 if (ret < 0) 224 return; 225 226 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND); 227 clear_bit(atu_index, ep->ob_window_map); 228 } 229 230 static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, 231 phys_addr_t addr, 232 u64 pci_addr, size_t size) 233 { 234 int ret; 235 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 236 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 237 238 ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size); 239 if (ret) { 240 dev_err(pci->dev, "Failed to enable address\n"); 241 return ret; 242 } 243 244 return 0; 245 } 246 247 static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no) 248 { 249 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 250 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 251 u32 val, reg; 252 253 if (!ep->msi_cap) 254 return -EINVAL; 255 256 reg = ep->msi_cap + PCI_MSI_FLAGS; 257 val = dw_pcie_readw_dbi(pci, reg); 258 if (!(val & PCI_MSI_FLAGS_ENABLE)) 259 return -EINVAL; 260 261 val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; 262 263 return val; 264 } 265 266 static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) 267 { 268 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 269 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 270 u32 val, reg; 271 272 if (!ep->msi_cap) 273 return -EINVAL; 274 275 reg = ep->msi_cap + PCI_MSI_FLAGS; 276 val = dw_pcie_readw_dbi(pci, reg); 277 val &= ~PCI_MSI_FLAGS_QMASK; 278 val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; 279 dw_pcie_dbi_ro_wr_en(pci); 280 dw_pcie_writew_dbi(pci, reg, val); 281 dw_pcie_dbi_ro_wr_dis(pci); 282 283 return 0; 284 } 285 286 static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) 287 { 288 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 289 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 290 u32 val, reg; 291 292 if (!ep->msix_cap) 293 return -EINVAL; 294 295 reg = ep->msix_cap + PCI_MSIX_FLAGS; 296 val = dw_pcie_readw_dbi(pci, reg); 297 if (!(val & PCI_MSIX_FLAGS_ENABLE)) 298 return -EINVAL; 299 300 val &= PCI_MSIX_FLAGS_QSIZE; 301 302 return val; 303 } 304 305 static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts) 306 { 307 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 308 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 309 u32 val, reg; 310 311 if (!ep->msix_cap) 312 return -EINVAL; 313 314 reg = ep->msix_cap + PCI_MSIX_FLAGS; 315 val = dw_pcie_readw_dbi(pci, reg); 316 val &= ~PCI_MSIX_FLAGS_QSIZE; 317 val |= interrupts; 318 dw_pcie_dbi_ro_wr_en(pci); 319 dw_pcie_writew_dbi(pci, reg, val); 320 dw_pcie_dbi_ro_wr_dis(pci); 321 322 return 0; 323 } 324 325 static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, 326 enum pci_epc_irq_type type, u16 interrupt_num) 327 { 328 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 329 330 if (!ep->ops->raise_irq) 331 return -EINVAL; 332 333 return ep->ops->raise_irq(ep, func_no, type, interrupt_num); 334 } 335 336 static void dw_pcie_ep_stop(struct pci_epc *epc) 337 { 338 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 339 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 340 341 if (!pci->ops->stop_link) 342 return; 343 344 pci->ops->stop_link(pci); 345 } 346 347 static int dw_pcie_ep_start(struct pci_epc *epc) 348 { 349 struct dw_pcie_ep *ep = epc_get_drvdata(epc); 350 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 351 352 if (!pci->ops->start_link) 353 return -EINVAL; 354 355 return pci->ops->start_link(pci); 356 } 357 358 static const struct pci_epc_ops epc_ops = { 359 .write_header = dw_pcie_ep_write_header, 360 .set_bar = dw_pcie_ep_set_bar, 361 .clear_bar = dw_pcie_ep_clear_bar, 362 .map_addr = dw_pcie_ep_map_addr, 363 .unmap_addr = dw_pcie_ep_unmap_addr, 364 .set_msi = dw_pcie_ep_set_msi, 365 .get_msi = dw_pcie_ep_get_msi, 366 .set_msix = dw_pcie_ep_set_msix, 367 .get_msix = dw_pcie_ep_get_msix, 368 .raise_irq = dw_pcie_ep_raise_irq, 369 .start = dw_pcie_ep_start, 370 .stop = dw_pcie_ep_stop, 371 }; 372 373 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) 374 { 375 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 376 struct device *dev = pci->dev; 377 378 dev_err(dev, "EP cannot trigger legacy IRQs\n"); 379 380 return -EINVAL; 381 } 382 383 int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, 384 u8 interrupt_num) 385 { 386 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 387 struct pci_epc *epc = ep->epc; 388 u16 msg_ctrl, msg_data; 389 u32 msg_addr_lower, msg_addr_upper, reg; 390 u64 msg_addr; 391 bool has_upper; 392 int ret; 393 394 if (!ep->msi_cap) 395 return -EINVAL; 396 397 /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */ 398 reg = ep->msi_cap + PCI_MSI_FLAGS; 399 msg_ctrl = dw_pcie_readw_dbi(pci, reg); 400 has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT); 401 reg = ep->msi_cap + PCI_MSI_ADDRESS_LO; 402 msg_addr_lower = dw_pcie_readl_dbi(pci, reg); 403 if (has_upper) { 404 reg = ep->msi_cap + PCI_MSI_ADDRESS_HI; 405 msg_addr_upper = dw_pcie_readl_dbi(pci, reg); 406 reg = ep->msi_cap + PCI_MSI_DATA_64; 407 msg_data = dw_pcie_readw_dbi(pci, reg); 408 } else { 409 msg_addr_upper = 0; 410 reg = ep->msi_cap + PCI_MSI_DATA_32; 411 msg_data = dw_pcie_readw_dbi(pci, reg); 412 } 413 msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; 414 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, 415 epc->mem->page_size); 416 if (ret) 417 return ret; 418 419 writel(msg_data | (interrupt_num - 1), ep->msi_mem); 420 421 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); 422 423 return 0; 424 } 425 426 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, 427 u16 interrupt_num) 428 { 429 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 430 struct pci_epc *epc = ep->epc; 431 u16 tbl_offset, bir; 432 u32 bar_addr_upper, bar_addr_lower; 433 u32 msg_addr_upper, msg_addr_lower; 434 u32 reg, msg_data, vec_ctrl; 435 u64 tbl_addr, msg_addr, reg_u64; 436 void __iomem *msix_tbl; 437 int ret; 438 439 reg = ep->msix_cap + PCI_MSIX_TABLE; 440 tbl_offset = dw_pcie_readl_dbi(pci, reg); 441 bir = (tbl_offset & PCI_MSIX_TABLE_BIR); 442 tbl_offset &= PCI_MSIX_TABLE_OFFSET; 443 444 reg = PCI_BASE_ADDRESS_0 + (4 * bir); 445 bar_addr_upper = 0; 446 bar_addr_lower = dw_pcie_readl_dbi(pci, reg); 447 reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK); 448 if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64) 449 bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4); 450 451 tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower; 452 tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE)); 453 tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK; 454 455 msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr, 456 PCI_MSIX_ENTRY_SIZE); 457 if (!msix_tbl) 458 return -EINVAL; 459 460 msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR); 461 msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR); 462 msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; 463 msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA); 464 vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL); 465 466 iounmap(msix_tbl); 467 468 if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT) 469 return -EPERM; 470 471 ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, 472 epc->mem->page_size); 473 if (ret) 474 return ret; 475 476 writel(msg_data, ep->msi_mem); 477 478 dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); 479 480 return 0; 481 } 482 483 void dw_pcie_ep_exit(struct dw_pcie_ep *ep) 484 { 485 struct pci_epc *epc = ep->epc; 486 487 pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, 488 epc->mem->page_size); 489 490 pci_epc_mem_exit(epc); 491 } 492 493 int dw_pcie_ep_init(struct dw_pcie_ep *ep) 494 { 495 int ret; 496 void *addr; 497 struct pci_epc *epc; 498 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 499 struct device *dev = pci->dev; 500 struct device_node *np = dev->of_node; 501 502 if (!pci->dbi_base || !pci->dbi_base2) { 503 dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); 504 return -EINVAL; 505 } 506 if (pci->iatu_unroll_enabled && !pci->atu_base) { 507 dev_err(dev, "atu_base is not populated\n"); 508 return -EINVAL; 509 } 510 511 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); 512 if (ret < 0) { 513 dev_err(dev, "Unable to read *num-ib-windows* property\n"); 514 return ret; 515 } 516 if (ep->num_ib_windows > MAX_IATU_IN) { 517 dev_err(dev, "Invalid *num-ib-windows*\n"); 518 return -EINVAL; 519 } 520 521 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); 522 if (ret < 0) { 523 dev_err(dev, "Unable to read *num-ob-windows* property\n"); 524 return ret; 525 } 526 if (ep->num_ob_windows > MAX_IATU_OUT) { 527 dev_err(dev, "Invalid *num-ob-windows*\n"); 528 return -EINVAL; 529 } 530 531 ep->ib_window_map = devm_kcalloc(dev, 532 BITS_TO_LONGS(ep->num_ib_windows), 533 sizeof(long), 534 GFP_KERNEL); 535 if (!ep->ib_window_map) 536 return -ENOMEM; 537 538 ep->ob_window_map = devm_kcalloc(dev, 539 BITS_TO_LONGS(ep->num_ob_windows), 540 sizeof(long), 541 GFP_KERNEL); 542 if (!ep->ob_window_map) 543 return -ENOMEM; 544 545 addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t), 546 GFP_KERNEL); 547 if (!addr) 548 return -ENOMEM; 549 ep->outbound_addr = addr; 550 551 epc = devm_pci_epc_create(dev, &epc_ops); 552 if (IS_ERR(epc)) { 553 dev_err(dev, "Failed to create epc device\n"); 554 return PTR_ERR(epc); 555 } 556 557 ep->epc = epc; 558 epc_set_drvdata(epc, ep); 559 560 if (ep->ops->ep_init) 561 ep->ops->ep_init(ep); 562 563 ret = of_property_read_u8(np, "max-functions", &epc->max_functions); 564 if (ret < 0) 565 epc->max_functions = 1; 566 567 ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, 568 ep->page_size); 569 if (ret < 0) { 570 dev_err(dev, "Failed to initialize address space\n"); 571 return ret; 572 } 573 574 ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, 575 epc->mem->page_size); 576 if (!ep->msi_mem) { 577 dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); 578 return -ENOMEM; 579 } 580 ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI); 581 582 ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); 583 584 dw_pcie_setup(pci); 585 586 return 0; 587 } 588