1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Marvell Armada-8K SoCs 4 * 5 * Armada-8K PCIe Glue Layer Source Code 6 * 7 * Copyright (C) 2016 Marvell Technology Group Ltd. 8 * 9 * Author: Yehuda Yitshak <yehuday@marvell.com> 10 * Author: Shadi Ammouri <shadi@marvell.com> 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/of.h> 19 #include <linux/pci.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/resource.h> 23 #include <linux/of_pci.h> 24 #include <linux/of_irq.h> 25 26 #include "pcie-designware.h" 27 28 #define ARMADA8K_PCIE_MAX_LANES PCIE_LNK_X4 29 30 struct armada8k_pcie { 31 struct dw_pcie *pci; 32 struct clk *clk; 33 struct clk *clk_reg; 34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; 35 unsigned int phy_count; 36 }; 37 38 #define PCIE_VENDOR_REGS_OFFSET 0x8000 39 40 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0) 41 #define PCIE_APP_LTSSM_EN BIT(2) 42 #define PCIE_DEVICE_TYPE_SHIFT 4 43 #define PCIE_DEVICE_TYPE_MASK 0xF 44 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ 45 46 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8) 47 #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) 48 #define PCIE_GLB_STS_PHY_LINK_UP BIT(9) 49 50 #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) 51 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) 52 #define PCIE_INT_A_ASSERT_MASK BIT(9) 53 #define PCIE_INT_B_ASSERT_MASK BIT(10) 54 #define PCIE_INT_C_ASSERT_MASK BIT(11) 55 #define PCIE_INT_D_ASSERT_MASK BIT(12) 56 57 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) 58 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) 59 #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C) 60 #define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60) 61 /* 62 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write 63 * allocate 64 */ 65 #define ARCACHE_DEFAULT_VALUE 0x3511 66 #define AWCACHE_DEFAULT_VALUE 0x5311 67 68 #define DOMAIN_OUTER_SHAREABLE 0x2 69 #define AX_USER_DOMAIN_MASK 0x3 70 #define AX_USER_DOMAIN_SHIFT 4 71 72 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) 73 74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) 75 { 76 int i; 77 78 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 79 phy_power_off(pcie->phy[i]); 80 phy_exit(pcie->phy[i]); 81 } 82 } 83 84 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) 85 { 86 int ret; 87 int i; 88 89 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 90 ret = phy_init(pcie->phy[i]); 91 if (ret) 92 return ret; 93 94 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, 95 pcie->phy_count); 96 if (ret) { 97 phy_exit(pcie->phy[i]); 98 return ret; 99 } 100 101 ret = phy_power_on(pcie->phy[i]); 102 if (ret) { 103 phy_exit(pcie->phy[i]); 104 return ret; 105 } 106 } 107 108 return 0; 109 } 110 111 static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie) 112 { 113 struct dw_pcie *pci = pcie->pci; 114 struct device *dev = pci->dev; 115 struct device_node *node = dev->of_node; 116 int ret = 0; 117 int i; 118 119 for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) { 120 pcie->phy[i] = devm_of_phy_get_by_index(dev, node, i); 121 if (IS_ERR(pcie->phy[i]) && 122 (PTR_ERR(pcie->phy[i]) == -EPROBE_DEFER)) 123 return PTR_ERR(pcie->phy[i]); 124 125 if (IS_ERR(pcie->phy[i])) { 126 pcie->phy[i] = NULL; 127 continue; 128 } 129 130 pcie->phy_count++; 131 } 132 133 /* Old bindings miss the PHY handle, so just warn if there is no PHY */ 134 if (!pcie->phy_count) 135 dev_warn(dev, "No available PHY\n"); 136 137 ret = armada8k_pcie_enable_phys(pcie); 138 if (ret) 139 dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret); 140 141 return ret; 142 } 143 144 static int armada8k_pcie_link_up(struct dw_pcie *pci) 145 { 146 u32 reg; 147 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 148 149 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); 150 151 if ((reg & mask) == mask) 152 return 1; 153 154 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); 155 return 0; 156 } 157 158 static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) 159 { 160 struct dw_pcie *pci = pcie->pci; 161 u32 reg; 162 163 if (!dw_pcie_link_up(pci)) { 164 /* Disable LTSSM state machine to enable configuration */ 165 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 166 reg &= ~(PCIE_APP_LTSSM_EN); 167 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 168 } 169 170 /* Set the device to root complex mode */ 171 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 172 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); 173 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; 174 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 175 176 /* Set the PCIe master AxCache attributes */ 177 dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); 178 dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); 179 180 /* Set the PCIe master AxDomain attributes */ 181 reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); 182 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 183 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 184 dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); 185 186 reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); 187 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 188 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 189 dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); 190 191 /* Enable INT A-D interrupts */ 192 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); 193 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | 194 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; 195 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); 196 197 if (!dw_pcie_link_up(pci)) { 198 /* Configuration done. Start LTSSM */ 199 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); 200 reg |= PCIE_APP_LTSSM_EN; 201 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); 202 } 203 204 /* Wait until the link becomes active again */ 205 if (dw_pcie_wait_for_link(pci)) 206 dev_err(pci->dev, "Link not up after reconfiguration\n"); 207 } 208 209 static int armada8k_pcie_host_init(struct pcie_port *pp) 210 { 211 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 212 struct armada8k_pcie *pcie = to_armada8k_pcie(pci); 213 214 dw_pcie_setup_rc(pp); 215 armada8k_pcie_establish_link(pcie); 216 217 return 0; 218 } 219 220 static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) 221 { 222 struct armada8k_pcie *pcie = arg; 223 struct dw_pcie *pci = pcie->pci; 224 u32 val; 225 226 /* 227 * Interrupts are directly handled by the device driver of the 228 * PCI device. However, they are also latched into the PCIe 229 * controller, so we simply discard them. 230 */ 231 val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); 232 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); 233 234 return IRQ_HANDLED; 235 } 236 237 static const struct dw_pcie_host_ops armada8k_pcie_host_ops = { 238 .host_init = armada8k_pcie_host_init, 239 }; 240 241 static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, 242 struct platform_device *pdev) 243 { 244 struct dw_pcie *pci = pcie->pci; 245 struct pcie_port *pp = &pci->pp; 246 struct device *dev = &pdev->dev; 247 int ret; 248 249 pp->ops = &armada8k_pcie_host_ops; 250 251 pp->irq = platform_get_irq(pdev, 0); 252 if (pp->irq < 0) { 253 dev_err(dev, "failed to get irq for port\n"); 254 return pp->irq; 255 } 256 257 ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler, 258 IRQF_SHARED, "armada8k-pcie", pcie); 259 if (ret) { 260 dev_err(dev, "failed to request irq %d\n", pp->irq); 261 return ret; 262 } 263 264 ret = dw_pcie_host_init(pp); 265 if (ret) { 266 dev_err(dev, "failed to initialize host: %d\n", ret); 267 return ret; 268 } 269 270 return 0; 271 } 272 273 static const struct dw_pcie_ops dw_pcie_ops = { 274 .link_up = armada8k_pcie_link_up, 275 }; 276 277 static int armada8k_pcie_probe(struct platform_device *pdev) 278 { 279 struct dw_pcie *pci; 280 struct armada8k_pcie *pcie; 281 struct device *dev = &pdev->dev; 282 struct resource *base; 283 int ret; 284 285 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 286 if (!pcie) 287 return -ENOMEM; 288 289 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 290 if (!pci) 291 return -ENOMEM; 292 293 pci->dev = dev; 294 pci->ops = &dw_pcie_ops; 295 296 pcie->pci = pci; 297 298 pcie->clk = devm_clk_get(dev, NULL); 299 if (IS_ERR(pcie->clk)) 300 return PTR_ERR(pcie->clk); 301 302 ret = clk_prepare_enable(pcie->clk); 303 if (ret) 304 return ret; 305 306 pcie->clk_reg = devm_clk_get(dev, "reg"); 307 if (pcie->clk_reg == ERR_PTR(-EPROBE_DEFER)) { 308 ret = -EPROBE_DEFER; 309 goto fail; 310 } 311 if (!IS_ERR(pcie->clk_reg)) { 312 ret = clk_prepare_enable(pcie->clk_reg); 313 if (ret) 314 goto fail_clkreg; 315 } 316 317 /* Get the dw-pcie unit configuration/control registers base. */ 318 base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); 319 pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); 320 if (IS_ERR(pci->dbi_base)) { 321 dev_err(dev, "couldn't remap regs base %p\n", base); 322 ret = PTR_ERR(pci->dbi_base); 323 goto fail_clkreg; 324 } 325 326 ret = armada8k_pcie_setup_phys(pcie); 327 if (ret) 328 goto fail_clkreg; 329 330 platform_set_drvdata(pdev, pcie); 331 332 ret = armada8k_add_pcie_port(pcie, pdev); 333 if (ret) 334 goto disable_phy; 335 336 return 0; 337 338 disable_phy: 339 armada8k_pcie_disable_phys(pcie); 340 fail_clkreg: 341 clk_disable_unprepare(pcie->clk_reg); 342 fail: 343 clk_disable_unprepare(pcie->clk); 344 345 return ret; 346 } 347 348 static const struct of_device_id armada8k_pcie_of_match[] = { 349 { .compatible = "marvell,armada8k-pcie", }, 350 {}, 351 }; 352 353 static struct platform_driver armada8k_pcie_driver = { 354 .probe = armada8k_pcie_probe, 355 .driver = { 356 .name = "armada8k-pcie", 357 .of_match_table = of_match_ptr(armada8k_pcie_of_match), 358 .suppress_bind_attrs = true, 359 }, 360 }; 361 builtin_platform_driver(armada8k_pcie_driver); 362