1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Amlogic MESON SoCs 4 * 5 * Copyright (c) 2018 Amlogic, inc. 6 * Author: Yue Wang <yue.wang@amlogic.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/of_device.h> 13 #include <linux/of_gpio.h> 14 #include <linux/pci.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <linux/resource.h> 18 #include <linux/types.h> 19 #include <linux/phy/phy.h> 20 21 #include "pcie-designware.h" 22 23 #define to_meson_pcie(x) dev_get_drvdata((x)->dev) 24 25 #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) 26 #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) 27 28 /* PCIe specific config registers */ 29 #define PCIE_CFG0 0x0 30 #define APP_LTSSM_ENABLE BIT(7) 31 32 #define PCIE_CFG_STATUS12 0x30 33 #define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) 34 #define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) 35 #define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11) 36 37 #define PCIE_CFG_STATUS17 0x44 38 #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1) 39 40 #define WAIT_LINKUP_TIMEOUT 4000 41 #define PORT_CLK_RATE 100000000UL 42 #define MAX_PAYLOAD_SIZE 256 43 #define MAX_READ_REQ_SIZE 256 44 #define PCIE_RESET_DELAY 500 45 #define PCIE_SHARED_RESET 1 46 #define PCIE_NORMAL_RESET 0 47 48 enum pcie_data_rate { 49 PCIE_GEN1, 50 PCIE_GEN2, 51 PCIE_GEN3, 52 PCIE_GEN4 53 }; 54 55 struct meson_pcie_clk_res { 56 struct clk *clk; 57 struct clk *port_clk; 58 struct clk *general_clk; 59 }; 60 61 struct meson_pcie_rc_reset { 62 struct reset_control *port; 63 struct reset_control *apb; 64 }; 65 66 struct meson_pcie { 67 struct dw_pcie pci; 68 void __iomem *cfg_base; 69 struct meson_pcie_clk_res clk_res; 70 struct meson_pcie_rc_reset mrst; 71 struct gpio_desc *reset_gpio; 72 struct phy *phy; 73 }; 74 75 static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp, 76 const char *id, 77 u32 reset_type) 78 { 79 struct device *dev = mp->pci.dev; 80 struct reset_control *reset; 81 82 if (reset_type == PCIE_SHARED_RESET) 83 reset = devm_reset_control_get_shared(dev, id); 84 else 85 reset = devm_reset_control_get(dev, id); 86 87 return reset; 88 } 89 90 static int meson_pcie_get_resets(struct meson_pcie *mp) 91 { 92 struct meson_pcie_rc_reset *mrst = &mp->mrst; 93 94 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET); 95 if (IS_ERR(mrst->port)) 96 return PTR_ERR(mrst->port); 97 reset_control_deassert(mrst->port); 98 99 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET); 100 if (IS_ERR(mrst->apb)) 101 return PTR_ERR(mrst->apb); 102 reset_control_deassert(mrst->apb); 103 104 return 0; 105 } 106 107 static int meson_pcie_get_mems(struct platform_device *pdev, 108 struct meson_pcie *mp) 109 { 110 struct dw_pcie *pci = &mp->pci; 111 112 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); 113 if (IS_ERR(pci->dbi_base)) 114 return PTR_ERR(pci->dbi_base); 115 116 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); 117 if (IS_ERR(mp->cfg_base)) 118 return PTR_ERR(mp->cfg_base); 119 120 return 0; 121 } 122 123 static int meson_pcie_power_on(struct meson_pcie *mp) 124 { 125 int ret = 0; 126 127 ret = phy_init(mp->phy); 128 if (ret) 129 return ret; 130 131 ret = phy_power_on(mp->phy); 132 if (ret) { 133 phy_exit(mp->phy); 134 return ret; 135 } 136 137 return 0; 138 } 139 140 static void meson_pcie_power_off(struct meson_pcie *mp) 141 { 142 phy_power_off(mp->phy); 143 phy_exit(mp->phy); 144 } 145 146 static int meson_pcie_reset(struct meson_pcie *mp) 147 { 148 struct meson_pcie_rc_reset *mrst = &mp->mrst; 149 int ret = 0; 150 151 ret = phy_reset(mp->phy); 152 if (ret) 153 return ret; 154 155 reset_control_assert(mrst->port); 156 reset_control_assert(mrst->apb); 157 udelay(PCIE_RESET_DELAY); 158 reset_control_deassert(mrst->port); 159 reset_control_deassert(mrst->apb); 160 udelay(PCIE_RESET_DELAY); 161 162 return 0; 163 } 164 165 static inline struct clk *meson_pcie_probe_clock(struct device *dev, 166 const char *id, u64 rate) 167 { 168 struct clk *clk; 169 int ret; 170 171 clk = devm_clk_get(dev, id); 172 if (IS_ERR(clk)) 173 return clk; 174 175 if (rate) { 176 ret = clk_set_rate(clk, rate); 177 if (ret) { 178 dev_err(dev, "set clk rate failed, ret = %d\n", ret); 179 return ERR_PTR(ret); 180 } 181 } 182 183 ret = clk_prepare_enable(clk); 184 if (ret) { 185 dev_err(dev, "couldn't enable clk\n"); 186 return ERR_PTR(ret); 187 } 188 189 devm_add_action_or_reset(dev, 190 (void (*) (void *))clk_disable_unprepare, 191 clk); 192 193 return clk; 194 } 195 196 static int meson_pcie_probe_clocks(struct meson_pcie *mp) 197 { 198 struct device *dev = mp->pci.dev; 199 struct meson_pcie_clk_res *res = &mp->clk_res; 200 201 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE); 202 if (IS_ERR(res->port_clk)) 203 return PTR_ERR(res->port_clk); 204 205 res->general_clk = meson_pcie_probe_clock(dev, "general", 0); 206 if (IS_ERR(res->general_clk)) 207 return PTR_ERR(res->general_clk); 208 209 res->clk = meson_pcie_probe_clock(dev, "pclk", 0); 210 if (IS_ERR(res->clk)) 211 return PTR_ERR(res->clk); 212 213 return 0; 214 } 215 216 static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg) 217 { 218 return readl(mp->cfg_base + reg); 219 } 220 221 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg) 222 { 223 writel(val, mp->cfg_base + reg); 224 } 225 226 static void meson_pcie_assert_reset(struct meson_pcie *mp) 227 { 228 gpiod_set_value_cansleep(mp->reset_gpio, 1); 229 udelay(500); 230 gpiod_set_value_cansleep(mp->reset_gpio, 0); 231 } 232 233 static void meson_pcie_init_dw(struct meson_pcie *mp) 234 { 235 u32 val; 236 237 val = meson_cfg_readl(mp, PCIE_CFG0); 238 val |= APP_LTSSM_ENABLE; 239 meson_cfg_writel(mp, val, PCIE_CFG0); 240 } 241 242 static int meson_size_to_payload(struct meson_pcie *mp, int size) 243 { 244 struct device *dev = mp->pci.dev; 245 246 /* 247 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1. 248 * So if input size is not 2^order alignment or less than 2^7 or bigger 249 * than 2^12, just set to default size 2^(1+7). 250 */ 251 if (!is_power_of_2(size) || size < 128 || size > 4096) { 252 dev_warn(dev, "payload size %d, set to default 256\n", size); 253 return 1; 254 } 255 256 return fls(size) - 8; 257 } 258 259 static void meson_set_max_payload(struct meson_pcie *mp, int size) 260 { 261 struct dw_pcie *pci = &mp->pci; 262 u32 val; 263 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 264 int max_payload_size = meson_size_to_payload(mp, size); 265 266 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); 267 val &= ~PCI_EXP_DEVCTL_PAYLOAD; 268 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); 269 270 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); 271 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); 272 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); 273 } 274 275 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) 276 { 277 struct dw_pcie *pci = &mp->pci; 278 u32 val; 279 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 280 int max_rd_req_size = meson_size_to_payload(mp, size); 281 282 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); 283 val &= ~PCI_EXP_DEVCTL_READRQ; 284 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); 285 286 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); 287 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); 288 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); 289 } 290 291 static int meson_pcie_establish_link(struct meson_pcie *mp) 292 { 293 struct dw_pcie *pci = &mp->pci; 294 struct pcie_port *pp = &pci->pp; 295 296 meson_pcie_init_dw(mp); 297 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); 298 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); 299 300 dw_pcie_setup_rc(pp); 301 302 meson_pcie_assert_reset(mp); 303 304 return dw_pcie_wait_for_link(pci); 305 } 306 307 static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, 308 int where, int size, u32 *val) 309 { 310 int ret; 311 312 ret = pci_generic_config_read(bus, devfn, where, size, val); 313 if (ret != PCIBIOS_SUCCESSFUL) 314 return ret; 315 316 /* 317 * There is a bug in the MESON AXG PCIe controller whereby software 318 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate 319 * the return value in the config accessors. 320 */ 321 if (where == PCI_CLASS_REVISION && size == 4) 322 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff); 323 else if (where == PCI_CLASS_DEVICE && size == 2) 324 *val = PCI_CLASS_BRIDGE_PCI; 325 else if (where == PCI_CLASS_DEVICE && size == 1) 326 *val = PCI_CLASS_BRIDGE_PCI & 0xff; 327 else if (where == PCI_CLASS_DEVICE + 1 && size == 1) 328 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff; 329 330 return PCIBIOS_SUCCESSFUL; 331 } 332 333 static struct pci_ops meson_pci_ops = { 334 .map_bus = dw_pcie_own_conf_map_bus, 335 .read = meson_pcie_rd_own_conf, 336 .write = pci_generic_config_write, 337 }; 338 339 static int meson_pcie_link_up(struct dw_pcie *pci) 340 { 341 struct meson_pcie *mp = to_meson_pcie(pci); 342 struct device *dev = pci->dev; 343 u32 speed_okay = 0; 344 u32 cnt = 0; 345 u32 state12, state17, smlh_up, ltssm_up, rdlh_up; 346 347 do { 348 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12); 349 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17); 350 smlh_up = IS_SMLH_LINK_UP(state12); 351 rdlh_up = IS_RDLH_LINK_UP(state12); 352 ltssm_up = IS_LTSSM_UP(state12); 353 354 if (PM_CURRENT_STATE(state17) < PCIE_GEN3) 355 speed_okay = 1; 356 357 if (smlh_up) 358 dev_dbg(dev, "smlh_link_up is on\n"); 359 if (rdlh_up) 360 dev_dbg(dev, "rdlh_link_up is on\n"); 361 if (ltssm_up) 362 dev_dbg(dev, "ltssm_up is on\n"); 363 if (speed_okay) 364 dev_dbg(dev, "speed_okay\n"); 365 366 if (smlh_up && rdlh_up && ltssm_up && speed_okay) 367 return 1; 368 369 cnt++; 370 371 udelay(10); 372 } while (cnt < WAIT_LINKUP_TIMEOUT); 373 374 dev_err(dev, "error: wait linkup timeout\n"); 375 return 0; 376 } 377 378 static int meson_pcie_host_init(struct pcie_port *pp) 379 { 380 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 381 struct meson_pcie *mp = to_meson_pcie(pci); 382 int ret; 383 384 pp->bridge->ops = &meson_pci_ops; 385 386 ret = meson_pcie_establish_link(mp); 387 if (ret) 388 return ret; 389 390 dw_pcie_msi_init(pp); 391 392 return 0; 393 } 394 395 static const struct dw_pcie_host_ops meson_pcie_host_ops = { 396 .host_init = meson_pcie_host_init, 397 }; 398 399 static int meson_add_pcie_port(struct meson_pcie *mp, 400 struct platform_device *pdev) 401 { 402 struct dw_pcie *pci = &mp->pci; 403 struct pcie_port *pp = &pci->pp; 404 struct device *dev = &pdev->dev; 405 int ret; 406 407 if (IS_ENABLED(CONFIG_PCI_MSI)) { 408 pp->msi_irq = platform_get_irq(pdev, 0); 409 if (pp->msi_irq < 0) 410 return pp->msi_irq; 411 } 412 413 pp->ops = &meson_pcie_host_ops; 414 415 ret = dw_pcie_host_init(pp); 416 if (ret) { 417 dev_err(dev, "failed to initialize host\n"); 418 return ret; 419 } 420 421 return 0; 422 } 423 424 static const struct dw_pcie_ops dw_pcie_ops = { 425 .link_up = meson_pcie_link_up, 426 }; 427 428 static int meson_pcie_probe(struct platform_device *pdev) 429 { 430 struct device *dev = &pdev->dev; 431 struct dw_pcie *pci; 432 struct meson_pcie *mp; 433 int ret; 434 435 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); 436 if (!mp) 437 return -ENOMEM; 438 439 pci = &mp->pci; 440 pci->dev = dev; 441 pci->ops = &dw_pcie_ops; 442 pci->num_lanes = 1; 443 444 mp->phy = devm_phy_get(dev, "pcie"); 445 if (IS_ERR(mp->phy)) { 446 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy)); 447 return PTR_ERR(mp->phy); 448 } 449 450 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 451 if (IS_ERR(mp->reset_gpio)) { 452 dev_err(dev, "get reset gpio failed\n"); 453 return PTR_ERR(mp->reset_gpio); 454 } 455 456 ret = meson_pcie_get_resets(mp); 457 if (ret) { 458 dev_err(dev, "get reset resource failed, %d\n", ret); 459 return ret; 460 } 461 462 ret = meson_pcie_get_mems(pdev, mp); 463 if (ret) { 464 dev_err(dev, "get memory resource failed, %d\n", ret); 465 return ret; 466 } 467 468 ret = meson_pcie_power_on(mp); 469 if (ret) { 470 dev_err(dev, "phy power on failed, %d\n", ret); 471 return ret; 472 } 473 474 ret = meson_pcie_reset(mp); 475 if (ret) { 476 dev_err(dev, "reset failed, %d\n", ret); 477 goto err_phy; 478 } 479 480 ret = meson_pcie_probe_clocks(mp); 481 if (ret) { 482 dev_err(dev, "init clock resources failed, %d\n", ret); 483 goto err_phy; 484 } 485 486 platform_set_drvdata(pdev, mp); 487 488 ret = meson_add_pcie_port(mp, pdev); 489 if (ret < 0) { 490 dev_err(dev, "Add PCIe port failed, %d\n", ret); 491 goto err_phy; 492 } 493 494 return 0; 495 496 err_phy: 497 meson_pcie_power_off(mp); 498 return ret; 499 } 500 501 static const struct of_device_id meson_pcie_of_match[] = { 502 { 503 .compatible = "amlogic,axg-pcie", 504 }, 505 { 506 .compatible = "amlogic,g12a-pcie", 507 }, 508 {}, 509 }; 510 511 static struct platform_driver meson_pcie_driver = { 512 .probe = meson_pcie_probe, 513 .driver = { 514 .name = "meson-pcie", 515 .of_match_table = meson_pcie_of_match, 516 }, 517 }; 518 519 builtin_platform_driver(meson_pcie_driver); 520