1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Amlogic MESON SoCs 4 * 5 * Copyright (c) 2018 Amlogic, inc. 6 * Author: Yue Wang <yue.wang@amlogic.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/of_device.h> 13 #include <linux/of_gpio.h> 14 #include <linux/pci.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <linux/resource.h> 18 #include <linux/types.h> 19 #include <linux/phy/phy.h> 20 21 #include "pcie-designware.h" 22 23 #define to_meson_pcie(x) dev_get_drvdata((x)->dev) 24 25 #define TYPE1_HDR_OFFSET 0x0 26 #define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) 27 #define PCI_IO_EN BIT(0) 28 #define PCI_MEM_SPACE_EN BIT(1) 29 #define PCI_BUS_MASTER_EN BIT(2) 30 31 #define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) 32 #define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) 33 34 #define PCIE_CAP_OFFSET 0x70 35 #define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) 36 #define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) 37 #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) 38 #define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) 39 #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) 40 41 /* PCIe specific config registers */ 42 #define PCIE_CFG0 0x0 43 #define APP_LTSSM_ENABLE BIT(7) 44 45 #define PCIE_CFG_STATUS12 0x30 46 #define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) 47 #define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) 48 #define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11) 49 50 #define PCIE_CFG_STATUS17 0x44 51 #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1) 52 53 #define WAIT_LINKUP_TIMEOUT 4000 54 #define PORT_CLK_RATE 100000000UL 55 #define MAX_PAYLOAD_SIZE 256 56 #define MAX_READ_REQ_SIZE 256 57 #define PCIE_RESET_DELAY 500 58 #define PCIE_SHARED_RESET 1 59 #define PCIE_NORMAL_RESET 0 60 61 enum pcie_data_rate { 62 PCIE_GEN1, 63 PCIE_GEN2, 64 PCIE_GEN3, 65 PCIE_GEN4 66 }; 67 68 struct meson_pcie_mem_res { 69 void __iomem *elbi_base; 70 void __iomem *cfg_base; 71 }; 72 73 struct meson_pcie_clk_res { 74 struct clk *clk; 75 struct clk *port_clk; 76 struct clk *general_clk; 77 }; 78 79 struct meson_pcie_rc_reset { 80 struct reset_control *port; 81 struct reset_control *apb; 82 }; 83 84 struct meson_pcie { 85 struct dw_pcie pci; 86 struct meson_pcie_mem_res mem_res; 87 struct meson_pcie_clk_res clk_res; 88 struct meson_pcie_rc_reset mrst; 89 struct gpio_desc *reset_gpio; 90 struct phy *phy; 91 }; 92 93 static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp, 94 const char *id, 95 u32 reset_type) 96 { 97 struct device *dev = mp->pci.dev; 98 struct reset_control *reset; 99 100 if (reset_type == PCIE_SHARED_RESET) 101 reset = devm_reset_control_get_shared(dev, id); 102 else 103 reset = devm_reset_control_get(dev, id); 104 105 return reset; 106 } 107 108 static int meson_pcie_get_resets(struct meson_pcie *mp) 109 { 110 struct meson_pcie_rc_reset *mrst = &mp->mrst; 111 112 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET); 113 if (IS_ERR(mrst->port)) 114 return PTR_ERR(mrst->port); 115 reset_control_deassert(mrst->port); 116 117 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET); 118 if (IS_ERR(mrst->apb)) 119 return PTR_ERR(mrst->apb); 120 reset_control_deassert(mrst->apb); 121 122 return 0; 123 } 124 125 static void __iomem *meson_pcie_get_mem(struct platform_device *pdev, 126 struct meson_pcie *mp, 127 const char *id) 128 { 129 struct device *dev = mp->pci.dev; 130 struct resource *res; 131 132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id); 133 134 return devm_ioremap_resource(dev, res); 135 } 136 137 static int meson_pcie_get_mems(struct platform_device *pdev, 138 struct meson_pcie *mp) 139 { 140 mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi"); 141 if (IS_ERR(mp->mem_res.elbi_base)) 142 return PTR_ERR(mp->mem_res.elbi_base); 143 144 mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg"); 145 if (IS_ERR(mp->mem_res.cfg_base)) 146 return PTR_ERR(mp->mem_res.cfg_base); 147 148 return 0; 149 } 150 151 static int meson_pcie_power_on(struct meson_pcie *mp) 152 { 153 int ret = 0; 154 155 ret = phy_init(mp->phy); 156 if (ret) 157 return ret; 158 159 ret = phy_power_on(mp->phy); 160 if (ret) { 161 phy_exit(mp->phy); 162 return ret; 163 } 164 165 return 0; 166 } 167 168 static void meson_pcie_power_off(struct meson_pcie *mp) 169 { 170 phy_power_off(mp->phy); 171 phy_exit(mp->phy); 172 } 173 174 static int meson_pcie_reset(struct meson_pcie *mp) 175 { 176 struct meson_pcie_rc_reset *mrst = &mp->mrst; 177 int ret = 0; 178 179 ret = phy_reset(mp->phy); 180 if (ret) 181 return ret; 182 183 reset_control_assert(mrst->port); 184 reset_control_assert(mrst->apb); 185 udelay(PCIE_RESET_DELAY); 186 reset_control_deassert(mrst->port); 187 reset_control_deassert(mrst->apb); 188 udelay(PCIE_RESET_DELAY); 189 190 return 0; 191 } 192 193 static inline struct clk *meson_pcie_probe_clock(struct device *dev, 194 const char *id, u64 rate) 195 { 196 struct clk *clk; 197 int ret; 198 199 clk = devm_clk_get(dev, id); 200 if (IS_ERR(clk)) 201 return clk; 202 203 if (rate) { 204 ret = clk_set_rate(clk, rate); 205 if (ret) { 206 dev_err(dev, "set clk rate failed, ret = %d\n", ret); 207 return ERR_PTR(ret); 208 } 209 } 210 211 ret = clk_prepare_enable(clk); 212 if (ret) { 213 dev_err(dev, "couldn't enable clk\n"); 214 return ERR_PTR(ret); 215 } 216 217 devm_add_action_or_reset(dev, 218 (void (*) (void *))clk_disable_unprepare, 219 clk); 220 221 return clk; 222 } 223 224 static int meson_pcie_probe_clocks(struct meson_pcie *mp) 225 { 226 struct device *dev = mp->pci.dev; 227 struct meson_pcie_clk_res *res = &mp->clk_res; 228 229 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE); 230 if (IS_ERR(res->port_clk)) 231 return PTR_ERR(res->port_clk); 232 233 res->general_clk = meson_pcie_probe_clock(dev, "general", 0); 234 if (IS_ERR(res->general_clk)) 235 return PTR_ERR(res->general_clk); 236 237 res->clk = meson_pcie_probe_clock(dev, "pclk", 0); 238 if (IS_ERR(res->clk)) 239 return PTR_ERR(res->clk); 240 241 return 0; 242 } 243 244 static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg) 245 { 246 writel(val, mp->mem_res.elbi_base + reg); 247 } 248 249 static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg) 250 { 251 return readl(mp->mem_res.elbi_base + reg); 252 } 253 254 static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg) 255 { 256 return readl(mp->mem_res.cfg_base + reg); 257 } 258 259 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg) 260 { 261 writel(val, mp->mem_res.cfg_base + reg); 262 } 263 264 static void meson_pcie_assert_reset(struct meson_pcie *mp) 265 { 266 gpiod_set_value_cansleep(mp->reset_gpio, 1); 267 udelay(500); 268 gpiod_set_value_cansleep(mp->reset_gpio, 0); 269 } 270 271 static void meson_pcie_init_dw(struct meson_pcie *mp) 272 { 273 u32 val; 274 275 val = meson_cfg_readl(mp, PCIE_CFG0); 276 val |= APP_LTSSM_ENABLE; 277 meson_cfg_writel(mp, val, PCIE_CFG0); 278 279 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0); 280 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1); 281 } 282 283 static int meson_size_to_payload(struct meson_pcie *mp, int size) 284 { 285 struct device *dev = mp->pci.dev; 286 287 /* 288 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1. 289 * So if input size is not 2^order alignment or less than 2^7 or bigger 290 * than 2^12, just set to default size 2^(1+7). 291 */ 292 if (!is_power_of_2(size) || size < 128 || size > 4096) { 293 dev_warn(dev, "payload size %d, set to default 256\n", size); 294 return 1; 295 } 296 297 return fls(size) - 8; 298 } 299 300 static void meson_set_max_payload(struct meson_pcie *mp, int size) 301 { 302 u32 val; 303 int max_payload_size = meson_size_to_payload(mp, size); 304 305 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 306 val &= ~PCIE_CAP_MAX_PAYLOAD_MASK; 307 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 308 309 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 310 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); 311 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 312 } 313 314 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) 315 { 316 u32 val; 317 int max_rd_req_size = meson_size_to_payload(mp, size); 318 319 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 320 val &= ~PCIE_CAP_MAX_READ_REQ_MASK; 321 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 322 323 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 324 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); 325 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 326 } 327 328 static inline void meson_enable_memory_space(struct meson_pcie *mp) 329 { 330 /* Set the RC Bus Master, Memory Space and I/O Space enables */ 331 meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN, 332 PCIE_STATUS_COMMAND); 333 } 334 335 static int meson_pcie_establish_link(struct meson_pcie *mp) 336 { 337 struct dw_pcie *pci = &mp->pci; 338 struct pcie_port *pp = &pci->pp; 339 340 meson_pcie_init_dw(mp); 341 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); 342 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); 343 344 dw_pcie_setup_rc(pp); 345 meson_enable_memory_space(mp); 346 347 meson_pcie_assert_reset(mp); 348 349 return dw_pcie_wait_for_link(pci); 350 } 351 352 static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, 353 int where, int size, u32 *val) 354 { 355 int ret; 356 357 ret = pci_generic_config_read(bus, devfn, where, size, val); 358 if (ret != PCIBIOS_SUCCESSFUL) 359 return ret; 360 361 /* 362 * There is a bug in the MESON AXG PCIe controller whereby software 363 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate 364 * the return value in the config accessors. 365 */ 366 if (where == PCI_CLASS_REVISION && size == 4) 367 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff); 368 else if (where == PCI_CLASS_DEVICE && size == 2) 369 *val = PCI_CLASS_BRIDGE_PCI; 370 else if (where == PCI_CLASS_DEVICE && size == 1) 371 *val = PCI_CLASS_BRIDGE_PCI & 0xff; 372 else if (where == PCI_CLASS_DEVICE + 1 && size == 1) 373 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff; 374 375 return PCIBIOS_SUCCESSFUL; 376 } 377 378 static struct pci_ops meson_pci_ops = { 379 .map_bus = dw_pcie_own_conf_map_bus, 380 .read = meson_pcie_rd_own_conf, 381 .write = pci_generic_config_write, 382 }; 383 384 static int meson_pcie_link_up(struct dw_pcie *pci) 385 { 386 struct meson_pcie *mp = to_meson_pcie(pci); 387 struct device *dev = pci->dev; 388 u32 speed_okay = 0; 389 u32 cnt = 0; 390 u32 state12, state17, smlh_up, ltssm_up, rdlh_up; 391 392 do { 393 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12); 394 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17); 395 smlh_up = IS_SMLH_LINK_UP(state12); 396 rdlh_up = IS_RDLH_LINK_UP(state12); 397 ltssm_up = IS_LTSSM_UP(state12); 398 399 if (PM_CURRENT_STATE(state17) < PCIE_GEN3) 400 speed_okay = 1; 401 402 if (smlh_up) 403 dev_dbg(dev, "smlh_link_up is on\n"); 404 if (rdlh_up) 405 dev_dbg(dev, "rdlh_link_up is on\n"); 406 if (ltssm_up) 407 dev_dbg(dev, "ltssm_up is on\n"); 408 if (speed_okay) 409 dev_dbg(dev, "speed_okay\n"); 410 411 if (smlh_up && rdlh_up && ltssm_up && speed_okay) 412 return 1; 413 414 cnt++; 415 416 udelay(10); 417 } while (cnt < WAIT_LINKUP_TIMEOUT); 418 419 dev_err(dev, "error: wait linkup timeout\n"); 420 return 0; 421 } 422 423 static int meson_pcie_host_init(struct pcie_port *pp) 424 { 425 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 426 struct meson_pcie *mp = to_meson_pcie(pci); 427 int ret; 428 429 pp->bridge->ops = &meson_pci_ops; 430 431 ret = meson_pcie_establish_link(mp); 432 if (ret) 433 return ret; 434 435 dw_pcie_msi_init(pp); 436 437 return 0; 438 } 439 440 static const struct dw_pcie_host_ops meson_pcie_host_ops = { 441 .host_init = meson_pcie_host_init, 442 }; 443 444 static int meson_add_pcie_port(struct meson_pcie *mp, 445 struct platform_device *pdev) 446 { 447 struct dw_pcie *pci = &mp->pci; 448 struct pcie_port *pp = &pci->pp; 449 struct device *dev = &pdev->dev; 450 int ret; 451 452 if (IS_ENABLED(CONFIG_PCI_MSI)) { 453 pp->msi_irq = platform_get_irq(pdev, 0); 454 if (pp->msi_irq < 0) 455 return pp->msi_irq; 456 } 457 458 pp->ops = &meson_pcie_host_ops; 459 pci->dbi_base = mp->mem_res.elbi_base; 460 461 ret = dw_pcie_host_init(pp); 462 if (ret) { 463 dev_err(dev, "failed to initialize host\n"); 464 return ret; 465 } 466 467 return 0; 468 } 469 470 static const struct dw_pcie_ops dw_pcie_ops = { 471 .link_up = meson_pcie_link_up, 472 }; 473 474 static int meson_pcie_probe(struct platform_device *pdev) 475 { 476 struct device *dev = &pdev->dev; 477 struct dw_pcie *pci; 478 struct meson_pcie *mp; 479 int ret; 480 481 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); 482 if (!mp) 483 return -ENOMEM; 484 485 pci = &mp->pci; 486 pci->dev = dev; 487 pci->ops = &dw_pcie_ops; 488 pci->num_lanes = 1; 489 490 mp->phy = devm_phy_get(dev, "pcie"); 491 if (IS_ERR(mp->phy)) { 492 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy)); 493 return PTR_ERR(mp->phy); 494 } 495 496 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 497 if (IS_ERR(mp->reset_gpio)) { 498 dev_err(dev, "get reset gpio failed\n"); 499 return PTR_ERR(mp->reset_gpio); 500 } 501 502 ret = meson_pcie_get_resets(mp); 503 if (ret) { 504 dev_err(dev, "get reset resource failed, %d\n", ret); 505 return ret; 506 } 507 508 ret = meson_pcie_get_mems(pdev, mp); 509 if (ret) { 510 dev_err(dev, "get memory resource failed, %d\n", ret); 511 return ret; 512 } 513 514 ret = meson_pcie_power_on(mp); 515 if (ret) { 516 dev_err(dev, "phy power on failed, %d\n", ret); 517 return ret; 518 } 519 520 ret = meson_pcie_reset(mp); 521 if (ret) { 522 dev_err(dev, "reset failed, %d\n", ret); 523 goto err_phy; 524 } 525 526 ret = meson_pcie_probe_clocks(mp); 527 if (ret) { 528 dev_err(dev, "init clock resources failed, %d\n", ret); 529 goto err_phy; 530 } 531 532 platform_set_drvdata(pdev, mp); 533 534 ret = meson_add_pcie_port(mp, pdev); 535 if (ret < 0) { 536 dev_err(dev, "Add PCIe port failed, %d\n", ret); 537 goto err_phy; 538 } 539 540 return 0; 541 542 err_phy: 543 meson_pcie_power_off(mp); 544 return ret; 545 } 546 547 static const struct of_device_id meson_pcie_of_match[] = { 548 { 549 .compatible = "amlogic,axg-pcie", 550 }, 551 { 552 .compatible = "amlogic,g12a-pcie", 553 }, 554 {}, 555 }; 556 557 static struct platform_driver meson_pcie_driver = { 558 .probe = meson_pcie_probe, 559 .driver = { 560 .name = "meson-pcie", 561 .of_match_table = meson_pcie_of_match, 562 }, 563 }; 564 565 builtin_platform_driver(meson_pcie_driver); 566