19c0ef6d3SYue Wang // SPDX-License-Identifier: GPL-2.0 29c0ef6d3SYue Wang /* 39c0ef6d3SYue Wang * PCIe host controller driver for Amlogic MESON SoCs 49c0ef6d3SYue Wang * 59c0ef6d3SYue Wang * Copyright (c) 2018 Amlogic, inc. 69c0ef6d3SYue Wang * Author: Yue Wang <yue.wang@amlogic.com> 79c0ef6d3SYue Wang */ 89c0ef6d3SYue Wang 99c0ef6d3SYue Wang #include <linux/clk.h> 109c0ef6d3SYue Wang #include <linux/delay.h> 11a3869d43SCorentin Labbe #include <linux/gpio/consumer.h> 129c0ef6d3SYue Wang #include <linux/of_device.h> 139c0ef6d3SYue Wang #include <linux/of_gpio.h> 149c0ef6d3SYue Wang #include <linux/pci.h> 159c0ef6d3SYue Wang #include <linux/platform_device.h> 169c0ef6d3SYue Wang #include <linux/reset.h> 179c0ef6d3SYue Wang #include <linux/resource.h> 189c0ef6d3SYue Wang #include <linux/types.h> 194ff9f68fSNeil Armstrong #include <linux/phy/phy.h> 209c0ef6d3SYue Wang 219c0ef6d3SYue Wang #include "pcie-designware.h" 229c0ef6d3SYue Wang 239c0ef6d3SYue Wang #define to_meson_pcie(x) dev_get_drvdata((x)->dev) 249c0ef6d3SYue Wang 259c0ef6d3SYue Wang /* External local bus interface registers */ 269c0ef6d3SYue Wang #define PLR_OFFSET 0x700 279c0ef6d3SYue Wang #define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) 289c0ef6d3SYue Wang #define FAST_LINK_MODE BIT(7) 299c0ef6d3SYue Wang #define LINK_CAPABLE_MASK GENMASK(21, 16) 309c0ef6d3SYue Wang #define LINK_CAPABLE_X1 BIT(16) 319c0ef6d3SYue Wang 329c0ef6d3SYue Wang #define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) 339c0ef6d3SYue Wang #define NUM_OF_LANES_MASK GENMASK(12, 8) 349c0ef6d3SYue Wang #define NUM_OF_LANES_X1 BIT(8) 359c0ef6d3SYue Wang #define DIRECT_SPEED_CHANGE BIT(17) 369c0ef6d3SYue Wang 379c0ef6d3SYue Wang #define TYPE1_HDR_OFFSET 0x0 389c0ef6d3SYue Wang #define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) 399c0ef6d3SYue Wang #define PCI_IO_EN BIT(0) 409c0ef6d3SYue Wang #define PCI_MEM_SPACE_EN BIT(1) 419c0ef6d3SYue Wang #define PCI_BUS_MASTER_EN BIT(2) 429c0ef6d3SYue Wang 439c0ef6d3SYue Wang #define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) 449c0ef6d3SYue Wang #define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) 459c0ef6d3SYue Wang 469c0ef6d3SYue Wang #define PCIE_CAP_OFFSET 0x70 479c0ef6d3SYue Wang #define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) 489c0ef6d3SYue Wang #define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) 499c0ef6d3SYue Wang #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) 509c0ef6d3SYue Wang #define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) 519c0ef6d3SYue Wang #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) 529c0ef6d3SYue Wang 539c0ef6d3SYue Wang /* PCIe specific config registers */ 549c0ef6d3SYue Wang #define PCIE_CFG0 0x0 559c0ef6d3SYue Wang #define APP_LTSSM_ENABLE BIT(7) 569c0ef6d3SYue Wang 579c0ef6d3SYue Wang #define PCIE_CFG_STATUS12 0x30 589c0ef6d3SYue Wang #define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) 599c0ef6d3SYue Wang #define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) 609c0ef6d3SYue Wang #define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11) 619c0ef6d3SYue Wang 629c0ef6d3SYue Wang #define PCIE_CFG_STATUS17 0x44 639c0ef6d3SYue Wang #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1) 649c0ef6d3SYue Wang 659c0ef6d3SYue Wang #define WAIT_LINKUP_TIMEOUT 4000 669c0ef6d3SYue Wang #define PORT_CLK_RATE 100000000UL 679c0ef6d3SYue Wang #define MAX_PAYLOAD_SIZE 256 689c0ef6d3SYue Wang #define MAX_READ_REQ_SIZE 256 699c0ef6d3SYue Wang #define PCIE_RESET_DELAY 500 709c0ef6d3SYue Wang #define PCIE_SHARED_RESET 1 719c0ef6d3SYue Wang #define PCIE_NORMAL_RESET 0 729c0ef6d3SYue Wang 739c0ef6d3SYue Wang enum pcie_data_rate { 749c0ef6d3SYue Wang PCIE_GEN1, 759c0ef6d3SYue Wang PCIE_GEN2, 769c0ef6d3SYue Wang PCIE_GEN3, 779c0ef6d3SYue Wang PCIE_GEN4 789c0ef6d3SYue Wang }; 799c0ef6d3SYue Wang 809c0ef6d3SYue Wang struct meson_pcie_mem_res { 819c0ef6d3SYue Wang void __iomem *elbi_base; 829c0ef6d3SYue Wang void __iomem *cfg_base; 839c0ef6d3SYue Wang }; 849c0ef6d3SYue Wang 859c0ef6d3SYue Wang struct meson_pcie_clk_res { 869c0ef6d3SYue Wang struct clk *clk; 879c0ef6d3SYue Wang struct clk *port_clk; 889c0ef6d3SYue Wang struct clk *general_clk; 899c0ef6d3SYue Wang }; 909c0ef6d3SYue Wang 919c0ef6d3SYue Wang struct meson_pcie_rc_reset { 929c0ef6d3SYue Wang struct reset_control *port; 939c0ef6d3SYue Wang struct reset_control *apb; 949c0ef6d3SYue Wang }; 959c0ef6d3SYue Wang 969c0ef6d3SYue Wang struct meson_pcie { 979c0ef6d3SYue Wang struct dw_pcie pci; 989c0ef6d3SYue Wang struct meson_pcie_mem_res mem_res; 999c0ef6d3SYue Wang struct meson_pcie_clk_res clk_res; 1009c0ef6d3SYue Wang struct meson_pcie_rc_reset mrst; 1019c0ef6d3SYue Wang struct gpio_desc *reset_gpio; 1024ff9f68fSNeil Armstrong struct phy *phy; 1039c0ef6d3SYue Wang }; 1049c0ef6d3SYue Wang 1059c0ef6d3SYue Wang static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp, 1069c0ef6d3SYue Wang const char *id, 1079c0ef6d3SYue Wang u32 reset_type) 1089c0ef6d3SYue Wang { 1099c0ef6d3SYue Wang struct device *dev = mp->pci.dev; 1109c0ef6d3SYue Wang struct reset_control *reset; 1119c0ef6d3SYue Wang 1129c0ef6d3SYue Wang if (reset_type == PCIE_SHARED_RESET) 1139c0ef6d3SYue Wang reset = devm_reset_control_get_shared(dev, id); 1149c0ef6d3SYue Wang else 1159c0ef6d3SYue Wang reset = devm_reset_control_get(dev, id); 1169c0ef6d3SYue Wang 1179c0ef6d3SYue Wang return reset; 1189c0ef6d3SYue Wang } 1199c0ef6d3SYue Wang 1209c0ef6d3SYue Wang static int meson_pcie_get_resets(struct meson_pcie *mp) 1219c0ef6d3SYue Wang { 1229c0ef6d3SYue Wang struct meson_pcie_rc_reset *mrst = &mp->mrst; 1239c0ef6d3SYue Wang 1249c0ef6d3SYue Wang mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET); 1259c0ef6d3SYue Wang if (IS_ERR(mrst->port)) 1269c0ef6d3SYue Wang return PTR_ERR(mrst->port); 1279c0ef6d3SYue Wang reset_control_deassert(mrst->port); 1289c0ef6d3SYue Wang 1299c0ef6d3SYue Wang mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET); 1309c0ef6d3SYue Wang if (IS_ERR(mrst->apb)) 1319c0ef6d3SYue Wang return PTR_ERR(mrst->apb); 1329c0ef6d3SYue Wang reset_control_deassert(mrst->apb); 1339c0ef6d3SYue Wang 1349c0ef6d3SYue Wang return 0; 1359c0ef6d3SYue Wang } 1369c0ef6d3SYue Wang 1379c0ef6d3SYue Wang static void __iomem *meson_pcie_get_mem(struct platform_device *pdev, 1389c0ef6d3SYue Wang struct meson_pcie *mp, 1399c0ef6d3SYue Wang const char *id) 1409c0ef6d3SYue Wang { 1419c0ef6d3SYue Wang struct device *dev = mp->pci.dev; 1429c0ef6d3SYue Wang struct resource *res; 1439c0ef6d3SYue Wang 1449c0ef6d3SYue Wang res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id); 1459c0ef6d3SYue Wang 1469c0ef6d3SYue Wang return devm_ioremap_resource(dev, res); 1479c0ef6d3SYue Wang } 1489c0ef6d3SYue Wang 1499c0ef6d3SYue Wang static int meson_pcie_get_mems(struct platform_device *pdev, 1509c0ef6d3SYue Wang struct meson_pcie *mp) 1519c0ef6d3SYue Wang { 1529c0ef6d3SYue Wang mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi"); 1539c0ef6d3SYue Wang if (IS_ERR(mp->mem_res.elbi_base)) 1549c0ef6d3SYue Wang return PTR_ERR(mp->mem_res.elbi_base); 1559c0ef6d3SYue Wang 1569c0ef6d3SYue Wang mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg"); 1579c0ef6d3SYue Wang if (IS_ERR(mp->mem_res.cfg_base)) 1589c0ef6d3SYue Wang return PTR_ERR(mp->mem_res.cfg_base); 1599c0ef6d3SYue Wang 1609c0ef6d3SYue Wang return 0; 1619c0ef6d3SYue Wang } 1629c0ef6d3SYue Wang 1634ff9f68fSNeil Armstrong static int meson_pcie_power_on(struct meson_pcie *mp) 1649c0ef6d3SYue Wang { 1654ff9f68fSNeil Armstrong int ret = 0; 1664ff9f68fSNeil Armstrong 1674ff9f68fSNeil Armstrong ret = phy_init(mp->phy); 1684ff9f68fSNeil Armstrong if (ret) 1694ff9f68fSNeil Armstrong return ret; 1704ff9f68fSNeil Armstrong 1714ff9f68fSNeil Armstrong ret = phy_power_on(mp->phy); 1724ff9f68fSNeil Armstrong if (ret) { 1734ff9f68fSNeil Armstrong phy_exit(mp->phy); 1744ff9f68fSNeil Armstrong return ret; 1754ff9f68fSNeil Armstrong } 1764ff9f68fSNeil Armstrong 1774ff9f68fSNeil Armstrong return 0; 1789c0ef6d3SYue Wang } 1799c0ef6d3SYue Wang 1801e6bbc46SRemi Pommarel static void meson_pcie_power_off(struct meson_pcie *mp) 1811e6bbc46SRemi Pommarel { 1821e6bbc46SRemi Pommarel phy_power_off(mp->phy); 1831e6bbc46SRemi Pommarel phy_exit(mp->phy); 1841e6bbc46SRemi Pommarel } 1851e6bbc46SRemi Pommarel 1864ff9f68fSNeil Armstrong static int meson_pcie_reset(struct meson_pcie *mp) 1879c0ef6d3SYue Wang { 1889c0ef6d3SYue Wang struct meson_pcie_rc_reset *mrst = &mp->mrst; 1894ff9f68fSNeil Armstrong int ret = 0; 1909c0ef6d3SYue Wang 1914ff9f68fSNeil Armstrong ret = phy_reset(mp->phy); 1924ff9f68fSNeil Armstrong if (ret) 1934ff9f68fSNeil Armstrong return ret; 1949c0ef6d3SYue Wang 1959c0ef6d3SYue Wang reset_control_assert(mrst->port); 1969c0ef6d3SYue Wang reset_control_assert(mrst->apb); 1979c0ef6d3SYue Wang udelay(PCIE_RESET_DELAY); 1989c0ef6d3SYue Wang reset_control_deassert(mrst->port); 1999c0ef6d3SYue Wang reset_control_deassert(mrst->apb); 2009c0ef6d3SYue Wang udelay(PCIE_RESET_DELAY); 2014ff9f68fSNeil Armstrong 2024ff9f68fSNeil Armstrong return 0; 2039c0ef6d3SYue Wang } 2049c0ef6d3SYue Wang 2059c0ef6d3SYue Wang static inline struct clk *meson_pcie_probe_clock(struct device *dev, 2069c0ef6d3SYue Wang const char *id, u64 rate) 2079c0ef6d3SYue Wang { 2089c0ef6d3SYue Wang struct clk *clk; 2099c0ef6d3SYue Wang int ret; 2109c0ef6d3SYue Wang 2119c0ef6d3SYue Wang clk = devm_clk_get(dev, id); 2129c0ef6d3SYue Wang if (IS_ERR(clk)) 2139c0ef6d3SYue Wang return clk; 2149c0ef6d3SYue Wang 2159c0ef6d3SYue Wang if (rate) { 2169c0ef6d3SYue Wang ret = clk_set_rate(clk, rate); 2179c0ef6d3SYue Wang if (ret) { 2189c0ef6d3SYue Wang dev_err(dev, "set clk rate failed, ret = %d\n", ret); 2199c0ef6d3SYue Wang return ERR_PTR(ret); 2209c0ef6d3SYue Wang } 2219c0ef6d3SYue Wang } 2229c0ef6d3SYue Wang 2239c0ef6d3SYue Wang ret = clk_prepare_enable(clk); 2249c0ef6d3SYue Wang if (ret) { 2259c0ef6d3SYue Wang dev_err(dev, "couldn't enable clk\n"); 2269c0ef6d3SYue Wang return ERR_PTR(ret); 2279c0ef6d3SYue Wang } 2289c0ef6d3SYue Wang 2299c0ef6d3SYue Wang devm_add_action_or_reset(dev, 2309c0ef6d3SYue Wang (void (*) (void *))clk_disable_unprepare, 2319c0ef6d3SYue Wang clk); 2329c0ef6d3SYue Wang 2339c0ef6d3SYue Wang return clk; 2349c0ef6d3SYue Wang } 2359c0ef6d3SYue Wang 2369c0ef6d3SYue Wang static int meson_pcie_probe_clocks(struct meson_pcie *mp) 2379c0ef6d3SYue Wang { 2389c0ef6d3SYue Wang struct device *dev = mp->pci.dev; 2399c0ef6d3SYue Wang struct meson_pcie_clk_res *res = &mp->clk_res; 2409c0ef6d3SYue Wang 2419c0ef6d3SYue Wang res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE); 2429c0ef6d3SYue Wang if (IS_ERR(res->port_clk)) 2439c0ef6d3SYue Wang return PTR_ERR(res->port_clk); 2449c0ef6d3SYue Wang 245eacaf7dcSNeil Armstrong res->general_clk = meson_pcie_probe_clock(dev, "general", 0); 2469c0ef6d3SYue Wang if (IS_ERR(res->general_clk)) 2479c0ef6d3SYue Wang return PTR_ERR(res->general_clk); 2489c0ef6d3SYue Wang 249eacaf7dcSNeil Armstrong res->clk = meson_pcie_probe_clock(dev, "pclk", 0); 2509c0ef6d3SYue Wang if (IS_ERR(res->clk)) 2519c0ef6d3SYue Wang return PTR_ERR(res->clk); 2529c0ef6d3SYue Wang 2539c0ef6d3SYue Wang return 0; 2549c0ef6d3SYue Wang } 2559c0ef6d3SYue Wang 2569c0ef6d3SYue Wang static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg) 2579c0ef6d3SYue Wang { 2589c0ef6d3SYue Wang writel(val, mp->mem_res.elbi_base + reg); 2599c0ef6d3SYue Wang } 2609c0ef6d3SYue Wang 2619c0ef6d3SYue Wang static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg) 2629c0ef6d3SYue Wang { 2639c0ef6d3SYue Wang return readl(mp->mem_res.elbi_base + reg); 2649c0ef6d3SYue Wang } 2659c0ef6d3SYue Wang 2669c0ef6d3SYue Wang static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg) 2679c0ef6d3SYue Wang { 2689c0ef6d3SYue Wang return readl(mp->mem_res.cfg_base + reg); 2699c0ef6d3SYue Wang } 2709c0ef6d3SYue Wang 2719c0ef6d3SYue Wang static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg) 2729c0ef6d3SYue Wang { 2739c0ef6d3SYue Wang writel(val, mp->mem_res.cfg_base + reg); 2749c0ef6d3SYue Wang } 2759c0ef6d3SYue Wang 2769c0ef6d3SYue Wang static void meson_pcie_assert_reset(struct meson_pcie *mp) 2779c0ef6d3SYue Wang { 2789c0ef6d3SYue Wang gpiod_set_value_cansleep(mp->reset_gpio, 1); 2794d3186a5SRemi Pommarel udelay(500); 2804d3186a5SRemi Pommarel gpiod_set_value_cansleep(mp->reset_gpio, 0); 2819c0ef6d3SYue Wang } 2829c0ef6d3SYue Wang 2839c0ef6d3SYue Wang static void meson_pcie_init_dw(struct meson_pcie *mp) 2849c0ef6d3SYue Wang { 2859c0ef6d3SYue Wang u32 val; 2869c0ef6d3SYue Wang 2879c0ef6d3SYue Wang val = meson_cfg_readl(mp, PCIE_CFG0); 2889c0ef6d3SYue Wang val |= APP_LTSSM_ENABLE; 2899c0ef6d3SYue Wang meson_cfg_writel(mp, val, PCIE_CFG0); 2909c0ef6d3SYue Wang 2919c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF); 2929c0ef6d3SYue Wang val &= ~LINK_CAPABLE_MASK; 2939c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF); 2949c0ef6d3SYue Wang 2959c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF); 2969c0ef6d3SYue Wang val |= LINK_CAPABLE_X1 | FAST_LINK_MODE; 2979c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF); 2989c0ef6d3SYue Wang 2999c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); 3009c0ef6d3SYue Wang val &= ~NUM_OF_LANES_MASK; 3019c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); 3029c0ef6d3SYue Wang 3039c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); 3049c0ef6d3SYue Wang val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE; 3059c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); 3069c0ef6d3SYue Wang 3079c0ef6d3SYue Wang meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0); 3089c0ef6d3SYue Wang meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1); 3099c0ef6d3SYue Wang } 3109c0ef6d3SYue Wang 3119c0ef6d3SYue Wang static int meson_size_to_payload(struct meson_pcie *mp, int size) 3129c0ef6d3SYue Wang { 3139c0ef6d3SYue Wang struct device *dev = mp->pci.dev; 3149c0ef6d3SYue Wang 3159c0ef6d3SYue Wang /* 3169c0ef6d3SYue Wang * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1. 3179c0ef6d3SYue Wang * So if input size is not 2^order alignment or less than 2^7 or bigger 3189c0ef6d3SYue Wang * than 2^12, just set to default size 2^(1+7). 3199c0ef6d3SYue Wang */ 3209c0ef6d3SYue Wang if (!is_power_of_2(size) || size < 128 || size > 4096) { 3219c0ef6d3SYue Wang dev_warn(dev, "payload size %d, set to default 256\n", size); 3229c0ef6d3SYue Wang return 1; 3239c0ef6d3SYue Wang } 3249c0ef6d3SYue Wang 3259c0ef6d3SYue Wang return fls(size) - 8; 3269c0ef6d3SYue Wang } 3279c0ef6d3SYue Wang 3289c0ef6d3SYue Wang static void meson_set_max_payload(struct meson_pcie *mp, int size) 3299c0ef6d3SYue Wang { 3309c0ef6d3SYue Wang u32 val; 3319c0ef6d3SYue Wang int max_payload_size = meson_size_to_payload(mp, size); 3329c0ef6d3SYue Wang 3339c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 3349c0ef6d3SYue Wang val &= ~PCIE_CAP_MAX_PAYLOAD_MASK; 3359c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 3369c0ef6d3SYue Wang 3379c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 3389c0ef6d3SYue Wang val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); 3399c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 3409c0ef6d3SYue Wang } 3419c0ef6d3SYue Wang 3429c0ef6d3SYue Wang static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) 3439c0ef6d3SYue Wang { 3449c0ef6d3SYue Wang u32 val; 3459c0ef6d3SYue Wang int max_rd_req_size = meson_size_to_payload(mp, size); 3469c0ef6d3SYue Wang 3479c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 3489c0ef6d3SYue Wang val &= ~PCIE_CAP_MAX_READ_REQ_MASK; 3499c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 3509c0ef6d3SYue Wang 3519c0ef6d3SYue Wang val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); 3529c0ef6d3SYue Wang val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); 3539c0ef6d3SYue Wang meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); 3549c0ef6d3SYue Wang } 3559c0ef6d3SYue Wang 3569c0ef6d3SYue Wang static inline void meson_enable_memory_space(struct meson_pcie *mp) 3579c0ef6d3SYue Wang { 3589c0ef6d3SYue Wang /* Set the RC Bus Master, Memory Space and I/O Space enables */ 3599c0ef6d3SYue Wang meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN, 3609c0ef6d3SYue Wang PCIE_STATUS_COMMAND); 3619c0ef6d3SYue Wang } 3629c0ef6d3SYue Wang 3639c0ef6d3SYue Wang static int meson_pcie_establish_link(struct meson_pcie *mp) 3649c0ef6d3SYue Wang { 3659c0ef6d3SYue Wang struct dw_pcie *pci = &mp->pci; 3669c0ef6d3SYue Wang struct pcie_port *pp = &pci->pp; 3679c0ef6d3SYue Wang 3689c0ef6d3SYue Wang meson_pcie_init_dw(mp); 3699c0ef6d3SYue Wang meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); 3709c0ef6d3SYue Wang meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); 3719c0ef6d3SYue Wang 3729c0ef6d3SYue Wang dw_pcie_setup_rc(pp); 3739c0ef6d3SYue Wang meson_enable_memory_space(mp); 3749c0ef6d3SYue Wang 3759c0ef6d3SYue Wang meson_pcie_assert_reset(mp); 3769c0ef6d3SYue Wang 3779c0ef6d3SYue Wang return dw_pcie_wait_for_link(pci); 3789c0ef6d3SYue Wang } 3799c0ef6d3SYue Wang 3809c0ef6d3SYue Wang static void meson_pcie_enable_interrupts(struct meson_pcie *mp) 3819c0ef6d3SYue Wang { 3829c0ef6d3SYue Wang if (IS_ENABLED(CONFIG_PCI_MSI)) 3839c0ef6d3SYue Wang dw_pcie_msi_init(&mp->pci.pp); 3849c0ef6d3SYue Wang } 3859c0ef6d3SYue Wang 3869c0ef6d3SYue Wang static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 3879c0ef6d3SYue Wang u32 *val) 3889c0ef6d3SYue Wang { 3899c0ef6d3SYue Wang struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 3909c0ef6d3SYue Wang int ret; 3919c0ef6d3SYue Wang 3929c0ef6d3SYue Wang ret = dw_pcie_read(pci->dbi_base + where, size, val); 3939c0ef6d3SYue Wang if (ret != PCIBIOS_SUCCESSFUL) 3949c0ef6d3SYue Wang return ret; 3959c0ef6d3SYue Wang 3969c0ef6d3SYue Wang /* 3979c0ef6d3SYue Wang * There is a bug in the MESON AXG PCIe controller whereby software 3989c0ef6d3SYue Wang * cannot program the PCI_CLASS_DEVICE register, so we must fabricate 3999c0ef6d3SYue Wang * the return value in the config accessors. 4009c0ef6d3SYue Wang */ 4019c0ef6d3SYue Wang if (where == PCI_CLASS_REVISION && size == 4) 4029c0ef6d3SYue Wang *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff); 4039c0ef6d3SYue Wang else if (where == PCI_CLASS_DEVICE && size == 2) 4049c0ef6d3SYue Wang *val = PCI_CLASS_BRIDGE_PCI; 4059c0ef6d3SYue Wang else if (where == PCI_CLASS_DEVICE && size == 1) 4069c0ef6d3SYue Wang *val = PCI_CLASS_BRIDGE_PCI & 0xff; 4079c0ef6d3SYue Wang else if (where == PCI_CLASS_DEVICE + 1 && size == 1) 4089c0ef6d3SYue Wang *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff; 4099c0ef6d3SYue Wang 4109c0ef6d3SYue Wang return PCIBIOS_SUCCESSFUL; 4119c0ef6d3SYue Wang } 4129c0ef6d3SYue Wang 4139c0ef6d3SYue Wang static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where, 4149c0ef6d3SYue Wang int size, u32 val) 4159c0ef6d3SYue Wang { 4169c0ef6d3SYue Wang struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 4179c0ef6d3SYue Wang 4189c0ef6d3SYue Wang return dw_pcie_write(pci->dbi_base + where, size, val); 4199c0ef6d3SYue Wang } 4209c0ef6d3SYue Wang 4219c0ef6d3SYue Wang static int meson_pcie_link_up(struct dw_pcie *pci) 4229c0ef6d3SYue Wang { 4239c0ef6d3SYue Wang struct meson_pcie *mp = to_meson_pcie(pci); 4249c0ef6d3SYue Wang struct device *dev = pci->dev; 4259c0ef6d3SYue Wang u32 speed_okay = 0; 4269c0ef6d3SYue Wang u32 cnt = 0; 4279c0ef6d3SYue Wang u32 state12, state17, smlh_up, ltssm_up, rdlh_up; 4289c0ef6d3SYue Wang 4299c0ef6d3SYue Wang do { 4309c0ef6d3SYue Wang state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12); 4319c0ef6d3SYue Wang state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17); 4329c0ef6d3SYue Wang smlh_up = IS_SMLH_LINK_UP(state12); 4339c0ef6d3SYue Wang rdlh_up = IS_RDLH_LINK_UP(state12); 4349c0ef6d3SYue Wang ltssm_up = IS_LTSSM_UP(state12); 4359c0ef6d3SYue Wang 4369c0ef6d3SYue Wang if (PM_CURRENT_STATE(state17) < PCIE_GEN3) 4379c0ef6d3SYue Wang speed_okay = 1; 4389c0ef6d3SYue Wang 4399c0ef6d3SYue Wang if (smlh_up) 4409c0ef6d3SYue Wang dev_dbg(dev, "smlh_link_up is on\n"); 4419c0ef6d3SYue Wang if (rdlh_up) 4429c0ef6d3SYue Wang dev_dbg(dev, "rdlh_link_up is on\n"); 4439c0ef6d3SYue Wang if (ltssm_up) 4449c0ef6d3SYue Wang dev_dbg(dev, "ltssm_up is on\n"); 4459c0ef6d3SYue Wang if (speed_okay) 4469c0ef6d3SYue Wang dev_dbg(dev, "speed_okay\n"); 4479c0ef6d3SYue Wang 4489c0ef6d3SYue Wang if (smlh_up && rdlh_up && ltssm_up && speed_okay) 4499c0ef6d3SYue Wang return 1; 4509c0ef6d3SYue Wang 4519c0ef6d3SYue Wang cnt++; 4529c0ef6d3SYue Wang 4539c0ef6d3SYue Wang udelay(10); 4549c0ef6d3SYue Wang } while (cnt < WAIT_LINKUP_TIMEOUT); 4559c0ef6d3SYue Wang 4569c0ef6d3SYue Wang dev_err(dev, "error: wait linkup timeout\n"); 4579c0ef6d3SYue Wang return 0; 4589c0ef6d3SYue Wang } 4599c0ef6d3SYue Wang 4609c0ef6d3SYue Wang static int meson_pcie_host_init(struct pcie_port *pp) 4619c0ef6d3SYue Wang { 4629c0ef6d3SYue Wang struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 4639c0ef6d3SYue Wang struct meson_pcie *mp = to_meson_pcie(pci); 4649c0ef6d3SYue Wang int ret; 4659c0ef6d3SYue Wang 4669c0ef6d3SYue Wang ret = meson_pcie_establish_link(mp); 4679c0ef6d3SYue Wang if (ret) 4689c0ef6d3SYue Wang return ret; 4699c0ef6d3SYue Wang 4709c0ef6d3SYue Wang meson_pcie_enable_interrupts(mp); 4719c0ef6d3SYue Wang 4729c0ef6d3SYue Wang return 0; 4739c0ef6d3SYue Wang } 4749c0ef6d3SYue Wang 4759c0ef6d3SYue Wang static const struct dw_pcie_host_ops meson_pcie_host_ops = { 4769c0ef6d3SYue Wang .rd_own_conf = meson_pcie_rd_own_conf, 4779c0ef6d3SYue Wang .wr_own_conf = meson_pcie_wr_own_conf, 4789c0ef6d3SYue Wang .host_init = meson_pcie_host_init, 4799c0ef6d3SYue Wang }; 4809c0ef6d3SYue Wang 4819c0ef6d3SYue Wang static int meson_add_pcie_port(struct meson_pcie *mp, 4829c0ef6d3SYue Wang struct platform_device *pdev) 4839c0ef6d3SYue Wang { 4849c0ef6d3SYue Wang struct dw_pcie *pci = &mp->pci; 4859c0ef6d3SYue Wang struct pcie_port *pp = &pci->pp; 4869c0ef6d3SYue Wang struct device *dev = &pdev->dev; 4879c0ef6d3SYue Wang int ret; 4889c0ef6d3SYue Wang 4899c0ef6d3SYue Wang if (IS_ENABLED(CONFIG_PCI_MSI)) { 4909c0ef6d3SYue Wang pp->msi_irq = platform_get_irq(pdev, 0); 4919c0ef6d3SYue Wang if (pp->msi_irq < 0) { 4929c0ef6d3SYue Wang dev_err(dev, "failed to get MSI IRQ\n"); 4939c0ef6d3SYue Wang return pp->msi_irq; 4949c0ef6d3SYue Wang } 4959c0ef6d3SYue Wang } 4969c0ef6d3SYue Wang 4979c0ef6d3SYue Wang pp->ops = &meson_pcie_host_ops; 4989c0ef6d3SYue Wang pci->dbi_base = mp->mem_res.elbi_base; 4999c0ef6d3SYue Wang 5009c0ef6d3SYue Wang ret = dw_pcie_host_init(pp); 5019c0ef6d3SYue Wang if (ret) { 5029c0ef6d3SYue Wang dev_err(dev, "failed to initialize host\n"); 5039c0ef6d3SYue Wang return ret; 5049c0ef6d3SYue Wang } 5059c0ef6d3SYue Wang 5069c0ef6d3SYue Wang return 0; 5079c0ef6d3SYue Wang } 5089c0ef6d3SYue Wang 5099c0ef6d3SYue Wang static const struct dw_pcie_ops dw_pcie_ops = { 5109c0ef6d3SYue Wang .link_up = meson_pcie_link_up, 5119c0ef6d3SYue Wang }; 5129c0ef6d3SYue Wang 5139c0ef6d3SYue Wang static int meson_pcie_probe(struct platform_device *pdev) 5149c0ef6d3SYue Wang { 5159c0ef6d3SYue Wang struct device *dev = &pdev->dev; 5169c0ef6d3SYue Wang struct dw_pcie *pci; 5179c0ef6d3SYue Wang struct meson_pcie *mp; 5189c0ef6d3SYue Wang int ret; 5199c0ef6d3SYue Wang 5209c0ef6d3SYue Wang mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); 5219c0ef6d3SYue Wang if (!mp) 5229c0ef6d3SYue Wang return -ENOMEM; 5239c0ef6d3SYue Wang 5249c0ef6d3SYue Wang pci = &mp->pci; 5259c0ef6d3SYue Wang pci->dev = dev; 5269c0ef6d3SYue Wang pci->ops = &dw_pcie_ops; 5279c0ef6d3SYue Wang 5284ff9f68fSNeil Armstrong mp->phy = devm_phy_get(dev, "pcie"); 5291e6bbc46SRemi Pommarel if (IS_ERR(mp->phy)) { 5301e6bbc46SRemi Pommarel dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy)); 5314ff9f68fSNeil Armstrong return PTR_ERR(mp->phy); 5324ff9f68fSNeil Armstrong } 5334ff9f68fSNeil Armstrong 5349c0ef6d3SYue Wang mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 5359c0ef6d3SYue Wang if (IS_ERR(mp->reset_gpio)) { 5369c0ef6d3SYue Wang dev_err(dev, "get reset gpio failed\n"); 5379c0ef6d3SYue Wang return PTR_ERR(mp->reset_gpio); 5389c0ef6d3SYue Wang } 5399c0ef6d3SYue Wang 5409c0ef6d3SYue Wang ret = meson_pcie_get_resets(mp); 5419c0ef6d3SYue Wang if (ret) { 5429c0ef6d3SYue Wang dev_err(dev, "get reset resource failed, %d\n", ret); 5439c0ef6d3SYue Wang return ret; 5449c0ef6d3SYue Wang } 5459c0ef6d3SYue Wang 5469c0ef6d3SYue Wang ret = meson_pcie_get_mems(pdev, mp); 5479c0ef6d3SYue Wang if (ret) { 5489c0ef6d3SYue Wang dev_err(dev, "get memory resource failed, %d\n", ret); 5499c0ef6d3SYue Wang return ret; 5509c0ef6d3SYue Wang } 5519c0ef6d3SYue Wang 5524ff9f68fSNeil Armstrong ret = meson_pcie_power_on(mp); 5534ff9f68fSNeil Armstrong if (ret) { 5544ff9f68fSNeil Armstrong dev_err(dev, "phy power on failed, %d\n", ret); 5554ff9f68fSNeil Armstrong return ret; 5564ff9f68fSNeil Armstrong } 5574ff9f68fSNeil Armstrong 5584ff9f68fSNeil Armstrong ret = meson_pcie_reset(mp); 5594ff9f68fSNeil Armstrong if (ret) { 5604ff9f68fSNeil Armstrong dev_err(dev, "reset failed, %d\n", ret); 5614ff9f68fSNeil Armstrong goto err_phy; 5624ff9f68fSNeil Armstrong } 5639c0ef6d3SYue Wang 5649c0ef6d3SYue Wang ret = meson_pcie_probe_clocks(mp); 5659c0ef6d3SYue Wang if (ret) { 5669c0ef6d3SYue Wang dev_err(dev, "init clock resources failed, %d\n", ret); 5674ff9f68fSNeil Armstrong goto err_phy; 5689c0ef6d3SYue Wang } 5699c0ef6d3SYue Wang 5709c0ef6d3SYue Wang platform_set_drvdata(pdev, mp); 5719c0ef6d3SYue Wang 5729c0ef6d3SYue Wang ret = meson_add_pcie_port(mp, pdev); 5739c0ef6d3SYue Wang if (ret < 0) { 5749c0ef6d3SYue Wang dev_err(dev, "Add PCIe port failed, %d\n", ret); 5754ff9f68fSNeil Armstrong goto err_phy; 5769c0ef6d3SYue Wang } 5779c0ef6d3SYue Wang 5789c0ef6d3SYue Wang return 0; 5794ff9f68fSNeil Armstrong 5804ff9f68fSNeil Armstrong err_phy: 5811e6bbc46SRemi Pommarel meson_pcie_power_off(mp); 5824ff9f68fSNeil Armstrong return ret; 5834ff9f68fSNeil Armstrong } 5844ff9f68fSNeil Armstrong 5859c0ef6d3SYue Wang static const struct of_device_id meson_pcie_of_match[] = { 5869c0ef6d3SYue Wang { 5879c0ef6d3SYue Wang .compatible = "amlogic,axg-pcie", 5884ff9f68fSNeil Armstrong }, 5894ff9f68fSNeil Armstrong { 5904ff9f68fSNeil Armstrong .compatible = "amlogic,g12a-pcie", 5919c0ef6d3SYue Wang }, 5929c0ef6d3SYue Wang {}, 5939c0ef6d3SYue Wang }; 5949c0ef6d3SYue Wang 5959c0ef6d3SYue Wang static struct platform_driver meson_pcie_driver = { 5969c0ef6d3SYue Wang .probe = meson_pcie_probe, 5979c0ef6d3SYue Wang .driver = { 5989c0ef6d3SYue Wang .name = "meson-pcie", 5999c0ef6d3SYue Wang .of_match_table = meson_pcie_of_match, 6009c0ef6d3SYue Wang }, 6019c0ef6d3SYue Wang }; 6029c0ef6d3SYue Wang 6039c0ef6d3SYue Wang builtin_platform_driver(meson_pcie_driver); 604