19c0ef6d3SYue Wang // SPDX-License-Identifier: GPL-2.0
29c0ef6d3SYue Wang /*
39c0ef6d3SYue Wang * PCIe host controller driver for Amlogic MESON SoCs
49c0ef6d3SYue Wang *
59c0ef6d3SYue Wang * Copyright (c) 2018 Amlogic, inc.
69c0ef6d3SYue Wang * Author: Yue Wang <yue.wang@amlogic.com>
79c0ef6d3SYue Wang */
89c0ef6d3SYue Wang
99c0ef6d3SYue Wang #include <linux/clk.h>
109c0ef6d3SYue Wang #include <linux/delay.h>
11a3869d43SCorentin Labbe #include <linux/gpio/consumer.h>
129c0ef6d3SYue Wang #include <linux/of_gpio.h>
139c0ef6d3SYue Wang #include <linux/pci.h>
149c0ef6d3SYue Wang #include <linux/platform_device.h>
159c0ef6d3SYue Wang #include <linux/reset.h>
169c0ef6d3SYue Wang #include <linux/resource.h>
179c0ef6d3SYue Wang #include <linux/types.h>
184ff9f68fSNeil Armstrong #include <linux/phy/phy.h>
19*c925cfafSRob Herring #include <linux/mod_devicetable.h>
20a98d2187SKevin Hilman #include <linux/module.h>
219c0ef6d3SYue Wang
229c0ef6d3SYue Wang #include "pcie-designware.h"
239c0ef6d3SYue Wang
249c0ef6d3SYue Wang #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
259c0ef6d3SYue Wang
269c0ef6d3SYue Wang #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
279c0ef6d3SYue Wang #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
289c0ef6d3SYue Wang
299c0ef6d3SYue Wang /* PCIe specific config registers */
309c0ef6d3SYue Wang #define PCIE_CFG0 0x0
319c0ef6d3SYue Wang #define APP_LTSSM_ENABLE BIT(7)
329c0ef6d3SYue Wang
339c0ef6d3SYue Wang #define PCIE_CFG_STATUS12 0x30
349c0ef6d3SYue Wang #define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
359c0ef6d3SYue Wang #define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
369c0ef6d3SYue Wang #define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
379c0ef6d3SYue Wang
389c0ef6d3SYue Wang #define PCIE_CFG_STATUS17 0x44
399c0ef6d3SYue Wang #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
409c0ef6d3SYue Wang
419c0ef6d3SYue Wang #define WAIT_LINKUP_TIMEOUT 4000
429c0ef6d3SYue Wang #define PORT_CLK_RATE 100000000UL
439c0ef6d3SYue Wang #define MAX_PAYLOAD_SIZE 256
449c0ef6d3SYue Wang #define MAX_READ_REQ_SIZE 256
459c0ef6d3SYue Wang #define PCIE_RESET_DELAY 500
469c0ef6d3SYue Wang #define PCIE_SHARED_RESET 1
479c0ef6d3SYue Wang #define PCIE_NORMAL_RESET 0
489c0ef6d3SYue Wang
499c0ef6d3SYue Wang enum pcie_data_rate {
509c0ef6d3SYue Wang PCIE_GEN1,
519c0ef6d3SYue Wang PCIE_GEN2,
529c0ef6d3SYue Wang PCIE_GEN3,
539c0ef6d3SYue Wang PCIE_GEN4
549c0ef6d3SYue Wang };
559c0ef6d3SYue Wang
569c0ef6d3SYue Wang struct meson_pcie_clk_res {
579c0ef6d3SYue Wang struct clk *clk;
589c0ef6d3SYue Wang struct clk *port_clk;
599c0ef6d3SYue Wang struct clk *general_clk;
609c0ef6d3SYue Wang };
619c0ef6d3SYue Wang
629c0ef6d3SYue Wang struct meson_pcie_rc_reset {
639c0ef6d3SYue Wang struct reset_control *port;
649c0ef6d3SYue Wang struct reset_control *apb;
659c0ef6d3SYue Wang };
669c0ef6d3SYue Wang
679c0ef6d3SYue Wang struct meson_pcie {
689c0ef6d3SYue Wang struct dw_pcie pci;
692f2cea1eSRob Herring void __iomem *cfg_base;
709c0ef6d3SYue Wang struct meson_pcie_clk_res clk_res;
719c0ef6d3SYue Wang struct meson_pcie_rc_reset mrst;
729c0ef6d3SYue Wang struct gpio_desc *reset_gpio;
734ff9f68fSNeil Armstrong struct phy *phy;
749c0ef6d3SYue Wang };
759c0ef6d3SYue Wang
meson_pcie_get_reset(struct meson_pcie * mp,const char * id,u32 reset_type)769c0ef6d3SYue Wang static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
779c0ef6d3SYue Wang const char *id,
789c0ef6d3SYue Wang u32 reset_type)
799c0ef6d3SYue Wang {
809c0ef6d3SYue Wang struct device *dev = mp->pci.dev;
819c0ef6d3SYue Wang struct reset_control *reset;
829c0ef6d3SYue Wang
839c0ef6d3SYue Wang if (reset_type == PCIE_SHARED_RESET)
849c0ef6d3SYue Wang reset = devm_reset_control_get_shared(dev, id);
859c0ef6d3SYue Wang else
869c0ef6d3SYue Wang reset = devm_reset_control_get(dev, id);
879c0ef6d3SYue Wang
889c0ef6d3SYue Wang return reset;
899c0ef6d3SYue Wang }
909c0ef6d3SYue Wang
meson_pcie_get_resets(struct meson_pcie * mp)919c0ef6d3SYue Wang static int meson_pcie_get_resets(struct meson_pcie *mp)
929c0ef6d3SYue Wang {
939c0ef6d3SYue Wang struct meson_pcie_rc_reset *mrst = &mp->mrst;
949c0ef6d3SYue Wang
959c0ef6d3SYue Wang mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
969c0ef6d3SYue Wang if (IS_ERR(mrst->port))
979c0ef6d3SYue Wang return PTR_ERR(mrst->port);
989c0ef6d3SYue Wang reset_control_deassert(mrst->port);
999c0ef6d3SYue Wang
1009c0ef6d3SYue Wang mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
1019c0ef6d3SYue Wang if (IS_ERR(mrst->apb))
1029c0ef6d3SYue Wang return PTR_ERR(mrst->apb);
1039c0ef6d3SYue Wang reset_control_deassert(mrst->apb);
1049c0ef6d3SYue Wang
1059c0ef6d3SYue Wang return 0;
1069c0ef6d3SYue Wang }
1079c0ef6d3SYue Wang
meson_pcie_get_mems(struct platform_device * pdev,struct meson_pcie * mp)1089c0ef6d3SYue Wang static int meson_pcie_get_mems(struct platform_device *pdev,
1099c0ef6d3SYue Wang struct meson_pcie *mp)
1109c0ef6d3SYue Wang {
1112f2cea1eSRob Herring struct dw_pcie *pci = &mp->pci;
1129c0ef6d3SYue Wang
1132f2cea1eSRob Herring pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
1142f2cea1eSRob Herring if (IS_ERR(pci->dbi_base))
1152f2cea1eSRob Herring return PTR_ERR(pci->dbi_base);
1162f2cea1eSRob Herring
1172f2cea1eSRob Herring mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
1182f2cea1eSRob Herring if (IS_ERR(mp->cfg_base))
1192f2cea1eSRob Herring return PTR_ERR(mp->cfg_base);
1209c0ef6d3SYue Wang
1219c0ef6d3SYue Wang return 0;
1229c0ef6d3SYue Wang }
1239c0ef6d3SYue Wang
meson_pcie_power_on(struct meson_pcie * mp)1244ff9f68fSNeil Armstrong static int meson_pcie_power_on(struct meson_pcie *mp)
1259c0ef6d3SYue Wang {
1264ff9f68fSNeil Armstrong int ret = 0;
1274ff9f68fSNeil Armstrong
1284ff9f68fSNeil Armstrong ret = phy_init(mp->phy);
1294ff9f68fSNeil Armstrong if (ret)
1304ff9f68fSNeil Armstrong return ret;
1314ff9f68fSNeil Armstrong
1324ff9f68fSNeil Armstrong ret = phy_power_on(mp->phy);
1334ff9f68fSNeil Armstrong if (ret) {
1344ff9f68fSNeil Armstrong phy_exit(mp->phy);
1354ff9f68fSNeil Armstrong return ret;
1364ff9f68fSNeil Armstrong }
1374ff9f68fSNeil Armstrong
1384ff9f68fSNeil Armstrong return 0;
1399c0ef6d3SYue Wang }
1409c0ef6d3SYue Wang
meson_pcie_power_off(struct meson_pcie * mp)1411e6bbc46SRemi Pommarel static void meson_pcie_power_off(struct meson_pcie *mp)
1421e6bbc46SRemi Pommarel {
1431e6bbc46SRemi Pommarel phy_power_off(mp->phy);
1441e6bbc46SRemi Pommarel phy_exit(mp->phy);
1451e6bbc46SRemi Pommarel }
1461e6bbc46SRemi Pommarel
meson_pcie_reset(struct meson_pcie * mp)1474ff9f68fSNeil Armstrong static int meson_pcie_reset(struct meson_pcie *mp)
1489c0ef6d3SYue Wang {
1499c0ef6d3SYue Wang struct meson_pcie_rc_reset *mrst = &mp->mrst;
1504ff9f68fSNeil Armstrong int ret = 0;
1519c0ef6d3SYue Wang
1524ff9f68fSNeil Armstrong ret = phy_reset(mp->phy);
1534ff9f68fSNeil Armstrong if (ret)
1544ff9f68fSNeil Armstrong return ret;
1559c0ef6d3SYue Wang
1569c0ef6d3SYue Wang reset_control_assert(mrst->port);
1579c0ef6d3SYue Wang reset_control_assert(mrst->apb);
1589c0ef6d3SYue Wang udelay(PCIE_RESET_DELAY);
1599c0ef6d3SYue Wang reset_control_deassert(mrst->port);
1609c0ef6d3SYue Wang reset_control_deassert(mrst->apb);
1619c0ef6d3SYue Wang udelay(PCIE_RESET_DELAY);
1624ff9f68fSNeil Armstrong
1634ff9f68fSNeil Armstrong return 0;
1649c0ef6d3SYue Wang }
1659c0ef6d3SYue Wang
meson_pcie_disable_clock(void * data)1669c0ef6d3SYue Wang static inline void meson_pcie_disable_clock(void *data)
1679c0ef6d3SYue Wang {
1689c0ef6d3SYue Wang struct clk *clk = data;
1699c0ef6d3SYue Wang
1709c0ef6d3SYue Wang clk_disable_unprepare(clk);
1719c0ef6d3SYue Wang }
1729c0ef6d3SYue Wang
meson_pcie_probe_clock(struct device * dev,const char * id,u64 rate)1739c0ef6d3SYue Wang static inline struct clk *meson_pcie_probe_clock(struct device *dev,
1749c0ef6d3SYue Wang const char *id, u64 rate)
1759c0ef6d3SYue Wang {
1769c0ef6d3SYue Wang struct clk *clk;
1779c0ef6d3SYue Wang int ret;
1789c0ef6d3SYue Wang
1799c0ef6d3SYue Wang clk = devm_clk_get(dev, id);
1809c0ef6d3SYue Wang if (IS_ERR(clk))
1819c0ef6d3SYue Wang return clk;
1829c0ef6d3SYue Wang
1839c0ef6d3SYue Wang if (rate) {
1849c0ef6d3SYue Wang ret = clk_set_rate(clk, rate);
1859c0ef6d3SYue Wang if (ret) {
1869c0ef6d3SYue Wang dev_err(dev, "set clk rate failed, ret = %d\n", ret);
1879c0ef6d3SYue Wang return ERR_PTR(ret);
1889c0ef6d3SYue Wang }
1899c0ef6d3SYue Wang }
1909c0ef6d3SYue Wang
1919c0ef6d3SYue Wang ret = clk_prepare_enable(clk);
1929c0ef6d3SYue Wang if (ret) {
1939c0ef6d3SYue Wang dev_err(dev, "couldn't enable clk\n");
1949c0ef6d3SYue Wang return ERR_PTR(ret);
1959c0ef6d3SYue Wang }
1969c0ef6d3SYue Wang
1979c0ef6d3SYue Wang devm_add_action_or_reset(dev, meson_pcie_disable_clock, clk);
1989c0ef6d3SYue Wang
1999c0ef6d3SYue Wang return clk;
2009c0ef6d3SYue Wang }
2019c0ef6d3SYue Wang
meson_pcie_probe_clocks(struct meson_pcie * mp)2029c0ef6d3SYue Wang static int meson_pcie_probe_clocks(struct meson_pcie *mp)
2039c0ef6d3SYue Wang {
2049c0ef6d3SYue Wang struct device *dev = mp->pci.dev;
2059c0ef6d3SYue Wang struct meson_pcie_clk_res *res = &mp->clk_res;
206eacaf7dcSNeil Armstrong
2079c0ef6d3SYue Wang res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
2089c0ef6d3SYue Wang if (IS_ERR(res->port_clk))
2099c0ef6d3SYue Wang return PTR_ERR(res->port_clk);
210eacaf7dcSNeil Armstrong
2119c0ef6d3SYue Wang res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
2129c0ef6d3SYue Wang if (IS_ERR(res->general_clk))
2139c0ef6d3SYue Wang return PTR_ERR(res->general_clk);
2149c0ef6d3SYue Wang
2159c0ef6d3SYue Wang res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
2169c0ef6d3SYue Wang if (IS_ERR(res->clk))
2179c0ef6d3SYue Wang return PTR_ERR(res->clk);
2189c0ef6d3SYue Wang
2192f2cea1eSRob Herring return 0;
2209c0ef6d3SYue Wang }
2219c0ef6d3SYue Wang
meson_cfg_readl(struct meson_pcie * mp,u32 reg)2229c0ef6d3SYue Wang static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
2239c0ef6d3SYue Wang {
2242f2cea1eSRob Herring return readl(mp->cfg_base + reg);
2259c0ef6d3SYue Wang }
2269c0ef6d3SYue Wang
meson_cfg_writel(struct meson_pcie * mp,u32 val,u32 reg)2279c0ef6d3SYue Wang static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
2289c0ef6d3SYue Wang {
2299c0ef6d3SYue Wang writel(val, mp->cfg_base + reg);
2304d3186a5SRemi Pommarel }
2314d3186a5SRemi Pommarel
meson_pcie_assert_reset(struct meson_pcie * mp)2329c0ef6d3SYue Wang static void meson_pcie_assert_reset(struct meson_pcie *mp)
2339c0ef6d3SYue Wang {
234886a9c13SRob Herring gpiod_set_value_cansleep(mp->reset_gpio, 1);
2359c0ef6d3SYue Wang udelay(500);
2369c0ef6d3SYue Wang gpiod_set_value_cansleep(mp->reset_gpio, 0);
2379c0ef6d3SYue Wang }
2389c0ef6d3SYue Wang
meson_pcie_ltssm_enable(struct meson_pcie * mp)2399c0ef6d3SYue Wang static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
2409c0ef6d3SYue Wang {
2419c0ef6d3SYue Wang u32 val;
2429c0ef6d3SYue Wang
2439c0ef6d3SYue Wang val = meson_cfg_readl(mp, PCIE_CFG0);
2449c0ef6d3SYue Wang val |= APP_LTSSM_ENABLE;
2459c0ef6d3SYue Wang meson_cfg_writel(mp, val, PCIE_CFG0);
2469c0ef6d3SYue Wang }
2479c0ef6d3SYue Wang
meson_size_to_payload(struct meson_pcie * mp,int size)2489c0ef6d3SYue Wang static int meson_size_to_payload(struct meson_pcie *mp, int size)
2499c0ef6d3SYue Wang {
2509c0ef6d3SYue Wang struct device *dev = mp->pci.dev;
2519c0ef6d3SYue Wang
2529c0ef6d3SYue Wang /*
2539c0ef6d3SYue Wang * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
2549c0ef6d3SYue Wang * So if input size is not 2^order alignment or less than 2^7 or bigger
2559c0ef6d3SYue Wang * than 2^12, just set to default size 2^(1+7).
2569c0ef6d3SYue Wang */
2579c0ef6d3SYue Wang if (!is_power_of_2(size) || size < 128 || size > 4096) {
2589c0ef6d3SYue Wang dev_warn(dev, "payload size %d, set to default 256\n", size);
2599c0ef6d3SYue Wang return 1;
2609c0ef6d3SYue Wang }
2619c0ef6d3SYue Wang
2622f2cea1eSRob Herring return fls(size) - 8;
2639c0ef6d3SYue Wang }
2642f2cea1eSRob Herring
meson_set_max_payload(struct meson_pcie * mp,int size)2659c0ef6d3SYue Wang static void meson_set_max_payload(struct meson_pcie *mp, int size)
2669c0ef6d3SYue Wang {
2672f2cea1eSRob Herring struct dw_pcie *pci = &mp->pci;
2682f2cea1eSRob Herring u32 val;
2692f2cea1eSRob Herring u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
2709c0ef6d3SYue Wang int max_payload_size = meson_size_to_payload(mp, size);
2712f2cea1eSRob Herring
2729c0ef6d3SYue Wang val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
2732f2cea1eSRob Herring val &= ~PCI_EXP_DEVCTL_PAYLOAD;
2749c0ef6d3SYue Wang dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
2759c0ef6d3SYue Wang
2769c0ef6d3SYue Wang val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
2779c0ef6d3SYue Wang val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
2782f2cea1eSRob Herring dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
2799c0ef6d3SYue Wang }
2802f2cea1eSRob Herring
meson_set_max_rd_req_size(struct meson_pcie * mp,int size)2819c0ef6d3SYue Wang static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
2829c0ef6d3SYue Wang {
2832f2cea1eSRob Herring struct dw_pcie *pci = &mp->pci;
2842f2cea1eSRob Herring u32 val;
2852f2cea1eSRob Herring u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
2869c0ef6d3SYue Wang int max_rd_req_size = meson_size_to_payload(mp, size);
2872f2cea1eSRob Herring
2889c0ef6d3SYue Wang val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
2892f2cea1eSRob Herring val &= ~PCI_EXP_DEVCTL_READRQ;
2909c0ef6d3SYue Wang dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
2919c0ef6d3SYue Wang
292886a9c13SRob Herring val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
2939c0ef6d3SYue Wang val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
294886a9c13SRob Herring dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
2959c0ef6d3SYue Wang }
296886a9c13SRob Herring
meson_pcie_start_link(struct dw_pcie * pci)2979c0ef6d3SYue Wang static int meson_pcie_start_link(struct dw_pcie *pci)
2989c0ef6d3SYue Wang {
299886a9c13SRob Herring struct meson_pcie *mp = to_meson_pcie(pci);
3009c0ef6d3SYue Wang
3019c0ef6d3SYue Wang meson_pcie_ltssm_enable(mp);
302e0ceb8f9SRob Herring meson_pcie_assert_reset(mp);
303e0ceb8f9SRob Herring
3049c0ef6d3SYue Wang return 0;
3059c0ef6d3SYue Wang }
3069c0ef6d3SYue Wang
meson_pcie_rd_own_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)307e0ceb8f9SRob Herring static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
3089c0ef6d3SYue Wang int where, int size, u32 *val)
3099c0ef6d3SYue Wang {
3109c0ef6d3SYue Wang int ret;
3119c0ef6d3SYue Wang
3129c0ef6d3SYue Wang ret = pci_generic_config_read(bus, devfn, where, size, val);
3139c0ef6d3SYue Wang if (ret != PCIBIOS_SUCCESSFUL)
3149c0ef6d3SYue Wang return ret;
3159c0ef6d3SYue Wang
316904b10fbSPali Rohár /*
317904b10fbSPali Rohár * There is a bug in the MESON AXG PCIe controller whereby software
318904b10fbSPali Rohár * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
319904b10fbSPali Rohár * the return value in the config accessors.
320904b10fbSPali Rohár */
321904b10fbSPali Rohár if ((where & ~3) == PCI_CLASS_REVISION) {
322904b10fbSPali Rohár if (size <= 2)
323904b10fbSPali Rohár *val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
3249c0ef6d3SYue Wang *val &= ~0xffffff00;
3259c0ef6d3SYue Wang *val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
3269c0ef6d3SYue Wang if (size <= 2)
3279c0ef6d3SYue Wang *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
328e0ceb8f9SRob Herring }
329e0ceb8f9SRob Herring
330e0ceb8f9SRob Herring return PCIBIOS_SUCCESSFUL;
331e0ceb8f9SRob Herring }
332e0ceb8f9SRob Herring
3339c0ef6d3SYue Wang static struct pci_ops meson_pci_ops = {
3349c0ef6d3SYue Wang .map_bus = dw_pcie_own_conf_map_bus,
3359c0ef6d3SYue Wang .read = meson_pcie_rd_own_conf,
3369c0ef6d3SYue Wang .write = pci_generic_config_write,
3379c0ef6d3SYue Wang };
3389c0ef6d3SYue Wang
meson_pcie_link_up(struct dw_pcie * pci)3399c0ef6d3SYue Wang static int meson_pcie_link_up(struct dw_pcie *pci)
3409c0ef6d3SYue Wang {
3419c0ef6d3SYue Wang struct meson_pcie *mp = to_meson_pcie(pci);
3429c0ef6d3SYue Wang struct device *dev = pci->dev;
3439c0ef6d3SYue Wang u32 speed_okay = 0;
3449c0ef6d3SYue Wang u32 cnt = 0;
3459c0ef6d3SYue Wang u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
3469c0ef6d3SYue Wang
3479c0ef6d3SYue Wang do {
3489c0ef6d3SYue Wang state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
3499c0ef6d3SYue Wang state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
3509c0ef6d3SYue Wang smlh_up = IS_SMLH_LINK_UP(state12);
3519c0ef6d3SYue Wang rdlh_up = IS_RDLH_LINK_UP(state12);
3529c0ef6d3SYue Wang ltssm_up = IS_LTSSM_UP(state12);
3539c0ef6d3SYue Wang
3549c0ef6d3SYue Wang if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
3559c0ef6d3SYue Wang speed_okay = 1;
3569c0ef6d3SYue Wang
3579c0ef6d3SYue Wang if (smlh_up)
3589c0ef6d3SYue Wang dev_dbg(dev, "smlh_link_up is on\n");
3599c0ef6d3SYue Wang if (rdlh_up)
3609c0ef6d3SYue Wang dev_dbg(dev, "rdlh_link_up is on\n");
3619c0ef6d3SYue Wang if (ltssm_up)
3629c0ef6d3SYue Wang dev_dbg(dev, "ltssm_up is on\n");
3639c0ef6d3SYue Wang if (speed_okay)
3649c0ef6d3SYue Wang dev_dbg(dev, "speed_okay\n");
3659c0ef6d3SYue Wang
3669c0ef6d3SYue Wang if (smlh_up && rdlh_up && ltssm_up && speed_okay)
3679c0ef6d3SYue Wang return 1;
3689c0ef6d3SYue Wang
3699c0ef6d3SYue Wang cnt++;
3709c0ef6d3SYue Wang
3719c0ef6d3SYue Wang udelay(10);
3729c0ef6d3SYue Wang } while (cnt < WAIT_LINKUP_TIMEOUT);
37360b3c27fSSerge Semin
3749c0ef6d3SYue Wang dev_err(dev, "error: wait linkup timeout\n");
3759c0ef6d3SYue Wang return 0;
3769c0ef6d3SYue Wang }
3779c0ef6d3SYue Wang
meson_pcie_host_init(struct dw_pcie_rp * pp)378e0ceb8f9SRob Herring static int meson_pcie_host_init(struct dw_pcie_rp *pp)
379e0ceb8f9SRob Herring {
380886a9c13SRob Herring struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
381886a9c13SRob Herring struct meson_pcie *mp = to_meson_pcie(pci);
3829c0ef6d3SYue Wang
3839c0ef6d3SYue Wang pp->bridge->ops = &meson_pci_ops;
3849c0ef6d3SYue Wang
3859c0ef6d3SYue Wang meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
3869c0ef6d3SYue Wang meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
3879c0ef6d3SYue Wang
3889c0ef6d3SYue Wang return 0;
3899c0ef6d3SYue Wang }
3909c0ef6d3SYue Wang
3919c0ef6d3SYue Wang static const struct dw_pcie_host_ops meson_pcie_host_ops = {
392886a9c13SRob Herring .host_init = meson_pcie_host_init,
3939c0ef6d3SYue Wang };
3949c0ef6d3SYue Wang
3959c0ef6d3SYue Wang static const struct dw_pcie_ops dw_pcie_ops = {
3969c0ef6d3SYue Wang .link_up = meson_pcie_link_up,
3979c0ef6d3SYue Wang .start_link = meson_pcie_start_link,
3989c0ef6d3SYue Wang };
3999c0ef6d3SYue Wang
meson_pcie_probe(struct platform_device * pdev)4009c0ef6d3SYue Wang static int meson_pcie_probe(struct platform_device *pdev)
4019c0ef6d3SYue Wang {
4029c0ef6d3SYue Wang struct device *dev = &pdev->dev;
4039c0ef6d3SYue Wang struct dw_pcie *pci;
4049c0ef6d3SYue Wang struct meson_pcie *mp;
4059c0ef6d3SYue Wang int ret;
4069c0ef6d3SYue Wang
4079c0ef6d3SYue Wang mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
4089c0ef6d3SYue Wang if (!mp)
40960f5b73fSRob Herring return -ENOMEM;
410244c40ccSRob Herring
4119c0ef6d3SYue Wang pci = &mp->pci;
4124ff9f68fSNeil Armstrong pci->dev = dev;
4131e6bbc46SRemi Pommarel pci->ops = &dw_pcie_ops;
4141e6bbc46SRemi Pommarel pci->pp.ops = &meson_pcie_host_ops;
4154ff9f68fSNeil Armstrong pci->num_lanes = 1;
4164ff9f68fSNeil Armstrong
4174ff9f68fSNeil Armstrong mp->phy = devm_phy_get(dev, "pcie");
4189c0ef6d3SYue Wang if (IS_ERR(mp->phy)) {
4199c0ef6d3SYue Wang dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
4209c0ef6d3SYue Wang return PTR_ERR(mp->phy);
4219c0ef6d3SYue Wang }
4229c0ef6d3SYue Wang
4239c0ef6d3SYue Wang mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
4249c0ef6d3SYue Wang if (IS_ERR(mp->reset_gpio)) {
4259c0ef6d3SYue Wang dev_err(dev, "get reset gpio failed\n");
4269c0ef6d3SYue Wang return PTR_ERR(mp->reset_gpio);
4279c0ef6d3SYue Wang }
4289c0ef6d3SYue Wang
4299c0ef6d3SYue Wang ret = meson_pcie_get_resets(mp);
4309c0ef6d3SYue Wang if (ret) {
4319c0ef6d3SYue Wang dev_err(dev, "get reset resource failed, %d\n", ret);
4329c0ef6d3SYue Wang return ret;
4339c0ef6d3SYue Wang }
4349c0ef6d3SYue Wang
4359c0ef6d3SYue Wang ret = meson_pcie_get_mems(pdev, mp);
4364ff9f68fSNeil Armstrong if (ret) {
4374ff9f68fSNeil Armstrong dev_err(dev, "get memory resource failed, %d\n", ret);
4384ff9f68fSNeil Armstrong return ret;
4394ff9f68fSNeil Armstrong }
4404ff9f68fSNeil Armstrong
4414ff9f68fSNeil Armstrong ret = meson_pcie_power_on(mp);
4424ff9f68fSNeil Armstrong if (ret) {
4434ff9f68fSNeil Armstrong dev_err(dev, "phy power on failed, %d\n", ret);
4444ff9f68fSNeil Armstrong return ret;
4454ff9f68fSNeil Armstrong }
4464ff9f68fSNeil Armstrong
4479c0ef6d3SYue Wang ret = meson_pcie_reset(mp);
4489c0ef6d3SYue Wang if (ret) {
4499c0ef6d3SYue Wang dev_err(dev, "reset failed, %d\n", ret);
4509c0ef6d3SYue Wang goto err_phy;
4514ff9f68fSNeil Armstrong }
4529c0ef6d3SYue Wang
4539c0ef6d3SYue Wang ret = meson_pcie_probe_clocks(mp);
4549c0ef6d3SYue Wang if (ret) {
4559c0ef6d3SYue Wang dev_err(dev, "init clock resources failed, %d\n", ret);
45660f5b73fSRob Herring goto err_phy;
4579c0ef6d3SYue Wang }
4589c0ef6d3SYue Wang
4594ff9f68fSNeil Armstrong platform_set_drvdata(pdev, mp);
4609c0ef6d3SYue Wang
4619c0ef6d3SYue Wang ret = dw_pcie_host_init(&pci->pp);
4629c0ef6d3SYue Wang if (ret < 0) {
4634ff9f68fSNeil Armstrong dev_err(dev, "Add PCIe port failed, %d\n", ret);
4644ff9f68fSNeil Armstrong goto err_phy;
4651e6bbc46SRemi Pommarel }
4664ff9f68fSNeil Armstrong
4674ff9f68fSNeil Armstrong return 0;
4684ff9f68fSNeil Armstrong
4699c0ef6d3SYue Wang err_phy:
4709c0ef6d3SYue Wang meson_pcie_power_off(mp);
4719c0ef6d3SYue Wang return ret;
4724ff9f68fSNeil Armstrong }
4734ff9f68fSNeil Armstrong
4744ff9f68fSNeil Armstrong static const struct of_device_id meson_pcie_of_match[] = {
4759c0ef6d3SYue Wang {
4769c0ef6d3SYue Wang .compatible = "amlogic,axg-pcie",
4779c0ef6d3SYue Wang },
478a98d2187SKevin Hilman {
4799c0ef6d3SYue Wang .compatible = "amlogic,g12a-pcie",
4809c0ef6d3SYue Wang },
4819c0ef6d3SYue Wang {},
4829c0ef6d3SYue Wang };
4839c0ef6d3SYue Wang MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
4849c0ef6d3SYue Wang
4859c0ef6d3SYue Wang static struct platform_driver meson_pcie_driver = {
4869c0ef6d3SYue Wang .probe = meson_pcie_probe,
4879c0ef6d3SYue Wang .driver = {
488a98d2187SKevin Hilman .name = "meson-pcie",
489a98d2187SKevin Hilman .of_match_table = meson_pcie_of_match,
490a98d2187SKevin Hilman },
491a98d2187SKevin Hilman };
492a98d2187SKevin Hilman
493 module_platform_driver(meson_pcie_driver);
494
495 MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
496 MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
497 MODULE_LICENSE("GPL v2");
498