1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe controller EP driver for Freescale Layerscape SoCs 4 * 5 * Copyright (C) 2018 NXP Semiconductor. 6 * 7 * Author: Xiaowei Bao <xiaowei.bao@nxp.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/of_pci.h> 13 #include <linux/of_platform.h> 14 #include <linux/of_address.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/resource.h> 18 19 #include "pcie-designware.h" 20 21 #define PEX_PF0_CONFIG 0xC0014 22 #define PEX_PF0_CFG_READY BIT(0) 23 24 /* PEX PFa PCIE PME and message interrupt registers*/ 25 #define PEX_PF0_PME_MES_DR 0xC0020 26 #define PEX_PF0_PME_MES_DR_LUD BIT(7) 27 #define PEX_PF0_PME_MES_DR_LDD BIT(9) 28 #define PEX_PF0_PME_MES_DR_HRD BIT(10) 29 30 #define PEX_PF0_PME_MES_IER 0xC0028 31 #define PEX_PF0_PME_MES_IER_LUDIE BIT(7) 32 #define PEX_PF0_PME_MES_IER_LDDIE BIT(9) 33 #define PEX_PF0_PME_MES_IER_HRDIE BIT(10) 34 35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) 36 37 struct ls_pcie_ep_drvdata { 38 u32 func_offset; 39 const struct dw_pcie_ep_ops *ops; 40 const struct dw_pcie_ops *dw_pcie_ops; 41 }; 42 43 struct ls_pcie_ep { 44 struct dw_pcie *pci; 45 struct pci_epc_features *ls_epc; 46 const struct ls_pcie_ep_drvdata *drvdata; 47 int irq; 48 u32 lnkcap; 49 bool big_endian; 50 }; 51 52 static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) 53 { 54 struct dw_pcie *pci = pcie->pci; 55 56 if (pcie->big_endian) 57 return ioread32be(pci->dbi_base + offset); 58 else 59 return ioread32(pci->dbi_base + offset); 60 } 61 62 static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) 63 { 64 struct dw_pcie *pci = pcie->pci; 65 66 if (pcie->big_endian) 67 iowrite32be(value, pci->dbi_base + offset); 68 else 69 iowrite32(value, pci->dbi_base + offset); 70 } 71 72 static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 73 { 74 struct ls_pcie_ep *pcie = dev_id; 75 struct dw_pcie *pci = pcie->pci; 76 u32 val, cfg; 77 u8 offset; 78 79 val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); 80 ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); 81 82 if (!val) 83 return IRQ_NONE; 84 85 if (val & PEX_PF0_PME_MES_DR_LUD) { 86 87 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 88 89 /* 90 * The values of the Maximum Link Width and Supported Link 91 * Speed from the Link Capabilities Register will be lost 92 * during link down or hot reset. Restore initial value 93 * that configured by the Reset Configuration Word (RCW). 94 */ 95 dw_pcie_dbi_ro_wr_en(pci); 96 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); 97 dw_pcie_dbi_ro_wr_dis(pci); 98 99 cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); 100 cfg |= PEX_PF0_CFG_READY; 101 ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); 102 dw_pcie_ep_linkup(&pci->ep); 103 104 dev_dbg(pci->dev, "Link up\n"); 105 } else if (val & PEX_PF0_PME_MES_DR_LDD) { 106 dev_dbg(pci->dev, "Link down\n"); 107 pci_epc_linkdown(pci->ep.epc); 108 } else if (val & PEX_PF0_PME_MES_DR_HRD) { 109 dev_dbg(pci->dev, "Hot reset\n"); 110 } 111 112 return IRQ_HANDLED; 113 } 114 115 static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, 116 struct platform_device *pdev) 117 { 118 u32 val; 119 int ret; 120 121 pcie->irq = platform_get_irq_byname(pdev, "pme"); 122 if (pcie->irq < 0) 123 return pcie->irq; 124 125 ret = devm_request_irq(&pdev->dev, pcie->irq, ls_pcie_ep_event_handler, 126 IRQF_SHARED, pdev->name, pcie); 127 if (ret) { 128 dev_err(&pdev->dev, "Can't register PCIe IRQ\n"); 129 return ret; 130 } 131 132 /* Enable interrupts */ 133 val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER); 134 val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE | 135 PEX_PF0_PME_MES_IER_LUDIE; 136 ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); 137 138 return 0; 139 } 140 141 static const struct pci_epc_features* 142 ls_pcie_ep_get_features(struct dw_pcie_ep *ep) 143 { 144 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 145 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); 146 147 return pcie->ls_epc; 148 } 149 150 static void ls_pcie_ep_init(struct dw_pcie_ep *ep) 151 { 152 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 153 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); 154 struct dw_pcie_ep_func *ep_func; 155 enum pci_barno bar; 156 157 ep_func = dw_pcie_ep_get_func_from_ep(ep, 0); 158 if (!ep_func) 159 return; 160 161 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 162 dw_pcie_ep_reset_bar(pci, bar); 163 164 pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false; 165 pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false; 166 } 167 168 static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 169 enum pci_epc_irq_type type, u16 interrupt_num) 170 { 171 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 172 173 switch (type) { 174 case PCI_EPC_IRQ_LEGACY: 175 return dw_pcie_ep_raise_legacy_irq(ep, func_no); 176 case PCI_EPC_IRQ_MSI: 177 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 178 case PCI_EPC_IRQ_MSIX: 179 return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no, 180 interrupt_num); 181 default: 182 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 183 return -EINVAL; 184 } 185 } 186 187 static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep, 188 u8 func_no) 189 { 190 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 191 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); 192 193 WARN_ON(func_no && !pcie->drvdata->func_offset); 194 return pcie->drvdata->func_offset * func_no; 195 } 196 197 static const struct dw_pcie_ep_ops ls_pcie_ep_ops = { 198 .ep_init = ls_pcie_ep_init, 199 .raise_irq = ls_pcie_ep_raise_irq, 200 .get_features = ls_pcie_ep_get_features, 201 .func_conf_select = ls_pcie_ep_func_conf_select, 202 }; 203 204 static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = { 205 .ops = &ls_pcie_ep_ops, 206 }; 207 208 static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = { 209 .func_offset = 0x20000, 210 .ops = &ls_pcie_ep_ops, 211 }; 212 213 static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = { 214 .func_offset = 0x8000, 215 .ops = &ls_pcie_ep_ops, 216 }; 217 218 static const struct of_device_id ls_pcie_ep_of_match[] = { 219 { .compatible = "fsl,ls1028a-pcie-ep", .data = &ls1_ep_drvdata }, 220 { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata }, 221 { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata }, 222 { .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata }, 223 { .compatible = "fsl,lx2160ar2-pcie-ep", .data = &lx2_ep_drvdata }, 224 { }, 225 }; 226 227 static int __init ls_pcie_ep_probe(struct platform_device *pdev) 228 { 229 struct device *dev = &pdev->dev; 230 struct dw_pcie *pci; 231 struct ls_pcie_ep *pcie; 232 struct pci_epc_features *ls_epc; 233 struct resource *dbi_base; 234 u8 offset; 235 int ret; 236 237 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 238 if (!pcie) 239 return -ENOMEM; 240 241 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 242 if (!pci) 243 return -ENOMEM; 244 245 ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL); 246 if (!ls_epc) 247 return -ENOMEM; 248 249 pcie->drvdata = of_device_get_match_data(dev); 250 251 pci->dev = dev; 252 pci->ops = pcie->drvdata->dw_pcie_ops; 253 254 ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4); 255 ls_epc->linkup_notifier = true; 256 257 pcie->pci = pci; 258 pcie->ls_epc = ls_epc; 259 260 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 261 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); 262 if (IS_ERR(pci->dbi_base)) 263 return PTR_ERR(pci->dbi_base); 264 265 pci->ep.ops = &ls_pcie_ep_ops; 266 267 pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); 268 269 platform_set_drvdata(pdev, pcie); 270 271 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 272 pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 273 274 ret = dw_pcie_ep_init(&pci->ep); 275 if (ret) 276 return ret; 277 278 return ls_pcie_ep_interrupt_init(pcie, pdev); 279 } 280 281 static struct platform_driver ls_pcie_ep_driver = { 282 .driver = { 283 .name = "layerscape-pcie-ep", 284 .of_match_table = ls_pcie_ep_of_match, 285 .suppress_bind_attrs = true, 286 }, 287 }; 288 builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe); 289