1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * http://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/msi.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/resource.h> 29 #include <linux/signal.h> 30 31 #include "../../pci.h" 32 #include "pcie-designware.h" 33 34 #define PCIE_VENDORID_MASK 0xffff 35 #define PCIE_DEVICEID_SHIFT 16 36 37 /* Application registers */ 38 #define CMD_STATUS 0x004 39 #define LTSSM_EN_VAL BIT(0) 40 #define OB_XLAT_EN_VAL BIT(1) 41 #define DBI_CS2 BIT(5) 42 43 #define CFG_SETUP 0x008 44 #define CFG_BUS(x) (((x) & 0xff) << 16) 45 #define CFG_DEVICE(x) (((x) & 0x1f) << 8) 46 #define CFG_FUNC(x) ((x) & 0x7) 47 #define CFG_TYPE1 BIT(24) 48 49 #define OB_SIZE 0x030 50 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 51 #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 52 #define OB_ENABLEN BIT(0) 53 #define OB_WIN_SIZE 8 /* 8MB */ 54 55 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 56 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 57 #define PCIE_EP_IRQ_SET 0x64 58 #define PCIE_EP_IRQ_CLR 0x68 59 #define INT_ENABLE BIT(0) 60 61 /* IRQ register defines */ 62 #define IRQ_EOI 0x050 63 64 #define MSI_IRQ 0x054 65 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 66 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 67 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 68 #define MSI_IRQ_OFFSET 4 69 70 #define IRQ_STATUS(n) (0x184 + ((n) << 4)) 71 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 72 #define INTx_EN BIT(0) 73 74 #define ERR_IRQ_STATUS 0x1c4 75 #define ERR_IRQ_ENABLE_SET 0x1c8 76 #define ERR_AER BIT(5) /* ECRC error */ 77 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 78 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 79 #define ERR_CORR BIT(3) /* Correctable error */ 80 #define ERR_NONFATAL BIT(2) /* Non-fatal error */ 81 #define ERR_FATAL BIT(1) /* Fatal error */ 82 #define ERR_SYS BIT(0) /* System error */ 83 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 84 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 85 86 /* PCIE controller device IDs */ 87 #define PCIE_RC_K2HK 0xb008 88 #define PCIE_RC_K2E 0xb009 89 #define PCIE_RC_K2L 0xb00a 90 #define PCIE_RC_K2G 0xb00b 91 92 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 93 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 94 95 #define EP 0x0 96 #define LEG_EP 0x1 97 #define RC 0x2 98 99 #define EXP_CAP_ID_OFFSET 0x70 100 101 #define KS_PCIE_SYSCLOCKOUTEN BIT(0) 102 103 #define AM654_PCIE_DEV_TYPE_MASK 0x3 104 #define AM654_WIN_SIZE SZ_64K 105 106 #define APP_ADDR_SPACE_0 (16 * SZ_1K) 107 108 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 109 110 struct ks_pcie_of_data { 111 enum dw_pcie_device_mode mode; 112 const struct dw_pcie_host_ops *host_ops; 113 const struct dw_pcie_ep_ops *ep_ops; 114 unsigned int version; 115 }; 116 117 struct keystone_pcie { 118 struct dw_pcie *pci; 119 /* PCI Device ID */ 120 u32 device_id; 121 int legacy_host_irqs[PCI_NUM_INTX]; 122 struct device_node *legacy_intc_np; 123 124 int msi_host_irq; 125 int num_lanes; 126 u32 num_viewport; 127 struct phy **phy; 128 struct device_link **link; 129 struct device_node *msi_intc_np; 130 struct irq_domain *legacy_irq_domain; 131 struct device_node *np; 132 133 /* Application register space */ 134 void __iomem *va_app_base; /* DT 1st resource */ 135 struct resource app; 136 bool is_am6; 137 }; 138 139 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 140 { 141 return readl(ks_pcie->va_app_base + offset); 142 } 143 144 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 145 u32 val) 146 { 147 writel(val, ks_pcie->va_app_base + offset); 148 } 149 150 static void ks_pcie_msi_irq_ack(struct irq_data *data) 151 { 152 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 153 struct keystone_pcie *ks_pcie; 154 u32 irq = data->hwirq; 155 struct dw_pcie *pci; 156 u32 reg_offset; 157 u32 bit_pos; 158 159 pci = to_dw_pcie_from_pp(pp); 160 ks_pcie = to_keystone_pcie(pci); 161 162 reg_offset = irq % 8; 163 bit_pos = irq >> 3; 164 165 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 166 BIT(bit_pos)); 167 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 168 } 169 170 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 171 { 172 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 173 struct keystone_pcie *ks_pcie; 174 struct dw_pcie *pci; 175 u64 msi_target; 176 177 pci = to_dw_pcie_from_pp(pp); 178 ks_pcie = to_keystone_pcie(pci); 179 180 msi_target = ks_pcie->app.start + MSI_IRQ; 181 msg->address_lo = lower_32_bits(msi_target); 182 msg->address_hi = upper_32_bits(msi_target); 183 msg->data = data->hwirq; 184 185 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 186 (int)data->hwirq, msg->address_hi, msg->address_lo); 187 } 188 189 static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 190 const struct cpumask *mask, bool force) 191 { 192 return -EINVAL; 193 } 194 195 static void ks_pcie_msi_mask(struct irq_data *data) 196 { 197 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 198 struct keystone_pcie *ks_pcie; 199 u32 irq = data->hwirq; 200 struct dw_pcie *pci; 201 unsigned long flags; 202 u32 reg_offset; 203 u32 bit_pos; 204 205 raw_spin_lock_irqsave(&pp->lock, flags); 206 207 pci = to_dw_pcie_from_pp(pp); 208 ks_pcie = to_keystone_pcie(pci); 209 210 reg_offset = irq % 8; 211 bit_pos = irq >> 3; 212 213 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 214 BIT(bit_pos)); 215 216 raw_spin_unlock_irqrestore(&pp->lock, flags); 217 } 218 219 static void ks_pcie_msi_unmask(struct irq_data *data) 220 { 221 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 222 struct keystone_pcie *ks_pcie; 223 u32 irq = data->hwirq; 224 struct dw_pcie *pci; 225 unsigned long flags; 226 u32 reg_offset; 227 u32 bit_pos; 228 229 raw_spin_lock_irqsave(&pp->lock, flags); 230 231 pci = to_dw_pcie_from_pp(pp); 232 ks_pcie = to_keystone_pcie(pci); 233 234 reg_offset = irq % 8; 235 bit_pos = irq >> 3; 236 237 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 238 BIT(bit_pos)); 239 240 raw_spin_unlock_irqrestore(&pp->lock, flags); 241 } 242 243 static struct irq_chip ks_pcie_msi_irq_chip = { 244 .name = "KEYSTONE-PCI-MSI", 245 .irq_ack = ks_pcie_msi_irq_ack, 246 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 247 .irq_set_affinity = ks_pcie_msi_set_affinity, 248 .irq_mask = ks_pcie_msi_mask, 249 .irq_unmask = ks_pcie_msi_unmask, 250 }; 251 252 static int ks_pcie_msi_host_init(struct pcie_port *pp) 253 { 254 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 255 return dw_pcie_allocate_domains(pp); 256 } 257 258 static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, 259 int offset) 260 { 261 struct dw_pcie *pci = ks_pcie->pci; 262 struct device *dev = pci->dev; 263 u32 pending; 264 int virq; 265 266 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 267 268 if (BIT(0) & pending) { 269 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); 270 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); 271 generic_handle_irq(virq); 272 } 273 274 /* EOI the INTx interrupt */ 275 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 276 } 277 278 /* 279 * Dummy function so that DW core doesn't configure MSI 280 */ 281 static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) 282 { 283 return 0; 284 } 285 286 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 287 { 288 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 289 } 290 291 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 292 { 293 u32 reg; 294 struct device *dev = ks_pcie->pci->dev; 295 296 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 297 if (!reg) 298 return IRQ_NONE; 299 300 if (reg & ERR_SYS) 301 dev_err(dev, "System Error\n"); 302 303 if (reg & ERR_FATAL) 304 dev_err(dev, "Fatal Error\n"); 305 306 if (reg & ERR_NONFATAL) 307 dev_dbg(dev, "Non Fatal Error\n"); 308 309 if (reg & ERR_CORR) 310 dev_dbg(dev, "Correctable Error\n"); 311 312 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 313 dev_err(dev, "AXI tag lookup fatal Error\n"); 314 315 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 316 dev_err(dev, "ECRC Error\n"); 317 318 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 319 320 return IRQ_HANDLED; 321 } 322 323 static void ks_pcie_ack_legacy_irq(struct irq_data *d) 324 { 325 } 326 327 static void ks_pcie_mask_legacy_irq(struct irq_data *d) 328 { 329 } 330 331 static void ks_pcie_unmask_legacy_irq(struct irq_data *d) 332 { 333 } 334 335 static struct irq_chip ks_pcie_legacy_irq_chip = { 336 .name = "Keystone-PCI-Legacy-IRQ", 337 .irq_ack = ks_pcie_ack_legacy_irq, 338 .irq_mask = ks_pcie_mask_legacy_irq, 339 .irq_unmask = ks_pcie_unmask_legacy_irq, 340 }; 341 342 static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, 343 unsigned int irq, 344 irq_hw_number_t hw_irq) 345 { 346 irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip, 347 handle_level_irq); 348 irq_set_chip_data(irq, d->host_data); 349 350 return 0; 351 } 352 353 static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = { 354 .map = ks_pcie_init_legacy_irq_map, 355 .xlate = irq_domain_xlate_onetwocell, 356 }; 357 358 /** 359 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask 360 * registers 361 * 362 * Since modification of dbi_cs2 involves different clock domain, read the 363 * status back to ensure the transition is complete. 364 */ 365 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 366 { 367 u32 val; 368 369 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 370 val |= DBI_CS2; 371 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 372 373 do { 374 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 375 } while (!(val & DBI_CS2)); 376 } 377 378 /** 379 * ks_pcie_clear_dbi_mode() - Disable DBI mode 380 * 381 * Since modification of dbi_cs2 involves different clock domain, read the 382 * status back to ensure the transition is complete. 383 */ 384 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 385 { 386 u32 val; 387 388 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 389 val &= ~DBI_CS2; 390 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 391 392 do { 393 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 394 } while (val & DBI_CS2); 395 } 396 397 static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 398 { 399 u32 val; 400 u32 num_viewport = ks_pcie->num_viewport; 401 struct dw_pcie *pci = ks_pcie->pci; 402 struct pcie_port *pp = &pci->pp; 403 u64 start = pp->mem->start; 404 u64 end = pp->mem->end; 405 int i; 406 407 /* Disable BARs for inbound access */ 408 ks_pcie_set_dbi_mode(ks_pcie); 409 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 410 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 411 ks_pcie_clear_dbi_mode(ks_pcie); 412 413 if (ks_pcie->is_am6) 414 return; 415 416 val = ilog2(OB_WIN_SIZE); 417 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 418 419 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 420 for (i = 0; i < num_viewport && (start < end); i++) { 421 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 422 lower_32_bits(start) | OB_ENABLEN); 423 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 424 upper_32_bits(start)); 425 start += OB_WIN_SIZE * SZ_1M; 426 } 427 428 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 429 val |= OB_XLAT_EN_VAL; 430 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 431 } 432 433 static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 434 unsigned int devfn, int where, int size, 435 u32 *val) 436 { 437 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 438 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 439 u32 reg; 440 441 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 442 CFG_FUNC(PCI_FUNC(devfn)); 443 if (bus->parent->number != pp->root_bus_nr) 444 reg |= CFG_TYPE1; 445 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 446 447 return dw_pcie_read(pp->va_cfg0_base + where, size, val); 448 } 449 450 static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 451 unsigned int devfn, int where, int size, 452 u32 val) 453 { 454 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 455 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 456 u32 reg; 457 458 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 459 CFG_FUNC(PCI_FUNC(devfn)); 460 if (bus->parent->number != pp->root_bus_nr) 461 reg |= CFG_TYPE1; 462 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 463 464 return dw_pcie_write(pp->va_cfg0_base + where, size, val); 465 } 466 467 /** 468 * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization 469 * 470 * This sets BAR0 to enable inbound access for MSI_IRQ register 471 */ 472 static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) 473 { 474 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 475 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 476 477 /* Configure and set up BAR0 */ 478 ks_pcie_set_dbi_mode(ks_pcie); 479 480 /* Enable BAR0 */ 481 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 482 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 483 484 ks_pcie_clear_dbi_mode(ks_pcie); 485 486 /* 487 * For BAR0, just setting bus address for inbound writes (MSI) should 488 * be sufficient. Use physical address to avoid any conflicts. 489 */ 490 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 491 } 492 493 /** 494 * ks_pcie_link_up() - Check if link up 495 */ 496 static int ks_pcie_link_up(struct dw_pcie *pci) 497 { 498 u32 val; 499 500 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 501 val &= PORT_LOGIC_LTSSM_STATE_MASK; 502 return (val == PORT_LOGIC_LTSSM_STATE_L0); 503 } 504 505 static void ks_pcie_stop_link(struct dw_pcie *pci) 506 { 507 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 508 u32 val; 509 510 /* Disable Link training */ 511 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 512 val &= ~LTSSM_EN_VAL; 513 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 514 } 515 516 static int ks_pcie_start_link(struct dw_pcie *pci) 517 { 518 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 519 struct device *dev = pci->dev; 520 u32 val; 521 522 if (dw_pcie_link_up(pci)) { 523 dev_dbg(dev, "link is already up\n"); 524 return 0; 525 } 526 527 /* Initiate Link Training */ 528 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 529 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 530 531 return 0; 532 } 533 534 static void ks_pcie_quirk(struct pci_dev *dev) 535 { 536 struct pci_bus *bus = dev->bus; 537 struct pci_dev *bridge; 538 static const struct pci_device_id rc_pci_devids[] = { 539 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 540 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 541 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 542 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 543 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 544 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 545 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 546 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 547 { 0, }, 548 }; 549 550 if (pci_is_root_bus(bus)) 551 bridge = dev; 552 553 /* look for the host bridge */ 554 while (!pci_is_root_bus(bus)) { 555 bridge = bus->self; 556 bus = bus->parent; 557 } 558 559 if (!bridge) 560 return; 561 562 /* 563 * Keystone PCI controller has a h/w limitation of 564 * 256 bytes maximum read request size. It can't handle 565 * anything higher than this. So force this limit on 566 * all downstream devices. 567 */ 568 if (pci_match_id(rc_pci_devids, bridge)) { 569 if (pcie_get_readrq(dev) > 256) { 570 dev_info(&dev->dev, "limiting MRRS to 256\n"); 571 pcie_set_readrq(dev, 256); 572 } 573 } 574 } 575 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 576 577 static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 578 { 579 unsigned int irq = desc->irq_data.hwirq; 580 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 581 u32 offset = irq - ks_pcie->msi_host_irq; 582 struct dw_pcie *pci = ks_pcie->pci; 583 struct pcie_port *pp = &pci->pp; 584 struct device *dev = pci->dev; 585 struct irq_chip *chip = irq_desc_get_chip(desc); 586 u32 vector, virq, reg, pos; 587 588 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 589 590 /* 591 * The chained irq handler installation would have replaced normal 592 * interrupt driver handler so we need to take care of mask/unmask and 593 * ack operation. 594 */ 595 chained_irq_enter(chip, desc); 596 597 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 598 /* 599 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 600 * shows 1, 9, 17, 25 and so forth 601 */ 602 for (pos = 0; pos < 4; pos++) { 603 if (!(reg & BIT(pos))) 604 continue; 605 606 vector = offset + (pos << 3); 607 virq = irq_linear_revmap(pp->irq_domain, vector); 608 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector, 609 virq); 610 generic_handle_irq(virq); 611 } 612 613 chained_irq_exit(chip, desc); 614 } 615 616 /** 617 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt 618 * @irq: IRQ line for legacy interrupts 619 * @desc: Pointer to irq descriptor 620 * 621 * Traverse through pending legacy interrupts and invoke handler for each. Also 622 * takes care of interrupt controller level mask/ack operation. 623 */ 624 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) 625 { 626 unsigned int irq = irq_desc_get_irq(desc); 627 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 628 struct dw_pcie *pci = ks_pcie->pci; 629 struct device *dev = pci->dev; 630 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; 631 struct irq_chip *chip = irq_desc_get_chip(desc); 632 633 dev_dbg(dev, ": Handling legacy irq %d\n", irq); 634 635 /* 636 * The chained irq handler installation would have replaced normal 637 * interrupt driver handler so we need to take care of mask/unmask and 638 * ack operation. 639 */ 640 chained_irq_enter(chip, desc); 641 ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); 642 chained_irq_exit(chip, desc); 643 } 644 645 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 646 { 647 struct device *dev = ks_pcie->pci->dev; 648 struct device_node *np = ks_pcie->np; 649 struct device_node *intc_np; 650 struct irq_data *irq_data; 651 int irq_count, irq, ret, i; 652 653 if (!IS_ENABLED(CONFIG_PCI_MSI)) 654 return 0; 655 656 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 657 if (!intc_np) { 658 if (ks_pcie->is_am6) 659 return 0; 660 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 661 return -EINVAL; 662 } 663 664 irq_count = of_irq_count(intc_np); 665 if (!irq_count) { 666 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 667 ret = -EINVAL; 668 goto err; 669 } 670 671 for (i = 0; i < irq_count; i++) { 672 irq = irq_of_parse_and_map(intc_np, i); 673 if (!irq) { 674 ret = -EINVAL; 675 goto err; 676 } 677 678 if (!ks_pcie->msi_host_irq) { 679 irq_data = irq_get_irq_data(irq); 680 if (!irq_data) { 681 ret = -EINVAL; 682 goto err; 683 } 684 ks_pcie->msi_host_irq = irq_data->hwirq; 685 } 686 687 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 688 ks_pcie); 689 } 690 691 of_node_put(intc_np); 692 return 0; 693 694 err: 695 of_node_put(intc_np); 696 return ret; 697 } 698 699 static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) 700 { 701 struct device *dev = ks_pcie->pci->dev; 702 struct irq_domain *legacy_irq_domain; 703 struct device_node *np = ks_pcie->np; 704 struct device_node *intc_np; 705 int irq_count, irq, ret = 0, i; 706 707 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 708 if (!intc_np) { 709 /* 710 * Since legacy interrupts are modeled as edge-interrupts in 711 * AM6, keep it disabled for now. 712 */ 713 if (ks_pcie->is_am6) 714 return 0; 715 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 716 return -EINVAL; 717 } 718 719 irq_count = of_irq_count(intc_np); 720 if (!irq_count) { 721 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 722 ret = -EINVAL; 723 goto err; 724 } 725 726 for (i = 0; i < irq_count; i++) { 727 irq = irq_of_parse_and_map(intc_np, i); 728 if (!irq) { 729 ret = -EINVAL; 730 goto err; 731 } 732 ks_pcie->legacy_host_irqs[i] = irq; 733 734 irq_set_chained_handler_and_data(irq, 735 ks_pcie_legacy_irq_handler, 736 ks_pcie); 737 } 738 739 legacy_irq_domain = 740 irq_domain_add_linear(intc_np, PCI_NUM_INTX, 741 &ks_pcie_legacy_irq_domain_ops, NULL); 742 if (!legacy_irq_domain) { 743 dev_err(dev, "Failed to add irq domain for legacy irqs\n"); 744 ret = -EINVAL; 745 goto err; 746 } 747 ks_pcie->legacy_irq_domain = legacy_irq_domain; 748 749 for (i = 0; i < PCI_NUM_INTX; i++) 750 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 751 752 err: 753 of_node_put(intc_np); 754 return ret; 755 } 756 757 #ifdef CONFIG_ARM 758 /* 759 * When a PCI device does not exist during config cycles, keystone host gets a 760 * bus error instead of returning 0xffffffff. This handler always returns 0 761 * for this kind of faults. 762 */ 763 static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 764 struct pt_regs *regs) 765 { 766 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 767 768 if ((instr & 0x0e100090) == 0x00100090) { 769 int reg = (instr >> 12) & 15; 770 771 regs->uregs[reg] = -1; 772 regs->ARM_pc += 4; 773 } 774 775 return 0; 776 } 777 #endif 778 779 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 780 { 781 int ret; 782 unsigned int id; 783 struct regmap *devctrl_regs; 784 struct dw_pcie *pci = ks_pcie->pci; 785 struct device *dev = pci->dev; 786 struct device_node *np = dev->of_node; 787 788 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 789 if (IS_ERR(devctrl_regs)) 790 return PTR_ERR(devctrl_regs); 791 792 ret = regmap_read(devctrl_regs, 0, &id); 793 if (ret) 794 return ret; 795 796 dw_pcie_dbi_ro_wr_en(pci); 797 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 798 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 799 dw_pcie_dbi_ro_wr_dis(pci); 800 801 return 0; 802 } 803 804 static int __init ks_pcie_host_init(struct pcie_port *pp) 805 { 806 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 807 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 808 int ret; 809 810 ret = ks_pcie_config_legacy_irq(ks_pcie); 811 if (ret) 812 return ret; 813 814 ret = ks_pcie_config_msi_irq(ks_pcie); 815 if (ret) 816 return ret; 817 818 dw_pcie_setup_rc(pp); 819 820 ks_pcie_stop_link(pci); 821 ks_pcie_setup_rc_app_regs(ks_pcie); 822 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 823 pci->dbi_base + PCI_IO_BASE); 824 825 ret = ks_pcie_init_id(ks_pcie); 826 if (ret < 0) 827 return ret; 828 829 #ifdef CONFIG_ARM 830 /* 831 * PCIe access errors that result into OCP errors are caught by ARM as 832 * "External aborts" 833 */ 834 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 835 "Asynchronous external abort"); 836 #endif 837 838 ks_pcie_start_link(pci); 839 dw_pcie_wait_for_link(pci); 840 841 return 0; 842 } 843 844 static const struct dw_pcie_host_ops ks_pcie_host_ops = { 845 .rd_other_conf = ks_pcie_rd_other_conf, 846 .wr_other_conf = ks_pcie_wr_other_conf, 847 .host_init = ks_pcie_host_init, 848 .msi_host_init = ks_pcie_msi_host_init, 849 .scan_bus = ks_pcie_v3_65_scan_bus, 850 }; 851 852 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 853 .host_init = ks_pcie_host_init, 854 .msi_host_init = ks_pcie_am654_msi_host_init, 855 }; 856 857 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 858 { 859 struct keystone_pcie *ks_pcie = priv; 860 861 return ks_pcie_handle_error_irq(ks_pcie); 862 } 863 864 static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, 865 struct platform_device *pdev) 866 { 867 struct dw_pcie *pci = ks_pcie->pci; 868 struct pcie_port *pp = &pci->pp; 869 struct device *dev = &pdev->dev; 870 struct resource *res; 871 int ret; 872 873 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 874 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); 875 if (IS_ERR(pp->va_cfg0_base)) 876 return PTR_ERR(pp->va_cfg0_base); 877 878 pp->va_cfg1_base = pp->va_cfg0_base; 879 880 ret = dw_pcie_host_init(pp); 881 if (ret) { 882 dev_err(dev, "failed to initialize host\n"); 883 return ret; 884 } 885 886 return 0; 887 } 888 889 static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, 890 u32 reg, size_t size) 891 { 892 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 893 u32 val; 894 895 ks_pcie_set_dbi_mode(ks_pcie); 896 dw_pcie_read(base + reg, size, &val); 897 ks_pcie_clear_dbi_mode(ks_pcie); 898 return val; 899 } 900 901 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 902 u32 reg, size_t size, u32 val) 903 { 904 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 905 906 ks_pcie_set_dbi_mode(ks_pcie); 907 dw_pcie_write(base + reg, size, val); 908 ks_pcie_clear_dbi_mode(ks_pcie); 909 } 910 911 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 912 .start_link = ks_pcie_start_link, 913 .stop_link = ks_pcie_stop_link, 914 .link_up = ks_pcie_link_up, 915 .read_dbi2 = ks_pcie_am654_read_dbi2, 916 .write_dbi2 = ks_pcie_am654_write_dbi2, 917 }; 918 919 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 920 { 921 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 922 int flags; 923 924 ep->page_size = AM654_WIN_SIZE; 925 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 926 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 927 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 928 } 929 930 static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) 931 { 932 struct dw_pcie *pci = ks_pcie->pci; 933 u8 int_pin; 934 935 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 936 if (int_pin == 0 || int_pin > 4) 937 return; 938 939 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 940 INT_ENABLE); 941 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 942 mdelay(1); 943 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 944 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 945 INT_ENABLE); 946 } 947 948 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 949 enum pci_epc_irq_type type, 950 u16 interrupt_num) 951 { 952 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 953 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 954 955 switch (type) { 956 case PCI_EPC_IRQ_LEGACY: 957 ks_pcie_am654_raise_legacy_irq(ks_pcie); 958 break; 959 case PCI_EPC_IRQ_MSI: 960 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 961 break; 962 case PCI_EPC_IRQ_MSIX: 963 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 964 break; 965 default: 966 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 967 return -EINVAL; 968 } 969 970 return 0; 971 } 972 973 static const struct pci_epc_features ks_pcie_am654_epc_features = { 974 .linkup_notifier = false, 975 .msi_capable = true, 976 .msix_capable = true, 977 .reserved_bar = 1 << BAR_0 | 1 << BAR_1, 978 .bar_fixed_64bit = 1 << BAR_0, 979 .bar_fixed_size[2] = SZ_1M, 980 .bar_fixed_size[3] = SZ_64K, 981 .bar_fixed_size[4] = 256, 982 .bar_fixed_size[5] = SZ_1M, 983 .align = SZ_1M, 984 }; 985 986 static const struct pci_epc_features* 987 ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 988 { 989 return &ks_pcie_am654_epc_features; 990 } 991 992 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 993 .ep_init = ks_pcie_am654_ep_init, 994 .raise_irq = ks_pcie_am654_raise_irq, 995 .get_features = &ks_pcie_am654_get_features, 996 }; 997 998 static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, 999 struct platform_device *pdev) 1000 { 1001 int ret; 1002 struct dw_pcie_ep *ep; 1003 struct resource *res; 1004 struct device *dev = &pdev->dev; 1005 struct dw_pcie *pci = ks_pcie->pci; 1006 1007 ep = &pci->ep; 1008 1009 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 1010 if (!res) 1011 return -EINVAL; 1012 1013 ep->phys_base = res->start; 1014 ep->addr_size = resource_size(res); 1015 1016 ret = dw_pcie_ep_init(ep); 1017 if (ret) { 1018 dev_err(dev, "failed to initialize endpoint\n"); 1019 return ret; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 1026 { 1027 int num_lanes = ks_pcie->num_lanes; 1028 1029 while (num_lanes--) { 1030 phy_power_off(ks_pcie->phy[num_lanes]); 1031 phy_exit(ks_pcie->phy[num_lanes]); 1032 } 1033 } 1034 1035 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 1036 { 1037 int i; 1038 int ret; 1039 int num_lanes = ks_pcie->num_lanes; 1040 1041 for (i = 0; i < num_lanes; i++) { 1042 ret = phy_reset(ks_pcie->phy[i]); 1043 if (ret < 0) 1044 goto err_phy; 1045 1046 ret = phy_init(ks_pcie->phy[i]); 1047 if (ret < 0) 1048 goto err_phy; 1049 1050 ret = phy_power_on(ks_pcie->phy[i]); 1051 if (ret < 0) { 1052 phy_exit(ks_pcie->phy[i]); 1053 goto err_phy; 1054 } 1055 } 1056 1057 return 0; 1058 1059 err_phy: 1060 while (--i >= 0) { 1061 phy_power_off(ks_pcie->phy[i]); 1062 phy_exit(ks_pcie->phy[i]); 1063 } 1064 1065 return ret; 1066 } 1067 1068 static int ks_pcie_set_mode(struct device *dev) 1069 { 1070 struct device_node *np = dev->of_node; 1071 struct regmap *syscon; 1072 u32 val; 1073 u32 mask; 1074 int ret = 0; 1075 1076 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1077 if (IS_ERR(syscon)) 1078 return 0; 1079 1080 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1081 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1082 1083 ret = regmap_update_bits(syscon, 0, mask, val); 1084 if (ret) { 1085 dev_err(dev, "failed to set pcie mode\n"); 1086 return ret; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static int ks_pcie_am654_set_mode(struct device *dev, 1093 enum dw_pcie_device_mode mode) 1094 { 1095 struct device_node *np = dev->of_node; 1096 struct regmap *syscon; 1097 u32 val; 1098 u32 mask; 1099 int ret = 0; 1100 1101 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1102 if (IS_ERR(syscon)) 1103 return 0; 1104 1105 mask = AM654_PCIE_DEV_TYPE_MASK; 1106 1107 switch (mode) { 1108 case DW_PCIE_RC_TYPE: 1109 val = RC; 1110 break; 1111 case DW_PCIE_EP_TYPE: 1112 val = EP; 1113 break; 1114 default: 1115 dev_err(dev, "INVALID device type %d\n", mode); 1116 return -EINVAL; 1117 } 1118 1119 ret = regmap_update_bits(syscon, 0, mask, val); 1120 if (ret) { 1121 dev_err(dev, "failed to set pcie mode\n"); 1122 return ret; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed) 1129 { 1130 u32 val; 1131 1132 dw_pcie_dbi_ro_wr_en(pci); 1133 1134 val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); 1135 if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { 1136 val &= ~((u32)PCI_EXP_LNKCAP_SLS); 1137 val |= link_speed; 1138 dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP, 1139 val); 1140 } 1141 1142 val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); 1143 if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { 1144 val &= ~((u32)PCI_EXP_LNKCAP_SLS); 1145 val |= link_speed; 1146 dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2, 1147 val); 1148 } 1149 1150 dw_pcie_dbi_ro_wr_dis(pci); 1151 } 1152 1153 static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1154 .host_ops = &ks_pcie_host_ops, 1155 .version = 0x365A, 1156 }; 1157 1158 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1159 .host_ops = &ks_pcie_am654_host_ops, 1160 .mode = DW_PCIE_RC_TYPE, 1161 .version = 0x490A, 1162 }; 1163 1164 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1165 .ep_ops = &ks_pcie_am654_ep_ops, 1166 .mode = DW_PCIE_EP_TYPE, 1167 .version = 0x490A, 1168 }; 1169 1170 static const struct of_device_id ks_pcie_of_match[] = { 1171 { 1172 .type = "pci", 1173 .data = &ks_pcie_rc_of_data, 1174 .compatible = "ti,keystone-pcie", 1175 }, 1176 { 1177 .data = &ks_pcie_am654_rc_of_data, 1178 .compatible = "ti,am654-pcie-rc", 1179 }, 1180 { 1181 .data = &ks_pcie_am654_ep_of_data, 1182 .compatible = "ti,am654-pcie-ep", 1183 }, 1184 { }, 1185 }; 1186 1187 static int __init ks_pcie_probe(struct platform_device *pdev) 1188 { 1189 const struct dw_pcie_host_ops *host_ops; 1190 const struct dw_pcie_ep_ops *ep_ops; 1191 struct device *dev = &pdev->dev; 1192 struct device_node *np = dev->of_node; 1193 const struct ks_pcie_of_data *data; 1194 const struct of_device_id *match; 1195 enum dw_pcie_device_mode mode; 1196 struct dw_pcie *pci; 1197 struct keystone_pcie *ks_pcie; 1198 struct device_link **link; 1199 struct gpio_desc *gpiod; 1200 void __iomem *atu_base; 1201 struct resource *res; 1202 unsigned int version; 1203 void __iomem *base; 1204 u32 num_viewport; 1205 struct phy **phy; 1206 int link_speed; 1207 u32 num_lanes; 1208 char name[10]; 1209 int ret; 1210 int irq; 1211 int i; 1212 1213 match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); 1214 data = (struct ks_pcie_of_data *)match->data; 1215 if (!data) 1216 return -EINVAL; 1217 1218 version = data->version; 1219 host_ops = data->host_ops; 1220 ep_ops = data->ep_ops; 1221 mode = data->mode; 1222 1223 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1224 if (!ks_pcie) 1225 return -ENOMEM; 1226 1227 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1228 if (!pci) 1229 return -ENOMEM; 1230 1231 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1232 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1233 if (IS_ERR(ks_pcie->va_app_base)) 1234 return PTR_ERR(ks_pcie->va_app_base); 1235 1236 ks_pcie->app = *res; 1237 1238 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1239 base = devm_pci_remap_cfg_resource(dev, res); 1240 if (IS_ERR(base)) 1241 return PTR_ERR(base); 1242 1243 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1244 ks_pcie->is_am6 = true; 1245 1246 pci->dbi_base = base; 1247 pci->dbi_base2 = base; 1248 pci->dev = dev; 1249 pci->ops = &ks_pcie_dw_pcie_ops; 1250 pci->version = version; 1251 1252 irq = platform_get_irq(pdev, 0); 1253 if (irq < 0) { 1254 dev_err(dev, "missing IRQ resource: %d\n", irq); 1255 return irq; 1256 } 1257 1258 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1259 "ks-pcie-error-irq", ks_pcie); 1260 if (ret < 0) { 1261 dev_err(dev, "failed to request error IRQ %d\n", 1262 irq); 1263 return ret; 1264 } 1265 1266 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1267 if (ret) 1268 num_lanes = 1; 1269 1270 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1271 if (!phy) 1272 return -ENOMEM; 1273 1274 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1275 if (!link) 1276 return -ENOMEM; 1277 1278 for (i = 0; i < num_lanes; i++) { 1279 snprintf(name, sizeof(name), "pcie-phy%d", i); 1280 phy[i] = devm_phy_optional_get(dev, name); 1281 if (IS_ERR(phy[i])) { 1282 ret = PTR_ERR(phy[i]); 1283 goto err_link; 1284 } 1285 1286 if (!phy[i]) 1287 continue; 1288 1289 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1290 if (!link[i]) { 1291 ret = -EINVAL; 1292 goto err_link; 1293 } 1294 } 1295 1296 ks_pcie->np = np; 1297 ks_pcie->pci = pci; 1298 ks_pcie->link = link; 1299 ks_pcie->num_lanes = num_lanes; 1300 ks_pcie->phy = phy; 1301 1302 gpiod = devm_gpiod_get_optional(dev, "reset", 1303 GPIOD_OUT_LOW); 1304 if (IS_ERR(gpiod)) { 1305 ret = PTR_ERR(gpiod); 1306 if (ret != -EPROBE_DEFER) 1307 dev_err(dev, "Failed to get reset GPIO\n"); 1308 goto err_link; 1309 } 1310 1311 ret = ks_pcie_enable_phy(ks_pcie); 1312 if (ret) { 1313 dev_err(dev, "failed to enable phy\n"); 1314 goto err_link; 1315 } 1316 1317 platform_set_drvdata(pdev, ks_pcie); 1318 pm_runtime_enable(dev); 1319 ret = pm_runtime_get_sync(dev); 1320 if (ret < 0) { 1321 dev_err(dev, "pm_runtime_get_sync failed\n"); 1322 goto err_get_sync; 1323 } 1324 1325 if (pci->version >= 0x480A) { 1326 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); 1327 atu_base = devm_ioremap_resource(dev, res); 1328 if (IS_ERR(atu_base)) { 1329 ret = PTR_ERR(atu_base); 1330 goto err_get_sync; 1331 } 1332 1333 pci->atu_base = atu_base; 1334 1335 ret = ks_pcie_am654_set_mode(dev, mode); 1336 if (ret < 0) 1337 goto err_get_sync; 1338 } else { 1339 ret = ks_pcie_set_mode(dev); 1340 if (ret < 0) 1341 goto err_get_sync; 1342 } 1343 1344 link_speed = of_pci_get_max_link_speed(np); 1345 if (link_speed < 0) 1346 link_speed = 2; 1347 1348 ks_pcie_set_link_speed(pci, link_speed); 1349 1350 switch (mode) { 1351 case DW_PCIE_RC_TYPE: 1352 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1353 ret = -ENODEV; 1354 goto err_get_sync; 1355 } 1356 1357 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1358 if (ret < 0) { 1359 dev_err(dev, "unable to read *num-viewport* property\n"); 1360 goto err_get_sync; 1361 } 1362 1363 /* 1364 * "Power Sequencing and Reset Signal Timings" table in 1365 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1366 * indicates PERST# should be deasserted after minimum of 100us 1367 * once REFCLK is stable. The REFCLK to the connector in RC 1368 * mode is selected while enabling the PHY. So deassert PERST# 1369 * after 100 us. 1370 */ 1371 if (gpiod) { 1372 usleep_range(100, 200); 1373 gpiod_set_value_cansleep(gpiod, 1); 1374 } 1375 1376 ks_pcie->num_viewport = num_viewport; 1377 pci->pp.ops = host_ops; 1378 ret = ks_pcie_add_pcie_port(ks_pcie, pdev); 1379 if (ret < 0) 1380 goto err_get_sync; 1381 break; 1382 case DW_PCIE_EP_TYPE: 1383 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1384 ret = -ENODEV; 1385 goto err_get_sync; 1386 } 1387 1388 pci->ep.ops = ep_ops; 1389 ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); 1390 if (ret < 0) 1391 goto err_get_sync; 1392 break; 1393 default: 1394 dev_err(dev, "INVALID device type %d\n", mode); 1395 } 1396 1397 ks_pcie_enable_error_irq(ks_pcie); 1398 1399 return 0; 1400 1401 err_get_sync: 1402 pm_runtime_put(dev); 1403 pm_runtime_disable(dev); 1404 ks_pcie_disable_phy(ks_pcie); 1405 1406 err_link: 1407 while (--i >= 0 && link[i]) 1408 device_link_del(link[i]); 1409 1410 return ret; 1411 } 1412 1413 static int __exit ks_pcie_remove(struct platform_device *pdev) 1414 { 1415 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1416 struct device_link **link = ks_pcie->link; 1417 int num_lanes = ks_pcie->num_lanes; 1418 struct device *dev = &pdev->dev; 1419 1420 pm_runtime_put(dev); 1421 pm_runtime_disable(dev); 1422 ks_pcie_disable_phy(ks_pcie); 1423 while (num_lanes--) 1424 device_link_del(link[num_lanes]); 1425 1426 return 0; 1427 } 1428 1429 static struct platform_driver ks_pcie_driver __refdata = { 1430 .probe = ks_pcie_probe, 1431 .remove = __exit_p(ks_pcie_remove), 1432 .driver = { 1433 .name = "keystone-pcie", 1434 .of_match_table = of_match_ptr(ks_pcie_of_match), 1435 }, 1436 }; 1437 builtin_platform_driver(ks_pcie_driver); 1438