1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/msi.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/phy/phy.h> 25 #include <linux/platform_device.h> 26 #include <linux/regmap.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 30 #include "../../pci.h" 31 #include "pcie-designware.h" 32 33 #define PCIE_VENDORID_MASK 0xffff 34 #define PCIE_DEVICEID_SHIFT 16 35 36 /* Application registers */ 37 #define PID 0x000 38 #define RTL GENMASK(15, 11) 39 #define RTL_SHIFT 11 40 #define AM6_PCI_PG1_RTL_VER 0x15 41 42 #define CMD_STATUS 0x004 43 #define LTSSM_EN_VAL BIT(0) 44 #define OB_XLAT_EN_VAL BIT(1) 45 #define DBI_CS2 BIT(5) 46 47 #define CFG_SETUP 0x008 48 #define CFG_BUS(x) (((x) & 0xff) << 16) 49 #define CFG_DEVICE(x) (((x) & 0x1f) << 8) 50 #define CFG_FUNC(x) ((x) & 0x7) 51 #define CFG_TYPE1 BIT(24) 52 53 #define OB_SIZE 0x030 54 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 55 #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 56 #define OB_ENABLEN BIT(0) 57 #define OB_WIN_SIZE 8 /* 8MB */ 58 59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 61 #define PCIE_EP_IRQ_SET 0x64 62 #define PCIE_EP_IRQ_CLR 0x68 63 #define INT_ENABLE BIT(0) 64 65 /* IRQ register defines */ 66 #define IRQ_EOI 0x050 67 68 #define MSI_IRQ 0x054 69 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 70 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 71 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 72 #define MSI_IRQ_OFFSET 4 73 74 #define IRQ_STATUS(n) (0x184 + ((n) << 4)) 75 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 76 #define INTx_EN BIT(0) 77 78 #define ERR_IRQ_STATUS 0x1c4 79 #define ERR_IRQ_ENABLE_SET 0x1c8 80 #define ERR_AER BIT(5) /* ECRC error */ 81 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 82 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 83 #define ERR_CORR BIT(3) /* Correctable error */ 84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */ 85 #define ERR_FATAL BIT(1) /* Fatal error */ 86 #define ERR_SYS BIT(0) /* System error */ 87 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 88 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 89 90 /* PCIE controller device IDs */ 91 #define PCIE_RC_K2HK 0xb008 92 #define PCIE_RC_K2E 0xb009 93 #define PCIE_RC_K2L 0xb00a 94 #define PCIE_RC_K2G 0xb00b 95 96 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 97 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 98 99 #define EP 0x0 100 #define LEG_EP 0x1 101 #define RC 0x2 102 103 #define KS_PCIE_SYSCLOCKOUTEN BIT(0) 104 105 #define AM654_PCIE_DEV_TYPE_MASK 0x3 106 #define AM654_WIN_SIZE SZ_64K 107 108 #define APP_ADDR_SPACE_0 (16 * SZ_1K) 109 110 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 111 112 #define PCI_DEVICE_ID_TI_AM654X 0xb00c 113 114 struct ks_pcie_of_data { 115 enum dw_pcie_device_mode mode; 116 const struct dw_pcie_host_ops *host_ops; 117 const struct dw_pcie_ep_ops *ep_ops; 118 u32 version; 119 }; 120 121 struct keystone_pcie { 122 struct dw_pcie *pci; 123 /* PCI Device ID */ 124 u32 device_id; 125 int legacy_host_irqs[PCI_NUM_INTX]; 126 struct device_node *legacy_intc_np; 127 128 int msi_host_irq; 129 int num_lanes; 130 u32 num_viewport; 131 struct phy **phy; 132 struct device_link **link; 133 struct device_node *msi_intc_np; 134 struct irq_domain *legacy_irq_domain; 135 struct device_node *np; 136 137 /* Application register space */ 138 void __iomem *va_app_base; /* DT 1st resource */ 139 struct resource app; 140 bool is_am6; 141 }; 142 143 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 144 { 145 return readl(ks_pcie->va_app_base + offset); 146 } 147 148 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 149 u32 val) 150 { 151 writel(val, ks_pcie->va_app_base + offset); 152 } 153 154 static void ks_pcie_msi_irq_ack(struct irq_data *data) 155 { 156 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 157 struct keystone_pcie *ks_pcie; 158 u32 irq = data->hwirq; 159 struct dw_pcie *pci; 160 u32 reg_offset; 161 u32 bit_pos; 162 163 pci = to_dw_pcie_from_pp(pp); 164 ks_pcie = to_keystone_pcie(pci); 165 166 reg_offset = irq % 8; 167 bit_pos = irq >> 3; 168 169 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 170 BIT(bit_pos)); 171 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 172 } 173 174 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 175 { 176 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 177 struct keystone_pcie *ks_pcie; 178 struct dw_pcie *pci; 179 u64 msi_target; 180 181 pci = to_dw_pcie_from_pp(pp); 182 ks_pcie = to_keystone_pcie(pci); 183 184 msi_target = ks_pcie->app.start + MSI_IRQ; 185 msg->address_lo = lower_32_bits(msi_target); 186 msg->address_hi = upper_32_bits(msi_target); 187 msg->data = data->hwirq; 188 189 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 190 (int)data->hwirq, msg->address_hi, msg->address_lo); 191 } 192 193 static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 194 const struct cpumask *mask, bool force) 195 { 196 return -EINVAL; 197 } 198 199 static void ks_pcie_msi_mask(struct irq_data *data) 200 { 201 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 202 struct keystone_pcie *ks_pcie; 203 u32 irq = data->hwirq; 204 struct dw_pcie *pci; 205 unsigned long flags; 206 u32 reg_offset; 207 u32 bit_pos; 208 209 raw_spin_lock_irqsave(&pp->lock, flags); 210 211 pci = to_dw_pcie_from_pp(pp); 212 ks_pcie = to_keystone_pcie(pci); 213 214 reg_offset = irq % 8; 215 bit_pos = irq >> 3; 216 217 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 218 BIT(bit_pos)); 219 220 raw_spin_unlock_irqrestore(&pp->lock, flags); 221 } 222 223 static void ks_pcie_msi_unmask(struct irq_data *data) 224 { 225 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 226 struct keystone_pcie *ks_pcie; 227 u32 irq = data->hwirq; 228 struct dw_pcie *pci; 229 unsigned long flags; 230 u32 reg_offset; 231 u32 bit_pos; 232 233 raw_spin_lock_irqsave(&pp->lock, flags); 234 235 pci = to_dw_pcie_from_pp(pp); 236 ks_pcie = to_keystone_pcie(pci); 237 238 reg_offset = irq % 8; 239 bit_pos = irq >> 3; 240 241 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 242 BIT(bit_pos)); 243 244 raw_spin_unlock_irqrestore(&pp->lock, flags); 245 } 246 247 static struct irq_chip ks_pcie_msi_irq_chip = { 248 .name = "KEYSTONE-PCI-MSI", 249 .irq_ack = ks_pcie_msi_irq_ack, 250 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 251 .irq_set_affinity = ks_pcie_msi_set_affinity, 252 .irq_mask = ks_pcie_msi_mask, 253 .irq_unmask = ks_pcie_msi_unmask, 254 }; 255 256 /** 257 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers 258 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 259 * PCIe host controller driver information. 260 * 261 * Since modification of dbi_cs2 involves different clock domain, read the 262 * status back to ensure the transition is complete. 263 */ 264 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 265 { 266 u32 val; 267 268 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 269 val |= DBI_CS2; 270 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 271 272 do { 273 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 274 } while (!(val & DBI_CS2)); 275 } 276 277 /** 278 * ks_pcie_clear_dbi_mode() - Disable DBI mode 279 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 280 * PCIe host controller driver information. 281 * 282 * Since modification of dbi_cs2 involves different clock domain, read the 283 * status back to ensure the transition is complete. 284 */ 285 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 286 { 287 u32 val; 288 289 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 290 val &= ~DBI_CS2; 291 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 292 293 do { 294 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 295 } while (val & DBI_CS2); 296 } 297 298 static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) 299 { 300 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 301 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 302 303 /* Configure and set up BAR0 */ 304 ks_pcie_set_dbi_mode(ks_pcie); 305 306 /* Enable BAR0 */ 307 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 308 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 309 310 ks_pcie_clear_dbi_mode(ks_pcie); 311 312 /* 313 * For BAR0, just setting bus address for inbound writes (MSI) should 314 * be sufficient. Use physical address to avoid any conflicts. 315 */ 316 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 317 318 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 319 return dw_pcie_allocate_domains(pp); 320 } 321 322 static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, 323 int offset) 324 { 325 struct dw_pcie *pci = ks_pcie->pci; 326 struct device *dev = pci->dev; 327 u32 pending; 328 329 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 330 331 if (BIT(0) & pending) { 332 dev_dbg(dev, ": irq: irq_offset %d", offset); 333 generic_handle_domain_irq(ks_pcie->legacy_irq_domain, offset); 334 } 335 336 /* EOI the INTx interrupt */ 337 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 338 } 339 340 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 341 { 342 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 343 } 344 345 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 346 { 347 u32 reg; 348 struct device *dev = ks_pcie->pci->dev; 349 350 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 351 if (!reg) 352 return IRQ_NONE; 353 354 if (reg & ERR_SYS) 355 dev_err(dev, "System Error\n"); 356 357 if (reg & ERR_FATAL) 358 dev_err(dev, "Fatal Error\n"); 359 360 if (reg & ERR_NONFATAL) 361 dev_dbg(dev, "Non Fatal Error\n"); 362 363 if (reg & ERR_CORR) 364 dev_dbg(dev, "Correctable Error\n"); 365 366 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 367 dev_err(dev, "AXI tag lookup fatal Error\n"); 368 369 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 370 dev_err(dev, "ECRC Error\n"); 371 372 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 373 374 return IRQ_HANDLED; 375 } 376 377 static void ks_pcie_ack_legacy_irq(struct irq_data *d) 378 { 379 } 380 381 static void ks_pcie_mask_legacy_irq(struct irq_data *d) 382 { 383 } 384 385 static void ks_pcie_unmask_legacy_irq(struct irq_data *d) 386 { 387 } 388 389 static struct irq_chip ks_pcie_legacy_irq_chip = { 390 .name = "Keystone-PCI-Legacy-IRQ", 391 .irq_ack = ks_pcie_ack_legacy_irq, 392 .irq_mask = ks_pcie_mask_legacy_irq, 393 .irq_unmask = ks_pcie_unmask_legacy_irq, 394 }; 395 396 static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, 397 unsigned int irq, 398 irq_hw_number_t hw_irq) 399 { 400 irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip, 401 handle_level_irq); 402 irq_set_chip_data(irq, d->host_data); 403 404 return 0; 405 } 406 407 static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = { 408 .map = ks_pcie_init_legacy_irq_map, 409 .xlate = irq_domain_xlate_onetwocell, 410 }; 411 412 static int ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 413 { 414 u32 val; 415 u32 num_viewport = ks_pcie->num_viewport; 416 struct dw_pcie *pci = ks_pcie->pci; 417 struct dw_pcie_rp *pp = &pci->pp; 418 struct resource_entry *entry; 419 struct resource *mem; 420 u64 start, end; 421 int i; 422 423 entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); 424 if (!entry) 425 return -ENODEV; 426 427 mem = entry->res; 428 start = mem->start; 429 end = mem->end; 430 431 /* Disable BARs for inbound access */ 432 ks_pcie_set_dbi_mode(ks_pcie); 433 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 434 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 435 ks_pcie_clear_dbi_mode(ks_pcie); 436 437 if (ks_pcie->is_am6) 438 return 0; 439 440 val = ilog2(OB_WIN_SIZE); 441 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 442 443 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 444 for (i = 0; i < num_viewport && (start < end); i++) { 445 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 446 lower_32_bits(start) | OB_ENABLEN); 447 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 448 upper_32_bits(start)); 449 start += OB_WIN_SIZE * SZ_1M; 450 } 451 452 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 453 val |= OB_XLAT_EN_VAL; 454 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 455 456 return 0; 457 } 458 459 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 460 unsigned int devfn, int where) 461 { 462 struct dw_pcie_rp *pp = bus->sysdata; 463 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 464 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 465 u32 reg; 466 467 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 468 CFG_FUNC(PCI_FUNC(devfn)); 469 if (!pci_is_root_bus(bus->parent)) 470 reg |= CFG_TYPE1; 471 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 472 473 return pp->va_cfg0_base + where; 474 } 475 476 static struct pci_ops ks_child_pcie_ops = { 477 .map_bus = ks_pcie_other_map_bus, 478 .read = pci_generic_config_read, 479 .write = pci_generic_config_write, 480 }; 481 482 static struct pci_ops ks_pcie_ops = { 483 .map_bus = dw_pcie_own_conf_map_bus, 484 .read = pci_generic_config_read, 485 .write = pci_generic_config_write, 486 }; 487 488 /** 489 * ks_pcie_link_up() - Check if link up 490 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host 491 * controller driver information. 492 */ 493 static int ks_pcie_link_up(struct dw_pcie *pci) 494 { 495 u32 val; 496 497 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 498 val &= PORT_LOGIC_LTSSM_STATE_MASK; 499 return (val == PORT_LOGIC_LTSSM_STATE_L0); 500 } 501 502 static void ks_pcie_stop_link(struct dw_pcie *pci) 503 { 504 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 505 u32 val; 506 507 /* Disable Link training */ 508 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 509 val &= ~LTSSM_EN_VAL; 510 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 511 } 512 513 static int ks_pcie_start_link(struct dw_pcie *pci) 514 { 515 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 516 u32 val; 517 518 /* Initiate Link Training */ 519 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 520 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 521 522 return 0; 523 } 524 525 static void ks_pcie_quirk(struct pci_dev *dev) 526 { 527 struct pci_bus *bus = dev->bus; 528 struct keystone_pcie *ks_pcie; 529 struct device *bridge_dev; 530 struct pci_dev *bridge; 531 u32 val; 532 533 static const struct pci_device_id rc_pci_devids[] = { 534 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 535 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 536 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 537 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 538 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 539 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 540 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 541 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 542 { 0, }, 543 }; 544 static const struct pci_device_id am6_pci_devids[] = { 545 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), 546 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 547 { 0, }, 548 }; 549 550 if (pci_is_root_bus(bus)) 551 bridge = dev; 552 553 /* look for the host bridge */ 554 while (!pci_is_root_bus(bus)) { 555 bridge = bus->self; 556 bus = bus->parent; 557 } 558 559 if (!bridge) 560 return; 561 562 /* 563 * Keystone PCI controller has a h/w limitation of 564 * 256 bytes maximum read request size. It can't handle 565 * anything higher than this. So force this limit on 566 * all downstream devices. 567 */ 568 if (pci_match_id(rc_pci_devids, bridge)) { 569 if (pcie_get_readrq(dev) > 256) { 570 dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); 571 pcie_set_readrq(dev, 256); 572 } 573 } 574 575 /* 576 * Memory transactions fail with PCI controller in AM654 PG1.0 577 * when MRRS is set to more than 128 bytes. Force the MRRS to 578 * 128 bytes in all downstream devices. 579 */ 580 if (pci_match_id(am6_pci_devids, bridge)) { 581 bridge_dev = pci_get_host_bridge_device(dev); 582 if (!bridge_dev || !bridge_dev->parent) 583 return; 584 585 ks_pcie = dev_get_drvdata(bridge_dev->parent); 586 if (!ks_pcie) 587 return; 588 589 val = ks_pcie_app_readl(ks_pcie, PID); 590 val &= RTL; 591 val >>= RTL_SHIFT; 592 if (val != AM6_PCI_PG1_RTL_VER) 593 return; 594 595 if (pcie_get_readrq(dev) > 128) { 596 dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); 597 pcie_set_readrq(dev, 128); 598 } 599 } 600 } 601 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 602 603 static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 604 { 605 unsigned int irq = desc->irq_data.hwirq; 606 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 607 u32 offset = irq - ks_pcie->msi_host_irq; 608 struct dw_pcie *pci = ks_pcie->pci; 609 struct dw_pcie_rp *pp = &pci->pp; 610 struct device *dev = pci->dev; 611 struct irq_chip *chip = irq_desc_get_chip(desc); 612 u32 vector, reg, pos; 613 614 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 615 616 /* 617 * The chained irq handler installation would have replaced normal 618 * interrupt driver handler so we need to take care of mask/unmask and 619 * ack operation. 620 */ 621 chained_irq_enter(chip, desc); 622 623 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 624 /* 625 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 626 * shows 1, 9, 17, 25 and so forth 627 */ 628 for (pos = 0; pos < 4; pos++) { 629 if (!(reg & BIT(pos))) 630 continue; 631 632 vector = offset + (pos << 3); 633 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector); 634 generic_handle_domain_irq(pp->irq_domain, vector); 635 } 636 637 chained_irq_exit(chip, desc); 638 } 639 640 /** 641 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt 642 * @desc: Pointer to irq descriptor 643 * 644 * Traverse through pending legacy interrupts and invoke handler for each. Also 645 * takes care of interrupt controller level mask/ack operation. 646 */ 647 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) 648 { 649 unsigned int irq = irq_desc_get_irq(desc); 650 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 651 struct dw_pcie *pci = ks_pcie->pci; 652 struct device *dev = pci->dev; 653 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; 654 struct irq_chip *chip = irq_desc_get_chip(desc); 655 656 dev_dbg(dev, ": Handling legacy irq %d\n", irq); 657 658 /* 659 * The chained irq handler installation would have replaced normal 660 * interrupt driver handler so we need to take care of mask/unmask and 661 * ack operation. 662 */ 663 chained_irq_enter(chip, desc); 664 ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); 665 chained_irq_exit(chip, desc); 666 } 667 668 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 669 { 670 struct device *dev = ks_pcie->pci->dev; 671 struct device_node *np = ks_pcie->np; 672 struct device_node *intc_np; 673 struct irq_data *irq_data; 674 int irq_count, irq, ret, i; 675 676 if (!IS_ENABLED(CONFIG_PCI_MSI)) 677 return 0; 678 679 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 680 if (!intc_np) { 681 if (ks_pcie->is_am6) 682 return 0; 683 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 684 return -EINVAL; 685 } 686 687 irq_count = of_irq_count(intc_np); 688 if (!irq_count) { 689 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 690 ret = -EINVAL; 691 goto err; 692 } 693 694 for (i = 0; i < irq_count; i++) { 695 irq = irq_of_parse_and_map(intc_np, i); 696 if (!irq) { 697 ret = -EINVAL; 698 goto err; 699 } 700 701 if (!ks_pcie->msi_host_irq) { 702 irq_data = irq_get_irq_data(irq); 703 if (!irq_data) { 704 ret = -EINVAL; 705 goto err; 706 } 707 ks_pcie->msi_host_irq = irq_data->hwirq; 708 } 709 710 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 711 ks_pcie); 712 } 713 714 of_node_put(intc_np); 715 return 0; 716 717 err: 718 of_node_put(intc_np); 719 return ret; 720 } 721 722 static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) 723 { 724 struct device *dev = ks_pcie->pci->dev; 725 struct irq_domain *legacy_irq_domain; 726 struct device_node *np = ks_pcie->np; 727 struct device_node *intc_np; 728 int irq_count, irq, ret = 0, i; 729 730 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 731 if (!intc_np) { 732 /* 733 * Since legacy interrupts are modeled as edge-interrupts in 734 * AM6, keep it disabled for now. 735 */ 736 if (ks_pcie->is_am6) 737 return 0; 738 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 739 return -EINVAL; 740 } 741 742 irq_count = of_irq_count(intc_np); 743 if (!irq_count) { 744 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 745 ret = -EINVAL; 746 goto err; 747 } 748 749 for (i = 0; i < irq_count; i++) { 750 irq = irq_of_parse_and_map(intc_np, i); 751 if (!irq) { 752 ret = -EINVAL; 753 goto err; 754 } 755 ks_pcie->legacy_host_irqs[i] = irq; 756 757 irq_set_chained_handler_and_data(irq, 758 ks_pcie_legacy_irq_handler, 759 ks_pcie); 760 } 761 762 legacy_irq_domain = 763 irq_domain_add_linear(intc_np, PCI_NUM_INTX, 764 &ks_pcie_legacy_irq_domain_ops, NULL); 765 if (!legacy_irq_domain) { 766 dev_err(dev, "Failed to add irq domain for legacy irqs\n"); 767 ret = -EINVAL; 768 goto err; 769 } 770 ks_pcie->legacy_irq_domain = legacy_irq_domain; 771 772 for (i = 0; i < PCI_NUM_INTX; i++) 773 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 774 775 err: 776 of_node_put(intc_np); 777 return ret; 778 } 779 780 #ifdef CONFIG_ARM 781 /* 782 * When a PCI device does not exist during config cycles, keystone host 783 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). 784 * This handler always returns 0 for this kind of fault. 785 */ 786 static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 787 struct pt_regs *regs) 788 { 789 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 790 791 if ((instr & 0x0e100090) == 0x00100090) { 792 int reg = (instr >> 12) & 15; 793 794 regs->uregs[reg] = -1; 795 regs->ARM_pc += 4; 796 } 797 798 return 0; 799 } 800 #endif 801 802 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 803 { 804 int ret; 805 unsigned int id; 806 struct regmap *devctrl_regs; 807 struct dw_pcie *pci = ks_pcie->pci; 808 struct device *dev = pci->dev; 809 struct device_node *np = dev->of_node; 810 struct of_phandle_args args; 811 unsigned int offset = 0; 812 813 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 814 if (IS_ERR(devctrl_regs)) 815 return PTR_ERR(devctrl_regs); 816 817 /* Do not error out to maintain old DT compatibility */ 818 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); 819 if (!ret) 820 offset = args.args[0]; 821 822 ret = regmap_read(devctrl_regs, offset, &id); 823 if (ret) 824 return ret; 825 826 dw_pcie_dbi_ro_wr_en(pci); 827 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 828 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 829 dw_pcie_dbi_ro_wr_dis(pci); 830 831 return 0; 832 } 833 834 static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) 835 { 836 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 837 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 838 int ret; 839 840 pp->bridge->ops = &ks_pcie_ops; 841 if (!ks_pcie->is_am6) 842 pp->bridge->child_ops = &ks_child_pcie_ops; 843 844 ret = ks_pcie_config_legacy_irq(ks_pcie); 845 if (ret) 846 return ret; 847 848 ret = ks_pcie_config_msi_irq(ks_pcie); 849 if (ret) 850 return ret; 851 852 ks_pcie_stop_link(pci); 853 ret = ks_pcie_setup_rc_app_regs(ks_pcie); 854 if (ret) 855 return ret; 856 857 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 858 pci->dbi_base + PCI_IO_BASE); 859 860 ret = ks_pcie_init_id(ks_pcie); 861 if (ret < 0) 862 return ret; 863 864 #ifdef CONFIG_ARM 865 /* 866 * PCIe access errors that result into OCP errors are caught by ARM as 867 * "External aborts" 868 */ 869 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 870 "Asynchronous external abort"); 871 #endif 872 873 return 0; 874 } 875 876 static const struct dw_pcie_host_ops ks_pcie_host_ops = { 877 .host_init = ks_pcie_host_init, 878 .msi_host_init = ks_pcie_msi_host_init, 879 }; 880 881 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 882 .host_init = ks_pcie_host_init, 883 }; 884 885 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 886 { 887 struct keystone_pcie *ks_pcie = priv; 888 889 return ks_pcie_handle_error_irq(ks_pcie); 890 } 891 892 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 893 u32 reg, size_t size, u32 val) 894 { 895 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 896 897 ks_pcie_set_dbi_mode(ks_pcie); 898 dw_pcie_write(base + reg, size, val); 899 ks_pcie_clear_dbi_mode(ks_pcie); 900 } 901 902 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 903 .start_link = ks_pcie_start_link, 904 .stop_link = ks_pcie_stop_link, 905 .link_up = ks_pcie_link_up, 906 .write_dbi2 = ks_pcie_am654_write_dbi2, 907 }; 908 909 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 910 { 911 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 912 int flags; 913 914 ep->page_size = AM654_WIN_SIZE; 915 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 916 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 917 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 918 } 919 920 static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) 921 { 922 struct dw_pcie *pci = ks_pcie->pci; 923 u8 int_pin; 924 925 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 926 if (int_pin == 0 || int_pin > 4) 927 return; 928 929 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 930 INT_ENABLE); 931 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 932 mdelay(1); 933 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 934 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 935 INT_ENABLE); 936 } 937 938 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 939 enum pci_epc_irq_type type, 940 u16 interrupt_num) 941 { 942 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 943 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 944 945 switch (type) { 946 case PCI_EPC_IRQ_LEGACY: 947 ks_pcie_am654_raise_legacy_irq(ks_pcie); 948 break; 949 case PCI_EPC_IRQ_MSI: 950 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 951 break; 952 case PCI_EPC_IRQ_MSIX: 953 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 954 break; 955 default: 956 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 957 return -EINVAL; 958 } 959 960 return 0; 961 } 962 963 static const struct pci_epc_features ks_pcie_am654_epc_features = { 964 .linkup_notifier = false, 965 .msi_capable = true, 966 .msix_capable = true, 967 .reserved_bar = 1 << BAR_0 | 1 << BAR_1, 968 .bar_fixed_64bit = 1 << BAR_0, 969 .bar_fixed_size[2] = SZ_1M, 970 .bar_fixed_size[3] = SZ_64K, 971 .bar_fixed_size[4] = 256, 972 .bar_fixed_size[5] = SZ_1M, 973 .align = SZ_1M, 974 }; 975 976 static const struct pci_epc_features* 977 ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 978 { 979 return &ks_pcie_am654_epc_features; 980 } 981 982 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 983 .ep_init = ks_pcie_am654_ep_init, 984 .raise_irq = ks_pcie_am654_raise_irq, 985 .get_features = &ks_pcie_am654_get_features, 986 }; 987 988 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 989 { 990 int num_lanes = ks_pcie->num_lanes; 991 992 while (num_lanes--) { 993 phy_power_off(ks_pcie->phy[num_lanes]); 994 phy_exit(ks_pcie->phy[num_lanes]); 995 } 996 } 997 998 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 999 { 1000 int i; 1001 int ret; 1002 int num_lanes = ks_pcie->num_lanes; 1003 1004 for (i = 0; i < num_lanes; i++) { 1005 ret = phy_reset(ks_pcie->phy[i]); 1006 if (ret < 0) 1007 goto err_phy; 1008 1009 ret = phy_init(ks_pcie->phy[i]); 1010 if (ret < 0) 1011 goto err_phy; 1012 1013 ret = phy_power_on(ks_pcie->phy[i]); 1014 if (ret < 0) { 1015 phy_exit(ks_pcie->phy[i]); 1016 goto err_phy; 1017 } 1018 } 1019 1020 return 0; 1021 1022 err_phy: 1023 while (--i >= 0) { 1024 phy_power_off(ks_pcie->phy[i]); 1025 phy_exit(ks_pcie->phy[i]); 1026 } 1027 1028 return ret; 1029 } 1030 1031 static int ks_pcie_set_mode(struct device *dev) 1032 { 1033 struct device_node *np = dev->of_node; 1034 struct of_phandle_args args; 1035 unsigned int offset = 0; 1036 struct regmap *syscon; 1037 u32 val; 1038 u32 mask; 1039 int ret = 0; 1040 1041 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1042 if (IS_ERR(syscon)) 1043 return 0; 1044 1045 /* Do not error out to maintain old DT compatibility */ 1046 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1047 if (!ret) 1048 offset = args.args[0]; 1049 1050 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1051 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1052 1053 ret = regmap_update_bits(syscon, offset, mask, val); 1054 if (ret) { 1055 dev_err(dev, "failed to set pcie mode\n"); 1056 return ret; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int ks_pcie_am654_set_mode(struct device *dev, 1063 enum dw_pcie_device_mode mode) 1064 { 1065 struct device_node *np = dev->of_node; 1066 struct of_phandle_args args; 1067 unsigned int offset = 0; 1068 struct regmap *syscon; 1069 u32 val; 1070 u32 mask; 1071 int ret = 0; 1072 1073 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1074 if (IS_ERR(syscon)) 1075 return 0; 1076 1077 /* Do not error out to maintain old DT compatibility */ 1078 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1079 if (!ret) 1080 offset = args.args[0]; 1081 1082 mask = AM654_PCIE_DEV_TYPE_MASK; 1083 1084 switch (mode) { 1085 case DW_PCIE_RC_TYPE: 1086 val = RC; 1087 break; 1088 case DW_PCIE_EP_TYPE: 1089 val = EP; 1090 break; 1091 default: 1092 dev_err(dev, "INVALID device type %d\n", mode); 1093 return -EINVAL; 1094 } 1095 1096 ret = regmap_update_bits(syscon, offset, mask, val); 1097 if (ret) { 1098 dev_err(dev, "failed to set pcie mode\n"); 1099 return ret; 1100 } 1101 1102 return 0; 1103 } 1104 1105 static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1106 .host_ops = &ks_pcie_host_ops, 1107 .version = DW_PCIE_VER_365A, 1108 }; 1109 1110 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1111 .host_ops = &ks_pcie_am654_host_ops, 1112 .mode = DW_PCIE_RC_TYPE, 1113 .version = DW_PCIE_VER_490A, 1114 }; 1115 1116 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1117 .ep_ops = &ks_pcie_am654_ep_ops, 1118 .mode = DW_PCIE_EP_TYPE, 1119 .version = DW_PCIE_VER_490A, 1120 }; 1121 1122 static const struct of_device_id ks_pcie_of_match[] = { 1123 { 1124 .type = "pci", 1125 .data = &ks_pcie_rc_of_data, 1126 .compatible = "ti,keystone-pcie", 1127 }, 1128 { 1129 .data = &ks_pcie_am654_rc_of_data, 1130 .compatible = "ti,am654-pcie-rc", 1131 }, 1132 { 1133 .data = &ks_pcie_am654_ep_of_data, 1134 .compatible = "ti,am654-pcie-ep", 1135 }, 1136 { }, 1137 }; 1138 1139 static int ks_pcie_probe(struct platform_device *pdev) 1140 { 1141 const struct dw_pcie_host_ops *host_ops; 1142 const struct dw_pcie_ep_ops *ep_ops; 1143 struct device *dev = &pdev->dev; 1144 struct device_node *np = dev->of_node; 1145 const struct ks_pcie_of_data *data; 1146 enum dw_pcie_device_mode mode; 1147 struct dw_pcie *pci; 1148 struct keystone_pcie *ks_pcie; 1149 struct device_link **link; 1150 struct gpio_desc *gpiod; 1151 struct resource *res; 1152 void __iomem *base; 1153 u32 num_viewport; 1154 struct phy **phy; 1155 u32 num_lanes; 1156 char name[10]; 1157 u32 version; 1158 int ret; 1159 int irq; 1160 int i; 1161 1162 data = of_device_get_match_data(dev); 1163 if (!data) 1164 return -EINVAL; 1165 1166 version = data->version; 1167 host_ops = data->host_ops; 1168 ep_ops = data->ep_ops; 1169 mode = data->mode; 1170 1171 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1172 if (!ks_pcie) 1173 return -ENOMEM; 1174 1175 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1176 if (!pci) 1177 return -ENOMEM; 1178 1179 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1180 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1181 if (IS_ERR(ks_pcie->va_app_base)) 1182 return PTR_ERR(ks_pcie->va_app_base); 1183 1184 ks_pcie->app = *res; 1185 1186 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1187 base = devm_pci_remap_cfg_resource(dev, res); 1188 if (IS_ERR(base)) 1189 return PTR_ERR(base); 1190 1191 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1192 ks_pcie->is_am6 = true; 1193 1194 pci->dbi_base = base; 1195 pci->dbi_base2 = base; 1196 pci->dev = dev; 1197 pci->ops = &ks_pcie_dw_pcie_ops; 1198 pci->version = version; 1199 1200 irq = platform_get_irq(pdev, 0); 1201 if (irq < 0) 1202 return irq; 1203 1204 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1205 "ks-pcie-error-irq", ks_pcie); 1206 if (ret < 0) { 1207 dev_err(dev, "failed to request error IRQ %d\n", 1208 irq); 1209 return ret; 1210 } 1211 1212 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1213 if (ret) 1214 num_lanes = 1; 1215 1216 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1217 if (!phy) 1218 return -ENOMEM; 1219 1220 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1221 if (!link) 1222 return -ENOMEM; 1223 1224 for (i = 0; i < num_lanes; i++) { 1225 snprintf(name, sizeof(name), "pcie-phy%d", i); 1226 phy[i] = devm_phy_optional_get(dev, name); 1227 if (IS_ERR(phy[i])) { 1228 ret = PTR_ERR(phy[i]); 1229 goto err_link; 1230 } 1231 1232 if (!phy[i]) 1233 continue; 1234 1235 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1236 if (!link[i]) { 1237 ret = -EINVAL; 1238 goto err_link; 1239 } 1240 } 1241 1242 ks_pcie->np = np; 1243 ks_pcie->pci = pci; 1244 ks_pcie->link = link; 1245 ks_pcie->num_lanes = num_lanes; 1246 ks_pcie->phy = phy; 1247 1248 gpiod = devm_gpiod_get_optional(dev, "reset", 1249 GPIOD_OUT_LOW); 1250 if (IS_ERR(gpiod)) { 1251 ret = PTR_ERR(gpiod); 1252 if (ret != -EPROBE_DEFER) 1253 dev_err(dev, "Failed to get reset GPIO\n"); 1254 goto err_link; 1255 } 1256 1257 /* Obtain references to the PHYs */ 1258 for (i = 0; i < num_lanes; i++) 1259 phy_pm_runtime_get_sync(ks_pcie->phy[i]); 1260 1261 ret = ks_pcie_enable_phy(ks_pcie); 1262 1263 /* Release references to the PHYs */ 1264 for (i = 0; i < num_lanes; i++) 1265 phy_pm_runtime_put_sync(ks_pcie->phy[i]); 1266 1267 if (ret) { 1268 dev_err(dev, "failed to enable phy\n"); 1269 goto err_link; 1270 } 1271 1272 platform_set_drvdata(pdev, ks_pcie); 1273 pm_runtime_enable(dev); 1274 ret = pm_runtime_get_sync(dev); 1275 if (ret < 0) { 1276 dev_err(dev, "pm_runtime_get_sync failed\n"); 1277 goto err_get_sync; 1278 } 1279 1280 if (dw_pcie_ver_is_ge(pci, 480A)) 1281 ret = ks_pcie_am654_set_mode(dev, mode); 1282 else 1283 ret = ks_pcie_set_mode(dev); 1284 if (ret < 0) 1285 goto err_get_sync; 1286 1287 switch (mode) { 1288 case DW_PCIE_RC_TYPE: 1289 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1290 ret = -ENODEV; 1291 goto err_get_sync; 1292 } 1293 1294 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1295 if (ret < 0) { 1296 dev_err(dev, "unable to read *num-viewport* property\n"); 1297 goto err_get_sync; 1298 } 1299 1300 /* 1301 * "Power Sequencing and Reset Signal Timings" table in 1302 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1303 * indicates PERST# should be deasserted after minimum of 100us 1304 * once REFCLK is stable. The REFCLK to the connector in RC 1305 * mode is selected while enabling the PHY. So deassert PERST# 1306 * after 100 us. 1307 */ 1308 if (gpiod) { 1309 usleep_range(100, 200); 1310 gpiod_set_value_cansleep(gpiod, 1); 1311 } 1312 1313 ks_pcie->num_viewport = num_viewport; 1314 pci->pp.ops = host_ops; 1315 ret = dw_pcie_host_init(&pci->pp); 1316 if (ret < 0) 1317 goto err_get_sync; 1318 break; 1319 case DW_PCIE_EP_TYPE: 1320 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1321 ret = -ENODEV; 1322 goto err_get_sync; 1323 } 1324 1325 pci->ep.ops = ep_ops; 1326 ret = dw_pcie_ep_init(&pci->ep); 1327 if (ret < 0) 1328 goto err_get_sync; 1329 break; 1330 default: 1331 dev_err(dev, "INVALID device type %d\n", mode); 1332 } 1333 1334 ks_pcie_enable_error_irq(ks_pcie); 1335 1336 return 0; 1337 1338 err_get_sync: 1339 pm_runtime_put(dev); 1340 pm_runtime_disable(dev); 1341 ks_pcie_disable_phy(ks_pcie); 1342 1343 err_link: 1344 while (--i >= 0 && link[i]) 1345 device_link_del(link[i]); 1346 1347 return ret; 1348 } 1349 1350 static int ks_pcie_remove(struct platform_device *pdev) 1351 { 1352 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1353 struct device_link **link = ks_pcie->link; 1354 int num_lanes = ks_pcie->num_lanes; 1355 struct device *dev = &pdev->dev; 1356 1357 pm_runtime_put(dev); 1358 pm_runtime_disable(dev); 1359 ks_pcie_disable_phy(ks_pcie); 1360 while (num_lanes--) 1361 device_link_del(link[num_lanes]); 1362 1363 return 0; 1364 } 1365 1366 static struct platform_driver ks_pcie_driver = { 1367 .probe = ks_pcie_probe, 1368 .remove = ks_pcie_remove, 1369 .driver = { 1370 .name = "keystone-pcie", 1371 .of_match_table = ks_pcie_of_match, 1372 }, 1373 }; 1374 builtin_platform_driver(ks_pcie_driver); 1375