1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/msi.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_pci.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/regmap.h> 28 #include <linux/resource.h> 29 #include <linux/signal.h> 30 31 #include "../../pci.h" 32 #include "pcie-designware.h" 33 34 #define PCIE_VENDORID_MASK 0xffff 35 #define PCIE_DEVICEID_SHIFT 16 36 37 /* Application registers */ 38 #define CMD_STATUS 0x004 39 #define LTSSM_EN_VAL BIT(0) 40 #define OB_XLAT_EN_VAL BIT(1) 41 #define DBI_CS2 BIT(5) 42 43 #define CFG_SETUP 0x008 44 #define CFG_BUS(x) (((x) & 0xff) << 16) 45 #define CFG_DEVICE(x) (((x) & 0x1f) << 8) 46 #define CFG_FUNC(x) ((x) & 0x7) 47 #define CFG_TYPE1 BIT(24) 48 49 #define OB_SIZE 0x030 50 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 51 #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 52 #define OB_ENABLEN BIT(0) 53 #define OB_WIN_SIZE 8 /* 8MB */ 54 55 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 56 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 57 #define PCIE_EP_IRQ_SET 0x64 58 #define PCIE_EP_IRQ_CLR 0x68 59 #define INT_ENABLE BIT(0) 60 61 /* IRQ register defines */ 62 #define IRQ_EOI 0x050 63 64 #define MSI_IRQ 0x054 65 #define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 66 #define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 67 #define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 68 #define MSI_IRQ_OFFSET 4 69 70 #define IRQ_STATUS(n) (0x184 + ((n) << 4)) 71 #define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 72 #define INTx_EN BIT(0) 73 74 #define ERR_IRQ_STATUS 0x1c4 75 #define ERR_IRQ_ENABLE_SET 0x1c8 76 #define ERR_AER BIT(5) /* ECRC error */ 77 #define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 78 #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 79 #define ERR_CORR BIT(3) /* Correctable error */ 80 #define ERR_NONFATAL BIT(2) /* Non-fatal error */ 81 #define ERR_FATAL BIT(1) /* Fatal error */ 82 #define ERR_SYS BIT(0) /* System error */ 83 #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 84 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 85 86 /* PCIE controller device IDs */ 87 #define PCIE_RC_K2HK 0xb008 88 #define PCIE_RC_K2E 0xb009 89 #define PCIE_RC_K2L 0xb00a 90 #define PCIE_RC_K2G 0xb00b 91 92 #define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 93 #define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 94 95 #define EP 0x0 96 #define LEG_EP 0x1 97 #define RC 0x2 98 99 #define KS_PCIE_SYSCLOCKOUTEN BIT(0) 100 101 #define AM654_PCIE_DEV_TYPE_MASK 0x3 102 #define AM654_WIN_SIZE SZ_64K 103 104 #define APP_ADDR_SPACE_0 (16 * SZ_1K) 105 106 #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 107 108 struct ks_pcie_of_data { 109 enum dw_pcie_device_mode mode; 110 const struct dw_pcie_host_ops *host_ops; 111 const struct dw_pcie_ep_ops *ep_ops; 112 unsigned int version; 113 }; 114 115 struct keystone_pcie { 116 struct dw_pcie *pci; 117 /* PCI Device ID */ 118 u32 device_id; 119 int legacy_host_irqs[PCI_NUM_INTX]; 120 struct device_node *legacy_intc_np; 121 122 int msi_host_irq; 123 int num_lanes; 124 u32 num_viewport; 125 struct phy **phy; 126 struct device_link **link; 127 struct device_node *msi_intc_np; 128 struct irq_domain *legacy_irq_domain; 129 struct device_node *np; 130 131 /* Application register space */ 132 void __iomem *va_app_base; /* DT 1st resource */ 133 struct resource app; 134 bool is_am6; 135 }; 136 137 static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 138 { 139 return readl(ks_pcie->va_app_base + offset); 140 } 141 142 static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 143 u32 val) 144 { 145 writel(val, ks_pcie->va_app_base + offset); 146 } 147 148 static void ks_pcie_msi_irq_ack(struct irq_data *data) 149 { 150 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 151 struct keystone_pcie *ks_pcie; 152 u32 irq = data->hwirq; 153 struct dw_pcie *pci; 154 u32 reg_offset; 155 u32 bit_pos; 156 157 pci = to_dw_pcie_from_pp(pp); 158 ks_pcie = to_keystone_pcie(pci); 159 160 reg_offset = irq % 8; 161 bit_pos = irq >> 3; 162 163 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 164 BIT(bit_pos)); 165 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 166 } 167 168 static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 169 { 170 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 171 struct keystone_pcie *ks_pcie; 172 struct dw_pcie *pci; 173 u64 msi_target; 174 175 pci = to_dw_pcie_from_pp(pp); 176 ks_pcie = to_keystone_pcie(pci); 177 178 msi_target = ks_pcie->app.start + MSI_IRQ; 179 msg->address_lo = lower_32_bits(msi_target); 180 msg->address_hi = upper_32_bits(msi_target); 181 msg->data = data->hwirq; 182 183 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 184 (int)data->hwirq, msg->address_hi, msg->address_lo); 185 } 186 187 static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 188 const struct cpumask *mask, bool force) 189 { 190 return -EINVAL; 191 } 192 193 static void ks_pcie_msi_mask(struct irq_data *data) 194 { 195 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 196 struct keystone_pcie *ks_pcie; 197 u32 irq = data->hwirq; 198 struct dw_pcie *pci; 199 unsigned long flags; 200 u32 reg_offset; 201 u32 bit_pos; 202 203 raw_spin_lock_irqsave(&pp->lock, flags); 204 205 pci = to_dw_pcie_from_pp(pp); 206 ks_pcie = to_keystone_pcie(pci); 207 208 reg_offset = irq % 8; 209 bit_pos = irq >> 3; 210 211 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 212 BIT(bit_pos)); 213 214 raw_spin_unlock_irqrestore(&pp->lock, flags); 215 } 216 217 static void ks_pcie_msi_unmask(struct irq_data *data) 218 { 219 struct pcie_port *pp = irq_data_get_irq_chip_data(data); 220 struct keystone_pcie *ks_pcie; 221 u32 irq = data->hwirq; 222 struct dw_pcie *pci; 223 unsigned long flags; 224 u32 reg_offset; 225 u32 bit_pos; 226 227 raw_spin_lock_irqsave(&pp->lock, flags); 228 229 pci = to_dw_pcie_from_pp(pp); 230 ks_pcie = to_keystone_pcie(pci); 231 232 reg_offset = irq % 8; 233 bit_pos = irq >> 3; 234 235 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 236 BIT(bit_pos)); 237 238 raw_spin_unlock_irqrestore(&pp->lock, flags); 239 } 240 241 static struct irq_chip ks_pcie_msi_irq_chip = { 242 .name = "KEYSTONE-PCI-MSI", 243 .irq_ack = ks_pcie_msi_irq_ack, 244 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 245 .irq_set_affinity = ks_pcie_msi_set_affinity, 246 .irq_mask = ks_pcie_msi_mask, 247 .irq_unmask = ks_pcie_msi_unmask, 248 }; 249 250 static int ks_pcie_msi_host_init(struct pcie_port *pp) 251 { 252 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 253 return dw_pcie_allocate_domains(pp); 254 } 255 256 static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, 257 int offset) 258 { 259 struct dw_pcie *pci = ks_pcie->pci; 260 struct device *dev = pci->dev; 261 u32 pending; 262 int virq; 263 264 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 265 266 if (BIT(0) & pending) { 267 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); 268 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); 269 generic_handle_irq(virq); 270 } 271 272 /* EOI the INTx interrupt */ 273 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 274 } 275 276 static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 277 { 278 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 279 } 280 281 static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 282 { 283 u32 reg; 284 struct device *dev = ks_pcie->pci->dev; 285 286 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 287 if (!reg) 288 return IRQ_NONE; 289 290 if (reg & ERR_SYS) 291 dev_err(dev, "System Error\n"); 292 293 if (reg & ERR_FATAL) 294 dev_err(dev, "Fatal Error\n"); 295 296 if (reg & ERR_NONFATAL) 297 dev_dbg(dev, "Non Fatal Error\n"); 298 299 if (reg & ERR_CORR) 300 dev_dbg(dev, "Correctable Error\n"); 301 302 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 303 dev_err(dev, "AXI tag lookup fatal Error\n"); 304 305 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 306 dev_err(dev, "ECRC Error\n"); 307 308 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 309 310 return IRQ_HANDLED; 311 } 312 313 static void ks_pcie_ack_legacy_irq(struct irq_data *d) 314 { 315 } 316 317 static void ks_pcie_mask_legacy_irq(struct irq_data *d) 318 { 319 } 320 321 static void ks_pcie_unmask_legacy_irq(struct irq_data *d) 322 { 323 } 324 325 static struct irq_chip ks_pcie_legacy_irq_chip = { 326 .name = "Keystone-PCI-Legacy-IRQ", 327 .irq_ack = ks_pcie_ack_legacy_irq, 328 .irq_mask = ks_pcie_mask_legacy_irq, 329 .irq_unmask = ks_pcie_unmask_legacy_irq, 330 }; 331 332 static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, 333 unsigned int irq, 334 irq_hw_number_t hw_irq) 335 { 336 irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip, 337 handle_level_irq); 338 irq_set_chip_data(irq, d->host_data); 339 340 return 0; 341 } 342 343 static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = { 344 .map = ks_pcie_init_legacy_irq_map, 345 .xlate = irq_domain_xlate_onetwocell, 346 }; 347 348 /** 349 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask 350 * registers 351 * 352 * Since modification of dbi_cs2 involves different clock domain, read the 353 * status back to ensure the transition is complete. 354 */ 355 static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 356 { 357 u32 val; 358 359 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 360 val |= DBI_CS2; 361 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 362 363 do { 364 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 365 } while (!(val & DBI_CS2)); 366 } 367 368 /** 369 * ks_pcie_clear_dbi_mode() - Disable DBI mode 370 * 371 * Since modification of dbi_cs2 involves different clock domain, read the 372 * status back to ensure the transition is complete. 373 */ 374 static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 375 { 376 u32 val; 377 378 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 379 val &= ~DBI_CS2; 380 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 381 382 do { 383 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 384 } while (val & DBI_CS2); 385 } 386 387 static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 388 { 389 u32 val; 390 u32 num_viewport = ks_pcie->num_viewport; 391 struct dw_pcie *pci = ks_pcie->pci; 392 struct pcie_port *pp = &pci->pp; 393 u64 start, end; 394 struct resource *mem; 395 int i; 396 397 mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res; 398 start = mem->start; 399 end = mem->end; 400 401 /* Disable BARs for inbound access */ 402 ks_pcie_set_dbi_mode(ks_pcie); 403 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 404 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 405 ks_pcie_clear_dbi_mode(ks_pcie); 406 407 if (ks_pcie->is_am6) 408 return; 409 410 val = ilog2(OB_WIN_SIZE); 411 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 412 413 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 414 for (i = 0; i < num_viewport && (start < end); i++) { 415 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 416 lower_32_bits(start) | OB_ENABLEN); 417 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 418 upper_32_bits(start)); 419 start += OB_WIN_SIZE * SZ_1M; 420 } 421 422 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 423 val |= OB_XLAT_EN_VAL; 424 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 425 } 426 427 static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 428 unsigned int devfn, int where) 429 { 430 struct pcie_port *pp = bus->sysdata; 431 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 432 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 433 u32 reg; 434 435 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 436 CFG_FUNC(PCI_FUNC(devfn)); 437 if (!pci_is_root_bus(bus->parent)) 438 reg |= CFG_TYPE1; 439 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 440 441 return pp->va_cfg0_base + where; 442 } 443 444 static struct pci_ops ks_child_pcie_ops = { 445 .map_bus = ks_pcie_other_map_bus, 446 .read = pci_generic_config_read, 447 .write = pci_generic_config_write, 448 }; 449 450 /** 451 * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization 452 * 453 * This sets BAR0 to enable inbound access for MSI_IRQ register 454 */ 455 static int ks_pcie_v3_65_add_bus(struct pci_bus *bus) 456 { 457 struct pcie_port *pp = bus->sysdata; 458 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 459 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 460 461 if (!pci_is_root_bus(bus)) 462 return 0; 463 464 /* Configure and set up BAR0 */ 465 ks_pcie_set_dbi_mode(ks_pcie); 466 467 /* Enable BAR0 */ 468 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 469 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 470 471 ks_pcie_clear_dbi_mode(ks_pcie); 472 473 /* 474 * For BAR0, just setting bus address for inbound writes (MSI) should 475 * be sufficient. Use physical address to avoid any conflicts. 476 */ 477 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 478 479 return 0; 480 } 481 482 static struct pci_ops ks_pcie_ops = { 483 .map_bus = dw_pcie_own_conf_map_bus, 484 .read = pci_generic_config_read, 485 .write = pci_generic_config_write, 486 .add_bus = ks_pcie_v3_65_add_bus, 487 }; 488 489 /** 490 * ks_pcie_link_up() - Check if link up 491 */ 492 static int ks_pcie_link_up(struct dw_pcie *pci) 493 { 494 u32 val; 495 496 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 497 val &= PORT_LOGIC_LTSSM_STATE_MASK; 498 return (val == PORT_LOGIC_LTSSM_STATE_L0); 499 } 500 501 static void ks_pcie_stop_link(struct dw_pcie *pci) 502 { 503 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 504 u32 val; 505 506 /* Disable Link training */ 507 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 508 val &= ~LTSSM_EN_VAL; 509 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 510 } 511 512 static int ks_pcie_start_link(struct dw_pcie *pci) 513 { 514 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 515 u32 val; 516 517 /* Initiate Link Training */ 518 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 519 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 520 521 return 0; 522 } 523 524 static void ks_pcie_quirk(struct pci_dev *dev) 525 { 526 struct pci_bus *bus = dev->bus; 527 struct pci_dev *bridge; 528 static const struct pci_device_id rc_pci_devids[] = { 529 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 530 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 531 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 532 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 533 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 534 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 535 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 536 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 537 { 0, }, 538 }; 539 540 if (pci_is_root_bus(bus)) 541 bridge = dev; 542 543 /* look for the host bridge */ 544 while (!pci_is_root_bus(bus)) { 545 bridge = bus->self; 546 bus = bus->parent; 547 } 548 549 if (!bridge) 550 return; 551 552 /* 553 * Keystone PCI controller has a h/w limitation of 554 * 256 bytes maximum read request size. It can't handle 555 * anything higher than this. So force this limit on 556 * all downstream devices. 557 */ 558 if (pci_match_id(rc_pci_devids, bridge)) { 559 if (pcie_get_readrq(dev) > 256) { 560 dev_info(&dev->dev, "limiting MRRS to 256\n"); 561 pcie_set_readrq(dev, 256); 562 } 563 } 564 } 565 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 566 567 static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 568 { 569 unsigned int irq = desc->irq_data.hwirq; 570 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 571 u32 offset = irq - ks_pcie->msi_host_irq; 572 struct dw_pcie *pci = ks_pcie->pci; 573 struct pcie_port *pp = &pci->pp; 574 struct device *dev = pci->dev; 575 struct irq_chip *chip = irq_desc_get_chip(desc); 576 u32 vector, virq, reg, pos; 577 578 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 579 580 /* 581 * The chained irq handler installation would have replaced normal 582 * interrupt driver handler so we need to take care of mask/unmask and 583 * ack operation. 584 */ 585 chained_irq_enter(chip, desc); 586 587 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 588 /* 589 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 590 * shows 1, 9, 17, 25 and so forth 591 */ 592 for (pos = 0; pos < 4; pos++) { 593 if (!(reg & BIT(pos))) 594 continue; 595 596 vector = offset + (pos << 3); 597 virq = irq_linear_revmap(pp->irq_domain, vector); 598 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector, 599 virq); 600 generic_handle_irq(virq); 601 } 602 603 chained_irq_exit(chip, desc); 604 } 605 606 /** 607 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt 608 * @irq: IRQ line for legacy interrupts 609 * @desc: Pointer to irq descriptor 610 * 611 * Traverse through pending legacy interrupts and invoke handler for each. Also 612 * takes care of interrupt controller level mask/ack operation. 613 */ 614 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) 615 { 616 unsigned int irq = irq_desc_get_irq(desc); 617 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 618 struct dw_pcie *pci = ks_pcie->pci; 619 struct device *dev = pci->dev; 620 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; 621 struct irq_chip *chip = irq_desc_get_chip(desc); 622 623 dev_dbg(dev, ": Handling legacy irq %d\n", irq); 624 625 /* 626 * The chained irq handler installation would have replaced normal 627 * interrupt driver handler so we need to take care of mask/unmask and 628 * ack operation. 629 */ 630 chained_irq_enter(chip, desc); 631 ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); 632 chained_irq_exit(chip, desc); 633 } 634 635 static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 636 { 637 struct device *dev = ks_pcie->pci->dev; 638 struct device_node *np = ks_pcie->np; 639 struct device_node *intc_np; 640 struct irq_data *irq_data; 641 int irq_count, irq, ret, i; 642 643 if (!IS_ENABLED(CONFIG_PCI_MSI)) 644 return 0; 645 646 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 647 if (!intc_np) { 648 if (ks_pcie->is_am6) 649 return 0; 650 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 651 return -EINVAL; 652 } 653 654 irq_count = of_irq_count(intc_np); 655 if (!irq_count) { 656 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 657 ret = -EINVAL; 658 goto err; 659 } 660 661 for (i = 0; i < irq_count; i++) { 662 irq = irq_of_parse_and_map(intc_np, i); 663 if (!irq) { 664 ret = -EINVAL; 665 goto err; 666 } 667 668 if (!ks_pcie->msi_host_irq) { 669 irq_data = irq_get_irq_data(irq); 670 if (!irq_data) { 671 ret = -EINVAL; 672 goto err; 673 } 674 ks_pcie->msi_host_irq = irq_data->hwirq; 675 } 676 677 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 678 ks_pcie); 679 } 680 681 of_node_put(intc_np); 682 return 0; 683 684 err: 685 of_node_put(intc_np); 686 return ret; 687 } 688 689 static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) 690 { 691 struct device *dev = ks_pcie->pci->dev; 692 struct irq_domain *legacy_irq_domain; 693 struct device_node *np = ks_pcie->np; 694 struct device_node *intc_np; 695 int irq_count, irq, ret = 0, i; 696 697 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 698 if (!intc_np) { 699 /* 700 * Since legacy interrupts are modeled as edge-interrupts in 701 * AM6, keep it disabled for now. 702 */ 703 if (ks_pcie->is_am6) 704 return 0; 705 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 706 return -EINVAL; 707 } 708 709 irq_count = of_irq_count(intc_np); 710 if (!irq_count) { 711 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 712 ret = -EINVAL; 713 goto err; 714 } 715 716 for (i = 0; i < irq_count; i++) { 717 irq = irq_of_parse_and_map(intc_np, i); 718 if (!irq) { 719 ret = -EINVAL; 720 goto err; 721 } 722 ks_pcie->legacy_host_irqs[i] = irq; 723 724 irq_set_chained_handler_and_data(irq, 725 ks_pcie_legacy_irq_handler, 726 ks_pcie); 727 } 728 729 legacy_irq_domain = 730 irq_domain_add_linear(intc_np, PCI_NUM_INTX, 731 &ks_pcie_legacy_irq_domain_ops, NULL); 732 if (!legacy_irq_domain) { 733 dev_err(dev, "Failed to add irq domain for legacy irqs\n"); 734 ret = -EINVAL; 735 goto err; 736 } 737 ks_pcie->legacy_irq_domain = legacy_irq_domain; 738 739 for (i = 0; i < PCI_NUM_INTX; i++) 740 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 741 742 err: 743 of_node_put(intc_np); 744 return ret; 745 } 746 747 #ifdef CONFIG_ARM 748 /* 749 * When a PCI device does not exist during config cycles, keystone host gets a 750 * bus error instead of returning 0xffffffff. This handler always returns 0 751 * for this kind of faults. 752 */ 753 static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 754 struct pt_regs *regs) 755 { 756 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 757 758 if ((instr & 0x0e100090) == 0x00100090) { 759 int reg = (instr >> 12) & 15; 760 761 regs->uregs[reg] = -1; 762 regs->ARM_pc += 4; 763 } 764 765 return 0; 766 } 767 #endif 768 769 static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 770 { 771 int ret; 772 unsigned int id; 773 struct regmap *devctrl_regs; 774 struct dw_pcie *pci = ks_pcie->pci; 775 struct device *dev = pci->dev; 776 struct device_node *np = dev->of_node; 777 778 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 779 if (IS_ERR(devctrl_regs)) 780 return PTR_ERR(devctrl_regs); 781 782 ret = regmap_read(devctrl_regs, 0, &id); 783 if (ret) 784 return ret; 785 786 dw_pcie_dbi_ro_wr_en(pci); 787 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 788 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 789 dw_pcie_dbi_ro_wr_dis(pci); 790 791 return 0; 792 } 793 794 static int __init ks_pcie_host_init(struct pcie_port *pp) 795 { 796 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 797 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 798 int ret; 799 800 pp->bridge->ops = &ks_pcie_ops; 801 pp->bridge->child_ops = &ks_child_pcie_ops; 802 803 ret = ks_pcie_config_legacy_irq(ks_pcie); 804 if (ret) 805 return ret; 806 807 ret = ks_pcie_config_msi_irq(ks_pcie); 808 if (ret) 809 return ret; 810 811 ks_pcie_stop_link(pci); 812 ks_pcie_setup_rc_app_regs(ks_pcie); 813 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 814 pci->dbi_base + PCI_IO_BASE); 815 816 ret = ks_pcie_init_id(ks_pcie); 817 if (ret < 0) 818 return ret; 819 820 #ifdef CONFIG_ARM 821 /* 822 * PCIe access errors that result into OCP errors are caught by ARM as 823 * "External aborts" 824 */ 825 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 826 "Asynchronous external abort"); 827 #endif 828 829 return 0; 830 } 831 832 static const struct dw_pcie_host_ops ks_pcie_host_ops = { 833 .host_init = ks_pcie_host_init, 834 .msi_host_init = ks_pcie_msi_host_init, 835 }; 836 837 static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 838 .host_init = ks_pcie_host_init, 839 }; 840 841 static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 842 { 843 struct keystone_pcie *ks_pcie = priv; 844 845 return ks_pcie_handle_error_irq(ks_pcie); 846 } 847 848 static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 849 u32 reg, size_t size, u32 val) 850 { 851 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 852 853 ks_pcie_set_dbi_mode(ks_pcie); 854 dw_pcie_write(base + reg, size, val); 855 ks_pcie_clear_dbi_mode(ks_pcie); 856 } 857 858 static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 859 .start_link = ks_pcie_start_link, 860 .stop_link = ks_pcie_stop_link, 861 .link_up = ks_pcie_link_up, 862 .write_dbi2 = ks_pcie_am654_write_dbi2, 863 }; 864 865 static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 866 { 867 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 868 int flags; 869 870 ep->page_size = AM654_WIN_SIZE; 871 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 872 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 873 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 874 } 875 876 static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) 877 { 878 struct dw_pcie *pci = ks_pcie->pci; 879 u8 int_pin; 880 881 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 882 if (int_pin == 0 || int_pin > 4) 883 return; 884 885 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 886 INT_ENABLE); 887 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 888 mdelay(1); 889 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 890 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 891 INT_ENABLE); 892 } 893 894 static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 895 enum pci_epc_irq_type type, 896 u16 interrupt_num) 897 { 898 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 899 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 900 901 switch (type) { 902 case PCI_EPC_IRQ_LEGACY: 903 ks_pcie_am654_raise_legacy_irq(ks_pcie); 904 break; 905 case PCI_EPC_IRQ_MSI: 906 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 907 break; 908 case PCI_EPC_IRQ_MSIX: 909 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 910 break; 911 default: 912 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 913 return -EINVAL; 914 } 915 916 return 0; 917 } 918 919 static const struct pci_epc_features ks_pcie_am654_epc_features = { 920 .linkup_notifier = false, 921 .msi_capable = true, 922 .msix_capable = true, 923 .reserved_bar = 1 << BAR_0 | 1 << BAR_1, 924 .bar_fixed_64bit = 1 << BAR_0, 925 .bar_fixed_size[2] = SZ_1M, 926 .bar_fixed_size[3] = SZ_64K, 927 .bar_fixed_size[4] = 256, 928 .bar_fixed_size[5] = SZ_1M, 929 .align = SZ_1M, 930 }; 931 932 static const struct pci_epc_features* 933 ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 934 { 935 return &ks_pcie_am654_epc_features; 936 } 937 938 static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 939 .ep_init = ks_pcie_am654_ep_init, 940 .raise_irq = ks_pcie_am654_raise_irq, 941 .get_features = &ks_pcie_am654_get_features, 942 }; 943 944 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 945 { 946 int num_lanes = ks_pcie->num_lanes; 947 948 while (num_lanes--) { 949 phy_power_off(ks_pcie->phy[num_lanes]); 950 phy_exit(ks_pcie->phy[num_lanes]); 951 } 952 } 953 954 static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 955 { 956 int i; 957 int ret; 958 int num_lanes = ks_pcie->num_lanes; 959 960 for (i = 0; i < num_lanes; i++) { 961 ret = phy_reset(ks_pcie->phy[i]); 962 if (ret < 0) 963 goto err_phy; 964 965 ret = phy_init(ks_pcie->phy[i]); 966 if (ret < 0) 967 goto err_phy; 968 969 ret = phy_power_on(ks_pcie->phy[i]); 970 if (ret < 0) { 971 phy_exit(ks_pcie->phy[i]); 972 goto err_phy; 973 } 974 } 975 976 return 0; 977 978 err_phy: 979 while (--i >= 0) { 980 phy_power_off(ks_pcie->phy[i]); 981 phy_exit(ks_pcie->phy[i]); 982 } 983 984 return ret; 985 } 986 987 static int ks_pcie_set_mode(struct device *dev) 988 { 989 struct device_node *np = dev->of_node; 990 struct regmap *syscon; 991 u32 val; 992 u32 mask; 993 int ret = 0; 994 995 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 996 if (IS_ERR(syscon)) 997 return 0; 998 999 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1000 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1001 1002 ret = regmap_update_bits(syscon, 0, mask, val); 1003 if (ret) { 1004 dev_err(dev, "failed to set pcie mode\n"); 1005 return ret; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int ks_pcie_am654_set_mode(struct device *dev, 1012 enum dw_pcie_device_mode mode) 1013 { 1014 struct device_node *np = dev->of_node; 1015 struct regmap *syscon; 1016 u32 val; 1017 u32 mask; 1018 int ret = 0; 1019 1020 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1021 if (IS_ERR(syscon)) 1022 return 0; 1023 1024 mask = AM654_PCIE_DEV_TYPE_MASK; 1025 1026 switch (mode) { 1027 case DW_PCIE_RC_TYPE: 1028 val = RC; 1029 break; 1030 case DW_PCIE_EP_TYPE: 1031 val = EP; 1032 break; 1033 default: 1034 dev_err(dev, "INVALID device type %d\n", mode); 1035 return -EINVAL; 1036 } 1037 1038 ret = regmap_update_bits(syscon, 0, mask, val); 1039 if (ret) { 1040 dev_err(dev, "failed to set pcie mode\n"); 1041 return ret; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1048 .host_ops = &ks_pcie_host_ops, 1049 .version = 0x365A, 1050 }; 1051 1052 static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1053 .host_ops = &ks_pcie_am654_host_ops, 1054 .mode = DW_PCIE_RC_TYPE, 1055 .version = 0x490A, 1056 }; 1057 1058 static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1059 .ep_ops = &ks_pcie_am654_ep_ops, 1060 .mode = DW_PCIE_EP_TYPE, 1061 .version = 0x490A, 1062 }; 1063 1064 static const struct of_device_id ks_pcie_of_match[] = { 1065 { 1066 .type = "pci", 1067 .data = &ks_pcie_rc_of_data, 1068 .compatible = "ti,keystone-pcie", 1069 }, 1070 { 1071 .data = &ks_pcie_am654_rc_of_data, 1072 .compatible = "ti,am654-pcie-rc", 1073 }, 1074 { 1075 .data = &ks_pcie_am654_ep_of_data, 1076 .compatible = "ti,am654-pcie-ep", 1077 }, 1078 { }, 1079 }; 1080 1081 static int __init ks_pcie_probe(struct platform_device *pdev) 1082 { 1083 const struct dw_pcie_host_ops *host_ops; 1084 const struct dw_pcie_ep_ops *ep_ops; 1085 struct device *dev = &pdev->dev; 1086 struct device_node *np = dev->of_node; 1087 const struct ks_pcie_of_data *data; 1088 const struct of_device_id *match; 1089 enum dw_pcie_device_mode mode; 1090 struct dw_pcie *pci; 1091 struct keystone_pcie *ks_pcie; 1092 struct device_link **link; 1093 struct gpio_desc *gpiod; 1094 struct resource *res; 1095 unsigned int version; 1096 void __iomem *base; 1097 u32 num_viewport; 1098 struct phy **phy; 1099 u32 num_lanes; 1100 char name[10]; 1101 int ret; 1102 int irq; 1103 int i; 1104 1105 match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); 1106 data = (struct ks_pcie_of_data *)match->data; 1107 if (!data) 1108 return -EINVAL; 1109 1110 version = data->version; 1111 host_ops = data->host_ops; 1112 ep_ops = data->ep_ops; 1113 mode = data->mode; 1114 1115 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1116 if (!ks_pcie) 1117 return -ENOMEM; 1118 1119 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1120 if (!pci) 1121 return -ENOMEM; 1122 1123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1124 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1125 if (IS_ERR(ks_pcie->va_app_base)) 1126 return PTR_ERR(ks_pcie->va_app_base); 1127 1128 ks_pcie->app = *res; 1129 1130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1131 base = devm_pci_remap_cfg_resource(dev, res); 1132 if (IS_ERR(base)) 1133 return PTR_ERR(base); 1134 1135 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1136 ks_pcie->is_am6 = true; 1137 1138 pci->dbi_base = base; 1139 pci->dbi_base2 = base; 1140 pci->dev = dev; 1141 pci->ops = &ks_pcie_dw_pcie_ops; 1142 pci->version = version; 1143 1144 irq = platform_get_irq(pdev, 0); 1145 if (irq < 0) 1146 return irq; 1147 1148 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1149 "ks-pcie-error-irq", ks_pcie); 1150 if (ret < 0) { 1151 dev_err(dev, "failed to request error IRQ %d\n", 1152 irq); 1153 return ret; 1154 } 1155 1156 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1157 if (ret) 1158 num_lanes = 1; 1159 1160 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1161 if (!phy) 1162 return -ENOMEM; 1163 1164 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1165 if (!link) 1166 return -ENOMEM; 1167 1168 for (i = 0; i < num_lanes; i++) { 1169 snprintf(name, sizeof(name), "pcie-phy%d", i); 1170 phy[i] = devm_phy_optional_get(dev, name); 1171 if (IS_ERR(phy[i])) { 1172 ret = PTR_ERR(phy[i]); 1173 goto err_link; 1174 } 1175 1176 if (!phy[i]) 1177 continue; 1178 1179 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1180 if (!link[i]) { 1181 ret = -EINVAL; 1182 goto err_link; 1183 } 1184 } 1185 1186 ks_pcie->np = np; 1187 ks_pcie->pci = pci; 1188 ks_pcie->link = link; 1189 ks_pcie->num_lanes = num_lanes; 1190 ks_pcie->phy = phy; 1191 1192 gpiod = devm_gpiod_get_optional(dev, "reset", 1193 GPIOD_OUT_LOW); 1194 if (IS_ERR(gpiod)) { 1195 ret = PTR_ERR(gpiod); 1196 if (ret != -EPROBE_DEFER) 1197 dev_err(dev, "Failed to get reset GPIO\n"); 1198 goto err_link; 1199 } 1200 1201 ret = ks_pcie_enable_phy(ks_pcie); 1202 if (ret) { 1203 dev_err(dev, "failed to enable phy\n"); 1204 goto err_link; 1205 } 1206 1207 platform_set_drvdata(pdev, ks_pcie); 1208 pm_runtime_enable(dev); 1209 ret = pm_runtime_get_sync(dev); 1210 if (ret < 0) { 1211 dev_err(dev, "pm_runtime_get_sync failed\n"); 1212 goto err_get_sync; 1213 } 1214 1215 if (pci->version >= 0x480A) 1216 ret = ks_pcie_am654_set_mode(dev, mode); 1217 else 1218 ret = ks_pcie_set_mode(dev); 1219 if (ret < 0) 1220 goto err_get_sync; 1221 1222 switch (mode) { 1223 case DW_PCIE_RC_TYPE: 1224 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1225 ret = -ENODEV; 1226 goto err_get_sync; 1227 } 1228 1229 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1230 if (ret < 0) { 1231 dev_err(dev, "unable to read *num-viewport* property\n"); 1232 goto err_get_sync; 1233 } 1234 1235 /* 1236 * "Power Sequencing and Reset Signal Timings" table in 1237 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1238 * indicates PERST# should be deasserted after minimum of 100us 1239 * once REFCLK is stable. The REFCLK to the connector in RC 1240 * mode is selected while enabling the PHY. So deassert PERST# 1241 * after 100 us. 1242 */ 1243 if (gpiod) { 1244 usleep_range(100, 200); 1245 gpiod_set_value_cansleep(gpiod, 1); 1246 } 1247 1248 ks_pcie->num_viewport = num_viewport; 1249 pci->pp.ops = host_ops; 1250 ret = dw_pcie_host_init(&pci->pp); 1251 if (ret < 0) 1252 goto err_get_sync; 1253 break; 1254 case DW_PCIE_EP_TYPE: 1255 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1256 ret = -ENODEV; 1257 goto err_get_sync; 1258 } 1259 1260 pci->ep.ops = ep_ops; 1261 ret = dw_pcie_ep_init(&pci->ep); 1262 if (ret < 0) 1263 goto err_get_sync; 1264 break; 1265 default: 1266 dev_err(dev, "INVALID device type %d\n", mode); 1267 } 1268 1269 ks_pcie_enable_error_irq(ks_pcie); 1270 1271 return 0; 1272 1273 err_get_sync: 1274 pm_runtime_put(dev); 1275 pm_runtime_disable(dev); 1276 ks_pcie_disable_phy(ks_pcie); 1277 1278 err_link: 1279 while (--i >= 0 && link[i]) 1280 device_link_del(link[i]); 1281 1282 return ret; 1283 } 1284 1285 static int __exit ks_pcie_remove(struct platform_device *pdev) 1286 { 1287 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1288 struct device_link **link = ks_pcie->link; 1289 int num_lanes = ks_pcie->num_lanes; 1290 struct device *dev = &pdev->dev; 1291 1292 pm_runtime_put(dev); 1293 pm_runtime_disable(dev); 1294 ks_pcie_disable_phy(ks_pcie); 1295 while (num_lanes--) 1296 device_link_del(link[num_lanes]); 1297 1298 return 0; 1299 } 1300 1301 static struct platform_driver ks_pcie_driver __refdata = { 1302 .probe = ks_pcie_probe, 1303 .remove = __exit_p(ks_pcie_remove), 1304 .driver = { 1305 .name = "keystone-pcie", 1306 .of_match_table = of_match_ptr(ks_pcie_of_match), 1307 }, 1308 }; 1309 builtin_platform_driver(ks_pcie_driver); 1310