1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * https://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19 #include <linux/module.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_device.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 #include <linux/types.h> 30 #include <linux/interrupt.h> 31 #include <linux/reset.h> 32 #include <linux/phy/phy.h> 33 #include <linux/pm_domain.h> 34 #include <linux/pm_runtime.h> 35 36 #include "pcie-designware.h" 37 38 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 40 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 41 #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) 42 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 43 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 44 45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 46 47 enum imx6_pcie_variants { 48 IMX6Q, 49 IMX6SX, 50 IMX6QP, 51 IMX7D, 52 IMX8MQ, 53 IMX8MM, 54 IMX8MP, 55 IMX8MQ_EP, 56 IMX8MM_EP, 57 IMX8MP_EP, 58 }; 59 60 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 61 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 62 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 63 64 struct imx6_pcie_drvdata { 65 enum imx6_pcie_variants variant; 66 enum dw_pcie_device_mode mode; 67 u32 flags; 68 int dbi_length; 69 const char *gpr; 70 }; 71 72 struct imx6_pcie { 73 struct dw_pcie *pci; 74 int reset_gpio; 75 bool gpio_active_high; 76 bool link_is_up; 77 struct clk *pcie_bus; 78 struct clk *pcie_phy; 79 struct clk *pcie_inbound_axi; 80 struct clk *pcie; 81 struct clk *pcie_aux; 82 struct regmap *iomuxc_gpr; 83 u32 controller_id; 84 struct reset_control *pciephy_reset; 85 struct reset_control *apps_reset; 86 struct reset_control *turnoff_reset; 87 u32 tx_deemph_gen1; 88 u32 tx_deemph_gen2_3p5db; 89 u32 tx_deemph_gen2_6db; 90 u32 tx_swing_full; 91 u32 tx_swing_low; 92 struct regulator *vpcie; 93 struct regulator *vph; 94 void __iomem *phy_base; 95 96 /* power domain for pcie */ 97 struct device *pd_pcie; 98 /* power domain for pcie phy */ 99 struct device *pd_pcie_phy; 100 struct phy *phy; 101 const struct imx6_pcie_drvdata *drvdata; 102 }; 103 104 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 105 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 106 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 107 108 /* PCIe Port Logic registers (memory-mapped) */ 109 #define PL_OFFSET 0x700 110 111 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 112 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 113 #define PCIE_PHY_CTRL_CAP_ADR BIT(16) 114 #define PCIE_PHY_CTRL_CAP_DAT BIT(17) 115 #define PCIE_PHY_CTRL_WR BIT(18) 116 #define PCIE_PHY_CTRL_RD BIT(19) 117 118 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 119 #define PCIE_PHY_STAT_ACK BIT(16) 120 121 /* PHY registers (not memory-mapped) */ 122 #define PCIE_PHY_ATEOVRD 0x10 123 #define PCIE_PHY_ATEOVRD_EN BIT(2) 124 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 125 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 126 127 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 128 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 129 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 130 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 131 132 #define PCIE_PHY_RX_ASIC_OUT 0x100D 133 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 134 135 /* iMX7 PCIe PHY registers */ 136 #define PCIE_PHY_CMN_REG4 0x14 137 /* These are probably the bits that *aren't* DCC_FB_EN */ 138 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 139 140 #define PCIE_PHY_CMN_REG15 0x54 141 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 142 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 143 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 144 145 #define PCIE_PHY_CMN_REG24 0x90 146 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 147 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 148 149 #define PCIE_PHY_CMN_REG26 0x98 150 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 151 152 #define PHY_RX_OVRD_IN_LO 0x1005 153 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 154 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 155 156 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 157 { 158 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 159 imx6_pcie->drvdata->variant != IMX8MQ_EP && 160 imx6_pcie->drvdata->variant != IMX8MM && 161 imx6_pcie->drvdata->variant != IMX8MM_EP && 162 imx6_pcie->drvdata->variant != IMX8MP && 163 imx6_pcie->drvdata->variant != IMX8MP_EP); 164 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 165 } 166 167 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 168 { 169 unsigned int mask, val, mode; 170 171 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) 172 mode = PCI_EXP_TYPE_ENDPOINT; 173 else 174 mode = PCI_EXP_TYPE_ROOT_PORT; 175 176 switch (imx6_pcie->drvdata->variant) { 177 case IMX8MQ: 178 case IMX8MQ_EP: 179 if (imx6_pcie->controller_id == 1) { 180 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; 181 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 182 mode); 183 } else { 184 mask = IMX6Q_GPR12_DEVICE_TYPE; 185 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); 186 } 187 break; 188 default: 189 mask = IMX6Q_GPR12_DEVICE_TYPE; 190 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); 191 break; 192 } 193 194 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); 195 } 196 197 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 198 { 199 struct dw_pcie *pci = imx6_pcie->pci; 200 bool val; 201 u32 max_iterations = 10; 202 u32 wait_counter = 0; 203 204 do { 205 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 206 PCIE_PHY_STAT_ACK; 207 wait_counter++; 208 209 if (val == exp_val) 210 return 0; 211 212 udelay(1); 213 } while (wait_counter < max_iterations); 214 215 return -ETIMEDOUT; 216 } 217 218 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 219 { 220 struct dw_pcie *pci = imx6_pcie->pci; 221 u32 val; 222 int ret; 223 224 val = PCIE_PHY_CTRL_DATA(addr); 225 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 226 227 val |= PCIE_PHY_CTRL_CAP_ADR; 228 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 229 230 ret = pcie_phy_poll_ack(imx6_pcie, true); 231 if (ret) 232 return ret; 233 234 val = PCIE_PHY_CTRL_DATA(addr); 235 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 236 237 return pcie_phy_poll_ack(imx6_pcie, false); 238 } 239 240 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 241 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 242 { 243 struct dw_pcie *pci = imx6_pcie->pci; 244 u32 phy_ctl; 245 int ret; 246 247 ret = pcie_phy_wait_ack(imx6_pcie, addr); 248 if (ret) 249 return ret; 250 251 /* assert Read signal */ 252 phy_ctl = PCIE_PHY_CTRL_RD; 253 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 254 255 ret = pcie_phy_poll_ack(imx6_pcie, true); 256 if (ret) 257 return ret; 258 259 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 260 261 /* deassert Read signal */ 262 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 263 264 return pcie_phy_poll_ack(imx6_pcie, false); 265 } 266 267 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 268 { 269 struct dw_pcie *pci = imx6_pcie->pci; 270 u32 var; 271 int ret; 272 273 /* write addr */ 274 /* cap addr */ 275 ret = pcie_phy_wait_ack(imx6_pcie, addr); 276 if (ret) 277 return ret; 278 279 var = PCIE_PHY_CTRL_DATA(data); 280 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 281 282 /* capture data */ 283 var |= PCIE_PHY_CTRL_CAP_DAT; 284 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 285 286 ret = pcie_phy_poll_ack(imx6_pcie, true); 287 if (ret) 288 return ret; 289 290 /* deassert cap data */ 291 var = PCIE_PHY_CTRL_DATA(data); 292 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 293 294 /* wait for ack de-assertion */ 295 ret = pcie_phy_poll_ack(imx6_pcie, false); 296 if (ret) 297 return ret; 298 299 /* assert wr signal */ 300 var = PCIE_PHY_CTRL_WR; 301 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 302 303 /* wait for ack */ 304 ret = pcie_phy_poll_ack(imx6_pcie, true); 305 if (ret) 306 return ret; 307 308 /* deassert wr signal */ 309 var = PCIE_PHY_CTRL_DATA(data); 310 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 311 312 /* wait for ack de-assertion */ 313 ret = pcie_phy_poll_ack(imx6_pcie, false); 314 if (ret) 315 return ret; 316 317 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 318 319 return 0; 320 } 321 322 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 323 { 324 switch (imx6_pcie->drvdata->variant) { 325 case IMX8MM: 326 case IMX8MM_EP: 327 case IMX8MP: 328 case IMX8MP_EP: 329 /* 330 * The PHY initialization had been done in the PHY 331 * driver, break here directly. 332 */ 333 break; 334 case IMX8MQ: 335 case IMX8MQ_EP: 336 /* 337 * TODO: Currently this code assumes external 338 * oscillator is being used 339 */ 340 regmap_update_bits(imx6_pcie->iomuxc_gpr, 341 imx6_pcie_grp_offset(imx6_pcie), 342 IMX8MQ_GPR_PCIE_REF_USE_PAD, 343 IMX8MQ_GPR_PCIE_REF_USE_PAD); 344 /* 345 * Regarding the datasheet, the PCIE_VPH is suggested 346 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the 347 * VREG_BYPASS should be cleared to zero. 348 */ 349 if (imx6_pcie->vph && 350 regulator_get_voltage(imx6_pcie->vph) > 3000000) 351 regmap_update_bits(imx6_pcie->iomuxc_gpr, 352 imx6_pcie_grp_offset(imx6_pcie), 353 IMX8MQ_GPR_PCIE_VREG_BYPASS, 354 0); 355 break; 356 case IMX7D: 357 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 358 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 359 break; 360 case IMX6SX: 361 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 362 IMX6SX_GPR12_PCIE_RX_EQ_MASK, 363 IMX6SX_GPR12_PCIE_RX_EQ_2); 364 fallthrough; 365 default: 366 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 367 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 368 369 /* configure constant input signal to the pcie ctrl and phy */ 370 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 371 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 372 373 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 374 IMX6Q_GPR8_TX_DEEMPH_GEN1, 375 imx6_pcie->tx_deemph_gen1 << 0); 376 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 377 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 378 imx6_pcie->tx_deemph_gen2_3p5db << 6); 379 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 380 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 381 imx6_pcie->tx_deemph_gen2_6db << 12); 382 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 383 IMX6Q_GPR8_TX_SWING_FULL, 384 imx6_pcie->tx_swing_full << 18); 385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 386 IMX6Q_GPR8_TX_SWING_LOW, 387 imx6_pcie->tx_swing_low << 25); 388 break; 389 } 390 391 imx6_pcie_configure_type(imx6_pcie); 392 } 393 394 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 395 { 396 u32 val; 397 struct device *dev = imx6_pcie->pci->dev; 398 399 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 400 IOMUXC_GPR22, val, 401 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 402 PHY_PLL_LOCK_WAIT_USLEEP_MAX, 403 PHY_PLL_LOCK_WAIT_TIMEOUT)) 404 dev_err(dev, "PCIe PLL lock timeout\n"); 405 } 406 407 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 408 { 409 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); 410 int mult, div; 411 u16 val; 412 413 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 414 return 0; 415 416 switch (phy_rate) { 417 case 125000000: 418 /* 419 * The default settings of the MPLL are for a 125MHz input 420 * clock, so no need to reconfigure anything in that case. 421 */ 422 return 0; 423 case 100000000: 424 mult = 25; 425 div = 0; 426 break; 427 case 200000000: 428 mult = 25; 429 div = 1; 430 break; 431 default: 432 dev_err(imx6_pcie->pci->dev, 433 "Unsupported PHY reference clock rate %lu\n", phy_rate); 434 return -EINVAL; 435 } 436 437 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 438 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 439 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 440 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 441 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 442 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 443 444 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 445 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 446 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 447 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 448 val |= PCIE_PHY_ATEOVRD_EN; 449 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 450 451 return 0; 452 } 453 454 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 455 { 456 u16 tmp; 457 458 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 459 return; 460 461 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 462 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 463 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 464 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 465 466 usleep_range(2000, 3000); 467 468 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 469 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 470 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 471 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 472 } 473 474 #ifdef CONFIG_ARM 475 /* Added for PCI abort handling */ 476 static int imx6q_pcie_abort_handler(unsigned long addr, 477 unsigned int fsr, struct pt_regs *regs) 478 { 479 unsigned long pc = instruction_pointer(regs); 480 unsigned long instr = *(unsigned long *)pc; 481 int reg = (instr >> 12) & 15; 482 483 /* 484 * If the instruction being executed was a read, 485 * make it look like it read all-ones. 486 */ 487 if ((instr & 0x0c100000) == 0x04100000) { 488 unsigned long val; 489 490 if (instr & 0x00400000) 491 val = 255; 492 else 493 val = -1; 494 495 regs->uregs[reg] = val; 496 regs->ARM_pc += 4; 497 return 0; 498 } 499 500 if ((instr & 0x0e100090) == 0x00100090) { 501 regs->uregs[reg] = -1; 502 regs->ARM_pc += 4; 503 return 0; 504 } 505 506 return 1; 507 } 508 #endif 509 510 static int imx6_pcie_attach_pd(struct device *dev) 511 { 512 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 513 struct device_link *link; 514 515 /* Do nothing when in a single power domain */ 516 if (dev->pm_domain) 517 return 0; 518 519 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 520 if (IS_ERR(imx6_pcie->pd_pcie)) 521 return PTR_ERR(imx6_pcie->pd_pcie); 522 /* Do nothing when power domain missing */ 523 if (!imx6_pcie->pd_pcie) 524 return 0; 525 link = device_link_add(dev, imx6_pcie->pd_pcie, 526 DL_FLAG_STATELESS | 527 DL_FLAG_PM_RUNTIME | 528 DL_FLAG_RPM_ACTIVE); 529 if (!link) { 530 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 531 return -EINVAL; 532 } 533 534 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 535 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 536 return PTR_ERR(imx6_pcie->pd_pcie_phy); 537 538 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 539 DL_FLAG_STATELESS | 540 DL_FLAG_PM_RUNTIME | 541 DL_FLAG_RPM_ACTIVE); 542 if (!link) { 543 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 544 return -EINVAL; 545 } 546 547 return 0; 548 } 549 550 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 551 { 552 struct dw_pcie *pci = imx6_pcie->pci; 553 struct device *dev = pci->dev; 554 unsigned int offset; 555 int ret = 0; 556 557 switch (imx6_pcie->drvdata->variant) { 558 case IMX6SX: 559 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 560 if (ret) { 561 dev_err(dev, "unable to enable pcie_axi clock\n"); 562 break; 563 } 564 565 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 566 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 567 break; 568 case IMX6QP: 569 case IMX6Q: 570 /* power up core phy and enable ref clock */ 571 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 572 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 573 /* 574 * the async reset input need ref clock to sync internally, 575 * when the ref clock comes after reset, internal synced 576 * reset time is too short, cannot meet the requirement. 577 * add one ~10us delay here. 578 */ 579 usleep_range(10, 100); 580 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 581 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 582 break; 583 case IMX7D: 584 break; 585 case IMX8MM: 586 case IMX8MM_EP: 587 case IMX8MQ: 588 case IMX8MQ_EP: 589 case IMX8MP: 590 case IMX8MP_EP: 591 ret = clk_prepare_enable(imx6_pcie->pcie_aux); 592 if (ret) { 593 dev_err(dev, "unable to enable pcie_aux clock\n"); 594 break; 595 } 596 597 offset = imx6_pcie_grp_offset(imx6_pcie); 598 /* 599 * Set the over ride low and enabled 600 * make sure that REF_CLK is turned on. 601 */ 602 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 603 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 604 0); 605 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 606 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 607 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 608 break; 609 } 610 611 return ret; 612 } 613 614 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 615 { 616 switch (imx6_pcie->drvdata->variant) { 617 case IMX6SX: 618 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 619 break; 620 case IMX6QP: 621 case IMX6Q: 622 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 623 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 624 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 625 IMX6Q_GPR1_PCIE_TEST_PD, 626 IMX6Q_GPR1_PCIE_TEST_PD); 627 break; 628 case IMX7D: 629 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 630 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 631 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 632 break; 633 case IMX8MM: 634 case IMX8MM_EP: 635 case IMX8MQ: 636 case IMX8MQ_EP: 637 case IMX8MP: 638 case IMX8MP_EP: 639 clk_disable_unprepare(imx6_pcie->pcie_aux); 640 break; 641 default: 642 break; 643 } 644 } 645 646 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 647 { 648 struct dw_pcie *pci = imx6_pcie->pci; 649 struct device *dev = pci->dev; 650 int ret; 651 652 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 653 if (ret) { 654 dev_err(dev, "unable to enable pcie_phy clock\n"); 655 return ret; 656 } 657 658 ret = clk_prepare_enable(imx6_pcie->pcie_bus); 659 if (ret) { 660 dev_err(dev, "unable to enable pcie_bus clock\n"); 661 goto err_pcie_bus; 662 } 663 664 ret = clk_prepare_enable(imx6_pcie->pcie); 665 if (ret) { 666 dev_err(dev, "unable to enable pcie clock\n"); 667 goto err_pcie; 668 } 669 670 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 671 if (ret) { 672 dev_err(dev, "unable to enable pcie ref clock\n"); 673 goto err_ref_clk; 674 } 675 676 /* allow the clocks to stabilize */ 677 usleep_range(200, 500); 678 return 0; 679 680 err_ref_clk: 681 clk_disable_unprepare(imx6_pcie->pcie); 682 err_pcie: 683 clk_disable_unprepare(imx6_pcie->pcie_bus); 684 err_pcie_bus: 685 clk_disable_unprepare(imx6_pcie->pcie_phy); 686 687 return ret; 688 } 689 690 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 691 { 692 imx6_pcie_disable_ref_clk(imx6_pcie); 693 clk_disable_unprepare(imx6_pcie->pcie); 694 clk_disable_unprepare(imx6_pcie->pcie_bus); 695 clk_disable_unprepare(imx6_pcie->pcie_phy); 696 } 697 698 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 699 { 700 switch (imx6_pcie->drvdata->variant) { 701 case IMX7D: 702 case IMX8MQ: 703 case IMX8MQ_EP: 704 reset_control_assert(imx6_pcie->pciephy_reset); 705 fallthrough; 706 case IMX8MM: 707 case IMX8MM_EP: 708 case IMX8MP: 709 case IMX8MP_EP: 710 reset_control_assert(imx6_pcie->apps_reset); 711 break; 712 case IMX6SX: 713 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 714 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 715 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 716 /* Force PCIe PHY reset */ 717 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 718 IMX6SX_GPR5_PCIE_BTNRST_RESET, 719 IMX6SX_GPR5_PCIE_BTNRST_RESET); 720 break; 721 case IMX6QP: 722 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 723 IMX6Q_GPR1_PCIE_SW_RST, 724 IMX6Q_GPR1_PCIE_SW_RST); 725 break; 726 case IMX6Q: 727 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 728 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 729 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 730 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 731 break; 732 } 733 734 /* Some boards don't have PCIe reset GPIO. */ 735 if (gpio_is_valid(imx6_pcie->reset_gpio)) 736 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 737 imx6_pcie->gpio_active_high); 738 } 739 740 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 741 { 742 struct dw_pcie *pci = imx6_pcie->pci; 743 struct device *dev = pci->dev; 744 745 switch (imx6_pcie->drvdata->variant) { 746 case IMX8MQ: 747 case IMX8MQ_EP: 748 reset_control_deassert(imx6_pcie->pciephy_reset); 749 break; 750 case IMX7D: 751 reset_control_deassert(imx6_pcie->pciephy_reset); 752 753 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 754 * oscillate, especially when cold. This turns off "Duty-cycle 755 * Corrector" and other mysterious undocumented things. 756 */ 757 if (likely(imx6_pcie->phy_base)) { 758 /* De-assert DCC_FB_EN */ 759 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 760 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 761 /* Assert RX_EQS and RX_EQS_SEL */ 762 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 763 | PCIE_PHY_CMN_REG24_RX_EQ, 764 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 765 /* Assert ATT_MODE */ 766 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 767 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 768 } else { 769 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 770 } 771 772 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 773 break; 774 case IMX6SX: 775 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 776 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 777 break; 778 case IMX6QP: 779 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 780 IMX6Q_GPR1_PCIE_SW_RST, 0); 781 782 usleep_range(200, 500); 783 break; 784 case IMX6Q: /* Nothing to do */ 785 case IMX8MM: 786 case IMX8MM_EP: 787 case IMX8MP: 788 case IMX8MP_EP: 789 break; 790 } 791 792 /* Some boards don't have PCIe reset GPIO. */ 793 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 794 msleep(100); 795 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 796 !imx6_pcie->gpio_active_high); 797 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 798 msleep(100); 799 } 800 801 return 0; 802 } 803 804 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 805 { 806 struct dw_pcie *pci = imx6_pcie->pci; 807 struct device *dev = pci->dev; 808 u32 tmp; 809 unsigned int retries; 810 811 for (retries = 0; retries < 200; retries++) { 812 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 813 /* Test if the speed change finished. */ 814 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 815 return 0; 816 usleep_range(100, 1000); 817 } 818 819 dev_err(dev, "Speed change timeout\n"); 820 return -ETIMEDOUT; 821 } 822 823 static void imx6_pcie_ltssm_enable(struct device *dev) 824 { 825 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 826 827 switch (imx6_pcie->drvdata->variant) { 828 case IMX6Q: 829 case IMX6SX: 830 case IMX6QP: 831 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 832 IMX6Q_GPR12_PCIE_CTL_2, 833 IMX6Q_GPR12_PCIE_CTL_2); 834 break; 835 case IMX7D: 836 case IMX8MQ: 837 case IMX8MQ_EP: 838 case IMX8MM: 839 case IMX8MM_EP: 840 case IMX8MP: 841 case IMX8MP_EP: 842 reset_control_deassert(imx6_pcie->apps_reset); 843 break; 844 } 845 } 846 847 static void imx6_pcie_ltssm_disable(struct device *dev) 848 { 849 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 850 851 switch (imx6_pcie->drvdata->variant) { 852 case IMX6Q: 853 case IMX6SX: 854 case IMX6QP: 855 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 856 IMX6Q_GPR12_PCIE_CTL_2, 0); 857 break; 858 case IMX7D: 859 case IMX8MQ: 860 case IMX8MQ_EP: 861 case IMX8MM: 862 case IMX8MM_EP: 863 case IMX8MP: 864 case IMX8MP_EP: 865 reset_control_assert(imx6_pcie->apps_reset); 866 break; 867 } 868 } 869 870 static int imx6_pcie_start_link(struct dw_pcie *pci) 871 { 872 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 873 struct device *dev = pci->dev; 874 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 875 u32 tmp; 876 int ret; 877 878 /* 879 * Force Gen1 operation when starting the link. In case the link is 880 * started in Gen2 mode, there is a possibility the devices on the 881 * bus will not be detected at all. This happens with PCIe switches. 882 */ 883 dw_pcie_dbi_ro_wr_en(pci); 884 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 885 tmp &= ~PCI_EXP_LNKCAP_SLS; 886 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 887 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 888 dw_pcie_dbi_ro_wr_dis(pci); 889 890 /* Start LTSSM. */ 891 imx6_pcie_ltssm_enable(dev); 892 893 ret = dw_pcie_wait_for_link(pci); 894 if (ret) 895 goto err_reset_phy; 896 897 if (pci->link_gen > 1) { 898 /* Allow faster modes after the link is up */ 899 dw_pcie_dbi_ro_wr_en(pci); 900 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 901 tmp &= ~PCI_EXP_LNKCAP_SLS; 902 tmp |= pci->link_gen; 903 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 904 905 /* 906 * Start Directed Speed Change so the best possible 907 * speed both link partners support can be negotiated. 908 */ 909 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 910 tmp |= PORT_LOGIC_SPEED_CHANGE; 911 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 912 dw_pcie_dbi_ro_wr_dis(pci); 913 914 if (imx6_pcie->drvdata->flags & 915 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 916 /* 917 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 918 * from i.MX6 family when no link speed transition 919 * occurs and we go Gen1 -> yep, Gen1. The difference 920 * is that, in such case, it will not be cleared by HW 921 * which will cause the following code to report false 922 * failure. 923 */ 924 925 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 926 if (ret) { 927 dev_err(dev, "Failed to bring link up!\n"); 928 goto err_reset_phy; 929 } 930 } 931 932 /* Make sure link training is finished as well! */ 933 ret = dw_pcie_wait_for_link(pci); 934 if (ret) 935 goto err_reset_phy; 936 } else { 937 dev_info(dev, "Link: Only Gen1 is enabled\n"); 938 } 939 940 imx6_pcie->link_is_up = true; 941 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 942 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 943 return 0; 944 945 err_reset_phy: 946 imx6_pcie->link_is_up = false; 947 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 948 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 949 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 950 imx6_pcie_reset_phy(imx6_pcie); 951 return 0; 952 } 953 954 static void imx6_pcie_stop_link(struct dw_pcie *pci) 955 { 956 struct device *dev = pci->dev; 957 958 /* Turn off PCIe LTSSM */ 959 imx6_pcie_ltssm_disable(dev); 960 } 961 962 static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 963 { 964 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 965 struct device *dev = pci->dev; 966 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 967 int ret; 968 969 if (imx6_pcie->vpcie) { 970 ret = regulator_enable(imx6_pcie->vpcie); 971 if (ret) { 972 dev_err(dev, "failed to enable vpcie regulator: %d\n", 973 ret); 974 return ret; 975 } 976 } 977 978 imx6_pcie_assert_core_reset(imx6_pcie); 979 imx6_pcie_init_phy(imx6_pcie); 980 981 ret = imx6_pcie_clk_enable(imx6_pcie); 982 if (ret) { 983 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 984 goto err_reg_disable; 985 } 986 987 if (imx6_pcie->phy) { 988 ret = phy_init(imx6_pcie->phy); 989 if (ret) { 990 dev_err(dev, "pcie PHY power up failed\n"); 991 goto err_clk_disable; 992 } 993 } 994 995 if (imx6_pcie->phy) { 996 ret = phy_power_on(imx6_pcie->phy); 997 if (ret) { 998 dev_err(dev, "waiting for PHY ready timeout!\n"); 999 goto err_phy_off; 1000 } 1001 } 1002 1003 ret = imx6_pcie_deassert_core_reset(imx6_pcie); 1004 if (ret < 0) { 1005 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 1006 goto err_phy_off; 1007 } 1008 1009 imx6_setup_phy_mpll(imx6_pcie); 1010 1011 return 0; 1012 1013 err_phy_off: 1014 if (imx6_pcie->phy) 1015 phy_exit(imx6_pcie->phy); 1016 err_clk_disable: 1017 imx6_pcie_clk_disable(imx6_pcie); 1018 err_reg_disable: 1019 if (imx6_pcie->vpcie) 1020 regulator_disable(imx6_pcie->vpcie); 1021 return ret; 1022 } 1023 1024 static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 1025 { 1026 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1027 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1028 1029 if (imx6_pcie->phy) { 1030 if (phy_power_off(imx6_pcie->phy)) 1031 dev_err(pci->dev, "unable to power off PHY\n"); 1032 phy_exit(imx6_pcie->phy); 1033 } 1034 imx6_pcie_clk_disable(imx6_pcie); 1035 1036 if (imx6_pcie->vpcie) 1037 regulator_disable(imx6_pcie->vpcie); 1038 } 1039 1040 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 1041 .host_init = imx6_pcie_host_init, 1042 }; 1043 1044 static const struct dw_pcie_ops dw_pcie_ops = { 1045 .start_link = imx6_pcie_start_link, 1046 .stop_link = imx6_pcie_stop_link, 1047 }; 1048 1049 static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) 1050 { 1051 enum pci_barno bar; 1052 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1053 1054 for (bar = BAR_0; bar <= BAR_5; bar++) 1055 dw_pcie_ep_reset_bar(pci, bar); 1056 } 1057 1058 static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1059 enum pci_epc_irq_type type, 1060 u16 interrupt_num) 1061 { 1062 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1063 1064 switch (type) { 1065 case PCI_EPC_IRQ_LEGACY: 1066 return dw_pcie_ep_raise_legacy_irq(ep, func_no); 1067 case PCI_EPC_IRQ_MSI: 1068 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 1069 case PCI_EPC_IRQ_MSIX: 1070 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 1071 default: 1072 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 1073 return -EINVAL; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static const struct pci_epc_features imx8m_pcie_epc_features = { 1080 .linkup_notifier = false, 1081 .msi_capable = true, 1082 .msix_capable = false, 1083 .reserved_bar = 1 << BAR_1 | 1 << BAR_3, 1084 .align = SZ_64K, 1085 }; 1086 1087 static const struct pci_epc_features* 1088 imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) 1089 { 1090 return &imx8m_pcie_epc_features; 1091 } 1092 1093 static const struct dw_pcie_ep_ops pcie_ep_ops = { 1094 .ep_init = imx6_pcie_ep_init, 1095 .raise_irq = imx6_pcie_ep_raise_irq, 1096 .get_features = imx6_pcie_ep_get_features, 1097 }; 1098 1099 static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, 1100 struct platform_device *pdev) 1101 { 1102 int ret; 1103 unsigned int pcie_dbi2_offset; 1104 struct dw_pcie_ep *ep; 1105 struct resource *res; 1106 struct dw_pcie *pci = imx6_pcie->pci; 1107 struct dw_pcie_rp *pp = &pci->pp; 1108 struct device *dev = pci->dev; 1109 1110 imx6_pcie_host_init(pp); 1111 ep = &pci->ep; 1112 ep->ops = &pcie_ep_ops; 1113 1114 switch (imx6_pcie->drvdata->variant) { 1115 case IMX8MQ_EP: 1116 case IMX8MM_EP: 1117 case IMX8MP_EP: 1118 pcie_dbi2_offset = SZ_1M; 1119 break; 1120 default: 1121 pcie_dbi2_offset = SZ_4K; 1122 break; 1123 } 1124 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; 1125 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 1126 if (!res) 1127 return -EINVAL; 1128 1129 ep->phys_base = res->start; 1130 ep->addr_size = resource_size(res); 1131 ep->page_size = SZ_64K; 1132 1133 ret = dw_pcie_ep_init(ep); 1134 if (ret) { 1135 dev_err(dev, "failed to initialize endpoint\n"); 1136 return ret; 1137 } 1138 /* Start LTSSM. */ 1139 imx6_pcie_ltssm_enable(dev); 1140 1141 return 0; 1142 } 1143 1144 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 1145 { 1146 struct device *dev = imx6_pcie->pci->dev; 1147 1148 /* Some variants have a turnoff reset in DT */ 1149 if (imx6_pcie->turnoff_reset) { 1150 reset_control_assert(imx6_pcie->turnoff_reset); 1151 reset_control_deassert(imx6_pcie->turnoff_reset); 1152 goto pm_turnoff_sleep; 1153 } 1154 1155 /* Others poke directly at IOMUXC registers */ 1156 switch (imx6_pcie->drvdata->variant) { 1157 case IMX6SX: 1158 case IMX6QP: 1159 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1160 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 1161 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 1162 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1163 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 1164 break; 1165 default: 1166 dev_err(dev, "PME_Turn_Off not implemented\n"); 1167 return; 1168 } 1169 1170 /* 1171 * Components with an upstream port must respond to 1172 * PME_Turn_Off with PME_TO_Ack but we can't check. 1173 * 1174 * The standard recommends a 1-10ms timeout after which to 1175 * proceed anyway as if acks were received. 1176 */ 1177 pm_turnoff_sleep: 1178 usleep_range(1000, 10000); 1179 } 1180 1181 static int imx6_pcie_suspend_noirq(struct device *dev) 1182 { 1183 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1184 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1185 1186 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1187 return 0; 1188 1189 imx6_pcie_pm_turnoff(imx6_pcie); 1190 imx6_pcie_stop_link(imx6_pcie->pci); 1191 imx6_pcie_host_exit(pp); 1192 1193 return 0; 1194 } 1195 1196 static int imx6_pcie_resume_noirq(struct device *dev) 1197 { 1198 int ret; 1199 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1200 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1201 1202 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1203 return 0; 1204 1205 ret = imx6_pcie_host_init(pp); 1206 if (ret) 1207 return ret; 1208 dw_pcie_setup_rc(pp); 1209 1210 if (imx6_pcie->link_is_up) 1211 imx6_pcie_start_link(imx6_pcie->pci); 1212 1213 return 0; 1214 } 1215 1216 static const struct dev_pm_ops imx6_pcie_pm_ops = { 1217 NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1218 imx6_pcie_resume_noirq) 1219 }; 1220 1221 static int imx6_pcie_probe(struct platform_device *pdev) 1222 { 1223 struct device *dev = &pdev->dev; 1224 struct dw_pcie *pci; 1225 struct imx6_pcie *imx6_pcie; 1226 struct device_node *np; 1227 struct resource *dbi_base; 1228 struct device_node *node = dev->of_node; 1229 int ret; 1230 u16 val; 1231 1232 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1233 if (!imx6_pcie) 1234 return -ENOMEM; 1235 1236 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1237 if (!pci) 1238 return -ENOMEM; 1239 1240 pci->dev = dev; 1241 pci->ops = &dw_pcie_ops; 1242 pci->pp.ops = &imx6_pcie_host_ops; 1243 1244 imx6_pcie->pci = pci; 1245 imx6_pcie->drvdata = of_device_get_match_data(dev); 1246 1247 /* Find the PHY if one is defined, only imx7d uses it */ 1248 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1249 if (np) { 1250 struct resource res; 1251 1252 ret = of_address_to_resource(np, 0, &res); 1253 if (ret) { 1254 dev_err(dev, "Unable to map PCIe PHY\n"); 1255 return ret; 1256 } 1257 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1258 if (IS_ERR(imx6_pcie->phy_base)) 1259 return PTR_ERR(imx6_pcie->phy_base); 1260 } 1261 1262 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1263 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); 1264 if (IS_ERR(pci->dbi_base)) 1265 return PTR_ERR(pci->dbi_base); 1266 1267 /* Fetch GPIOs */ 1268 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 1269 imx6_pcie->gpio_active_high = of_property_read_bool(node, 1270 "reset-gpio-active-high"); 1271 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 1272 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 1273 imx6_pcie->gpio_active_high ? 1274 GPIOF_OUT_INIT_HIGH : 1275 GPIOF_OUT_INIT_LOW, 1276 "PCIe reset"); 1277 if (ret) { 1278 dev_err(dev, "unable to get reset gpio\n"); 1279 return ret; 1280 } 1281 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 1282 return imx6_pcie->reset_gpio; 1283 } 1284 1285 /* Fetch clocks */ 1286 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); 1287 if (IS_ERR(imx6_pcie->pcie_bus)) 1288 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), 1289 "pcie_bus clock source missing or invalid\n"); 1290 1291 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); 1292 if (IS_ERR(imx6_pcie->pcie)) 1293 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), 1294 "pcie clock source missing or invalid\n"); 1295 1296 switch (imx6_pcie->drvdata->variant) { 1297 case IMX6SX: 1298 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 1299 "pcie_inbound_axi"); 1300 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) 1301 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), 1302 "pcie_inbound_axi clock missing or invalid\n"); 1303 break; 1304 case IMX8MQ: 1305 case IMX8MQ_EP: 1306 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1307 if (IS_ERR(imx6_pcie->pcie_aux)) 1308 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1309 "pcie_aux clock source missing or invalid\n"); 1310 fallthrough; 1311 case IMX7D: 1312 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1313 imx6_pcie->controller_id = 1; 1314 1315 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 1316 "pciephy"); 1317 if (IS_ERR(imx6_pcie->pciephy_reset)) { 1318 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 1319 return PTR_ERR(imx6_pcie->pciephy_reset); 1320 } 1321 1322 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1323 "apps"); 1324 if (IS_ERR(imx6_pcie->apps_reset)) { 1325 dev_err(dev, "Failed to get PCIE APPS reset control\n"); 1326 return PTR_ERR(imx6_pcie->apps_reset); 1327 } 1328 break; 1329 case IMX8MM: 1330 case IMX8MM_EP: 1331 case IMX8MP: 1332 case IMX8MP_EP: 1333 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1334 if (IS_ERR(imx6_pcie->pcie_aux)) 1335 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1336 "pcie_aux clock source missing or invalid\n"); 1337 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1338 "apps"); 1339 if (IS_ERR(imx6_pcie->apps_reset)) 1340 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 1341 "failed to get pcie apps reset control\n"); 1342 1343 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1344 if (IS_ERR(imx6_pcie->phy)) 1345 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 1346 "failed to get pcie phy\n"); 1347 1348 break; 1349 default: 1350 break; 1351 } 1352 /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */ 1353 if (imx6_pcie->phy == NULL) { 1354 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); 1355 if (IS_ERR(imx6_pcie->pcie_phy)) 1356 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), 1357 "pcie_phy clock source missing or invalid\n"); 1358 } 1359 1360 1361 /* Grab turnoff reset */ 1362 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1363 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1364 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1365 return PTR_ERR(imx6_pcie->turnoff_reset); 1366 } 1367 1368 /* Grab GPR config register range */ 1369 imx6_pcie->iomuxc_gpr = 1370 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); 1371 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1372 dev_err(dev, "unable to find iomuxc registers\n"); 1373 return PTR_ERR(imx6_pcie->iomuxc_gpr); 1374 } 1375 1376 /* Grab PCIe PHY Tx Settings */ 1377 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1378 &imx6_pcie->tx_deemph_gen1)) 1379 imx6_pcie->tx_deemph_gen1 = 0; 1380 1381 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1382 &imx6_pcie->tx_deemph_gen2_3p5db)) 1383 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1384 1385 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1386 &imx6_pcie->tx_deemph_gen2_6db)) 1387 imx6_pcie->tx_deemph_gen2_6db = 20; 1388 1389 if (of_property_read_u32(node, "fsl,tx-swing-full", 1390 &imx6_pcie->tx_swing_full)) 1391 imx6_pcie->tx_swing_full = 127; 1392 1393 if (of_property_read_u32(node, "fsl,tx-swing-low", 1394 &imx6_pcie->tx_swing_low)) 1395 imx6_pcie->tx_swing_low = 127; 1396 1397 /* Limit link speed */ 1398 pci->link_gen = 1; 1399 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1400 1401 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1402 if (IS_ERR(imx6_pcie->vpcie)) { 1403 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1404 return PTR_ERR(imx6_pcie->vpcie); 1405 imx6_pcie->vpcie = NULL; 1406 } 1407 1408 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1409 if (IS_ERR(imx6_pcie->vph)) { 1410 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1411 return PTR_ERR(imx6_pcie->vph); 1412 imx6_pcie->vph = NULL; 1413 } 1414 1415 platform_set_drvdata(pdev, imx6_pcie); 1416 1417 ret = imx6_pcie_attach_pd(dev); 1418 if (ret) 1419 return ret; 1420 1421 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 1422 ret = imx6_add_pcie_ep(imx6_pcie, pdev); 1423 if (ret < 0) 1424 return ret; 1425 } else { 1426 ret = dw_pcie_host_init(&pci->pp); 1427 if (ret < 0) 1428 return ret; 1429 1430 if (pci_msi_enabled()) { 1431 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1432 1433 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1434 val |= PCI_MSI_FLAGS_ENABLE; 1435 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1436 } 1437 } 1438 1439 return 0; 1440 } 1441 1442 static void imx6_pcie_shutdown(struct platform_device *pdev) 1443 { 1444 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1445 1446 /* bring down link, so bootloader gets clean state in case of reboot */ 1447 imx6_pcie_assert_core_reset(imx6_pcie); 1448 } 1449 1450 static const struct imx6_pcie_drvdata drvdata[] = { 1451 [IMX6Q] = { 1452 .variant = IMX6Q, 1453 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1454 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1455 .dbi_length = 0x200, 1456 .gpr = "fsl,imx6q-iomuxc-gpr", 1457 }, 1458 [IMX6SX] = { 1459 .variant = IMX6SX, 1460 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1461 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1462 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1463 .gpr = "fsl,imx6q-iomuxc-gpr", 1464 }, 1465 [IMX6QP] = { 1466 .variant = IMX6QP, 1467 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1468 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1469 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1470 .dbi_length = 0x200, 1471 .gpr = "fsl,imx6q-iomuxc-gpr", 1472 }, 1473 [IMX7D] = { 1474 .variant = IMX7D, 1475 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1476 .gpr = "fsl,imx7d-iomuxc-gpr", 1477 }, 1478 [IMX8MQ] = { 1479 .variant = IMX8MQ, 1480 .gpr = "fsl,imx8mq-iomuxc-gpr", 1481 }, 1482 [IMX8MM] = { 1483 .variant = IMX8MM, 1484 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1485 .gpr = "fsl,imx8mm-iomuxc-gpr", 1486 }, 1487 [IMX8MP] = { 1488 .variant = IMX8MP, 1489 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1490 .gpr = "fsl,imx8mp-iomuxc-gpr", 1491 }, 1492 [IMX8MQ_EP] = { 1493 .variant = IMX8MQ_EP, 1494 .mode = DW_PCIE_EP_TYPE, 1495 .gpr = "fsl,imx8mq-iomuxc-gpr", 1496 }, 1497 [IMX8MM_EP] = { 1498 .variant = IMX8MM_EP, 1499 .mode = DW_PCIE_EP_TYPE, 1500 .gpr = "fsl,imx8mm-iomuxc-gpr", 1501 }, 1502 [IMX8MP_EP] = { 1503 .variant = IMX8MP_EP, 1504 .mode = DW_PCIE_EP_TYPE, 1505 .gpr = "fsl,imx8mp-iomuxc-gpr", 1506 }, 1507 }; 1508 1509 static const struct of_device_id imx6_pcie_of_match[] = { 1510 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1511 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1512 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1513 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1514 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1515 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 1516 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, 1517 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, 1518 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, 1519 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, 1520 {}, 1521 }; 1522 1523 static struct platform_driver imx6_pcie_driver = { 1524 .driver = { 1525 .name = "imx6q-pcie", 1526 .of_match_table = imx6_pcie_of_match, 1527 .suppress_bind_attrs = true, 1528 .pm = &imx6_pcie_pm_ops, 1529 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1530 }, 1531 .probe = imx6_pcie_probe, 1532 .shutdown = imx6_pcie_shutdown, 1533 }; 1534 1535 static void imx6_pcie_quirk(struct pci_dev *dev) 1536 { 1537 struct pci_bus *bus = dev->bus; 1538 struct dw_pcie_rp *pp = bus->sysdata; 1539 1540 /* Bus parent is the PCI bridge, its parent is this platform driver */ 1541 if (!bus->dev.parent || !bus->dev.parent->parent) 1542 return; 1543 1544 /* Make sure we only quirk devices associated with this driver */ 1545 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1546 return; 1547 1548 if (pci_is_root_bus(bus)) { 1549 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1550 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1551 1552 /* 1553 * Limit config length to avoid the kernel reading beyond 1554 * the register set and causing an abort on i.MX 6Quad 1555 */ 1556 if (imx6_pcie->drvdata->dbi_length) { 1557 dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1558 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1559 dev->cfg_size); 1560 } 1561 } 1562 } 1563 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1564 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1565 1566 static int __init imx6_pcie_init(void) 1567 { 1568 #ifdef CONFIG_ARM 1569 /* 1570 * Since probe() can be deferred we need to make sure that 1571 * hook_fault_code is not called after __init memory is freed 1572 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1573 * we can install the handler here without risking it 1574 * accessing some uninitialized driver state. 1575 */ 1576 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1577 "external abort on non-linefetch"); 1578 #endif 1579 1580 return platform_driver_register(&imx6_pcie_driver); 1581 } 1582 device_initcall(imx6_pcie_init); 1583