1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * http://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19 #include <linux/module.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_device.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 #include <linux/types.h> 30 #include <linux/interrupt.h> 31 #include <linux/reset.h> 32 #include <linux/pm_domain.h> 33 #include <linux/pm_runtime.h> 34 35 #include "pcie-designware.h" 36 37 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 38 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 40 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 41 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 42 43 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 44 45 enum imx6_pcie_variants { 46 IMX6Q, 47 IMX6SX, 48 IMX6QP, 49 IMX7D, 50 IMX8MQ, 51 }; 52 53 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 54 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 55 56 struct imx6_pcie_drvdata { 57 enum imx6_pcie_variants variant; 58 u32 flags; 59 }; 60 61 struct imx6_pcie { 62 struct dw_pcie *pci; 63 int reset_gpio; 64 bool gpio_active_high; 65 struct clk *pcie_bus; 66 struct clk *pcie_phy; 67 struct clk *pcie_inbound_axi; 68 struct clk *pcie; 69 struct clk *pcie_aux; 70 struct regmap *iomuxc_gpr; 71 u32 controller_id; 72 struct reset_control *pciephy_reset; 73 struct reset_control *apps_reset; 74 struct reset_control *turnoff_reset; 75 u32 tx_deemph_gen1; 76 u32 tx_deemph_gen2_3p5db; 77 u32 tx_deemph_gen2_6db; 78 u32 tx_swing_full; 79 u32 tx_swing_low; 80 int link_gen; 81 struct regulator *vpcie; 82 void __iomem *phy_base; 83 84 /* power domain for pcie */ 85 struct device *pd_pcie; 86 /* power domain for pcie phy */ 87 struct device *pd_pcie_phy; 88 const struct imx6_pcie_drvdata *drvdata; 89 }; 90 91 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 92 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000 93 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50 94 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 95 96 /* PCIe Root Complex registers (memory-mapped) */ 97 #define PCIE_RC_IMX6_MSI_CAP 0x50 98 #define PCIE_RC_LCR 0x7c 99 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 100 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 101 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf 102 103 #define PCIE_RC_LCSR 0x80 104 105 /* PCIe Port Logic registers (memory-mapped) */ 106 #define PL_OFFSET 0x700 107 #define PCIE_PL_PFLR (PL_OFFSET + 0x08) 108 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) 109 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) 110 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) 111 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) 112 113 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 114 #define PCIE_PHY_CTRL_DATA_LOC 0 115 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 116 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 117 #define PCIE_PHY_CTRL_WR_LOC 18 118 #define PCIE_PHY_CTRL_RD_LOC 19 119 120 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 121 #define PCIE_PHY_STAT_ACK_LOC 16 122 123 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 124 125 /* PHY registers (not memory-mapped) */ 126 #define PCIE_PHY_ATEOVRD 0x10 127 #define PCIE_PHY_ATEOVRD_EN (0x1 << 2) 128 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 129 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 130 131 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 132 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 133 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 134 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD (0x1 << 9) 135 136 #define PCIE_PHY_RX_ASIC_OUT 0x100D 137 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 138 139 /* iMX7 PCIe PHY registers */ 140 #define PCIE_PHY_CMN_REG4 0x14 141 /* These are probably the bits that *aren't* DCC_FB_EN */ 142 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 143 144 #define PCIE_PHY_CMN_REG15 0x54 145 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 146 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 147 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 148 149 #define PCIE_PHY_CMN_REG24 0x90 150 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 151 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 152 153 #define PCIE_PHY_CMN_REG26 0x98 154 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 155 156 #define PHY_RX_OVRD_IN_LO 0x1005 157 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) 158 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) 159 160 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) 161 { 162 struct dw_pcie *pci = imx6_pcie->pci; 163 u32 val; 164 u32 max_iterations = 10; 165 u32 wait_counter = 0; 166 167 do { 168 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 169 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 170 wait_counter++; 171 172 if (val == exp_val) 173 return 0; 174 175 udelay(1); 176 } while (wait_counter < max_iterations); 177 178 return -ETIMEDOUT; 179 } 180 181 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 182 { 183 struct dw_pcie *pci = imx6_pcie->pci; 184 u32 val; 185 int ret; 186 187 val = addr << PCIE_PHY_CTRL_DATA_LOC; 188 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 189 190 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 191 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 192 193 ret = pcie_phy_poll_ack(imx6_pcie, 1); 194 if (ret) 195 return ret; 196 197 val = addr << PCIE_PHY_CTRL_DATA_LOC; 198 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 199 200 return pcie_phy_poll_ack(imx6_pcie, 0); 201 } 202 203 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 204 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) 205 { 206 struct dw_pcie *pci = imx6_pcie->pci; 207 u32 val, phy_ctl; 208 int ret; 209 210 ret = pcie_phy_wait_ack(imx6_pcie, addr); 211 if (ret) 212 return ret; 213 214 /* assert Read signal */ 215 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 216 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 217 218 ret = pcie_phy_poll_ack(imx6_pcie, 1); 219 if (ret) 220 return ret; 221 222 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 223 *data = val & 0xffff; 224 225 /* deassert Read signal */ 226 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 227 228 return pcie_phy_poll_ack(imx6_pcie, 0); 229 } 230 231 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) 232 { 233 struct dw_pcie *pci = imx6_pcie->pci; 234 u32 var; 235 int ret; 236 237 /* write addr */ 238 /* cap addr */ 239 ret = pcie_phy_wait_ack(imx6_pcie, addr); 240 if (ret) 241 return ret; 242 243 var = data << PCIE_PHY_CTRL_DATA_LOC; 244 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 245 246 /* capture data */ 247 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 248 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 249 250 ret = pcie_phy_poll_ack(imx6_pcie, 1); 251 if (ret) 252 return ret; 253 254 /* deassert cap data */ 255 var = data << PCIE_PHY_CTRL_DATA_LOC; 256 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 257 258 /* wait for ack de-assertion */ 259 ret = pcie_phy_poll_ack(imx6_pcie, 0); 260 if (ret) 261 return ret; 262 263 /* assert wr signal */ 264 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 265 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 266 267 /* wait for ack */ 268 ret = pcie_phy_poll_ack(imx6_pcie, 1); 269 if (ret) 270 return ret; 271 272 /* deassert wr signal */ 273 var = data << PCIE_PHY_CTRL_DATA_LOC; 274 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 275 276 /* wait for ack de-assertion */ 277 ret = pcie_phy_poll_ack(imx6_pcie, 0); 278 if (ret) 279 return ret; 280 281 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 282 283 return 0; 284 } 285 286 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 287 { 288 u32 tmp; 289 290 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 291 return; 292 293 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 294 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 295 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 296 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 297 298 usleep_range(2000, 3000); 299 300 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 301 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 302 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 303 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 304 } 305 306 #ifdef CONFIG_ARM 307 /* Added for PCI abort handling */ 308 static int imx6q_pcie_abort_handler(unsigned long addr, 309 unsigned int fsr, struct pt_regs *regs) 310 { 311 unsigned long pc = instruction_pointer(regs); 312 unsigned long instr = *(unsigned long *)pc; 313 int reg = (instr >> 12) & 15; 314 315 /* 316 * If the instruction being executed was a read, 317 * make it look like it read all-ones. 318 */ 319 if ((instr & 0x0c100000) == 0x04100000) { 320 unsigned long val; 321 322 if (instr & 0x00400000) 323 val = 255; 324 else 325 val = -1; 326 327 regs->uregs[reg] = val; 328 regs->ARM_pc += 4; 329 return 0; 330 } 331 332 if ((instr & 0x0e100090) == 0x00100090) { 333 regs->uregs[reg] = -1; 334 regs->ARM_pc += 4; 335 return 0; 336 } 337 338 return 1; 339 } 340 #endif 341 342 static int imx6_pcie_attach_pd(struct device *dev) 343 { 344 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 345 struct device_link *link; 346 347 /* Do nothing when in a single power domain */ 348 if (dev->pm_domain) 349 return 0; 350 351 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 352 if (IS_ERR(imx6_pcie->pd_pcie)) 353 return PTR_ERR(imx6_pcie->pd_pcie); 354 /* Do nothing when power domain missing */ 355 if (!imx6_pcie->pd_pcie) 356 return 0; 357 link = device_link_add(dev, imx6_pcie->pd_pcie, 358 DL_FLAG_STATELESS | 359 DL_FLAG_PM_RUNTIME | 360 DL_FLAG_RPM_ACTIVE); 361 if (!link) { 362 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 363 return -EINVAL; 364 } 365 366 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 367 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 368 return PTR_ERR(imx6_pcie->pd_pcie_phy); 369 370 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 371 DL_FLAG_STATELESS | 372 DL_FLAG_PM_RUNTIME | 373 DL_FLAG_RPM_ACTIVE); 374 if (!link) { 375 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 376 return -EINVAL; 377 } 378 379 return 0; 380 } 381 382 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 383 { 384 struct device *dev = imx6_pcie->pci->dev; 385 386 switch (imx6_pcie->drvdata->variant) { 387 case IMX7D: 388 case IMX8MQ: 389 reset_control_assert(imx6_pcie->pciephy_reset); 390 reset_control_assert(imx6_pcie->apps_reset); 391 break; 392 case IMX6SX: 393 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 394 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 395 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 396 /* Force PCIe PHY reset */ 397 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 398 IMX6SX_GPR5_PCIE_BTNRST_RESET, 399 IMX6SX_GPR5_PCIE_BTNRST_RESET); 400 break; 401 case IMX6QP: 402 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 403 IMX6Q_GPR1_PCIE_SW_RST, 404 IMX6Q_GPR1_PCIE_SW_RST); 405 break; 406 case IMX6Q: 407 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 408 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 409 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 410 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 411 break; 412 } 413 414 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { 415 int ret = regulator_disable(imx6_pcie->vpcie); 416 417 if (ret) 418 dev_err(dev, "failed to disable vpcie regulator: %d\n", 419 ret); 420 } 421 } 422 423 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 424 { 425 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ); 426 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 427 } 428 429 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 430 { 431 struct dw_pcie *pci = imx6_pcie->pci; 432 struct device *dev = pci->dev; 433 unsigned int offset; 434 int ret = 0; 435 436 switch (imx6_pcie->drvdata->variant) { 437 case IMX6SX: 438 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 439 if (ret) { 440 dev_err(dev, "unable to enable pcie_axi clock\n"); 441 break; 442 } 443 444 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 445 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 446 break; 447 case IMX6QP: /* FALLTHROUGH */ 448 case IMX6Q: 449 /* power up core phy and enable ref clock */ 450 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 451 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 452 /* 453 * the async reset input need ref clock to sync internally, 454 * when the ref clock comes after reset, internal synced 455 * reset time is too short, cannot meet the requirement. 456 * add one ~10us delay here. 457 */ 458 udelay(10); 459 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 460 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 461 break; 462 case IMX7D: 463 break; 464 case IMX8MQ: 465 ret = clk_prepare_enable(imx6_pcie->pcie_aux); 466 if (ret) { 467 dev_err(dev, "unable to enable pcie_aux clock\n"); 468 break; 469 } 470 471 offset = imx6_pcie_grp_offset(imx6_pcie); 472 /* 473 * Set the over ride low and enabled 474 * make sure that REF_CLK is turned on. 475 */ 476 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 477 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 478 0); 479 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 480 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 481 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 482 break; 483 } 484 485 return ret; 486 } 487 488 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 489 { 490 u32 val; 491 unsigned int retries; 492 struct device *dev = imx6_pcie->pci->dev; 493 494 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) { 495 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val); 496 497 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED) 498 return; 499 500 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN, 501 PHY_PLL_LOCK_WAIT_USLEEP_MAX); 502 } 503 504 dev_err(dev, "PCIe PLL lock timeout\n"); 505 } 506 507 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 508 { 509 struct dw_pcie *pci = imx6_pcie->pci; 510 struct device *dev = pci->dev; 511 int ret; 512 513 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { 514 ret = regulator_enable(imx6_pcie->vpcie); 515 if (ret) { 516 dev_err(dev, "failed to enable vpcie regulator: %d\n", 517 ret); 518 return; 519 } 520 } 521 522 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 523 if (ret) { 524 dev_err(dev, "unable to enable pcie_phy clock\n"); 525 goto err_pcie_phy; 526 } 527 528 ret = clk_prepare_enable(imx6_pcie->pcie_bus); 529 if (ret) { 530 dev_err(dev, "unable to enable pcie_bus clock\n"); 531 goto err_pcie_bus; 532 } 533 534 ret = clk_prepare_enable(imx6_pcie->pcie); 535 if (ret) { 536 dev_err(dev, "unable to enable pcie clock\n"); 537 goto err_pcie; 538 } 539 540 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 541 if (ret) { 542 dev_err(dev, "unable to enable pcie ref clock\n"); 543 goto err_ref_clk; 544 } 545 546 /* allow the clocks to stabilize */ 547 usleep_range(200, 500); 548 549 /* Some boards don't have PCIe reset GPIO. */ 550 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 551 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 552 imx6_pcie->gpio_active_high); 553 msleep(100); 554 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 555 !imx6_pcie->gpio_active_high); 556 } 557 558 switch (imx6_pcie->drvdata->variant) { 559 case IMX8MQ: 560 reset_control_deassert(imx6_pcie->pciephy_reset); 561 break; 562 case IMX7D: 563 reset_control_deassert(imx6_pcie->pciephy_reset); 564 565 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 566 * oscillate, especially when cold. This turns off "Duty-cycle 567 * Corrector" and other mysterious undocumented things. 568 */ 569 if (likely(imx6_pcie->phy_base)) { 570 /* De-assert DCC_FB_EN */ 571 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 572 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 573 /* Assert RX_EQS and RX_EQS_SEL */ 574 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 575 | PCIE_PHY_CMN_REG24_RX_EQ, 576 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 577 /* Assert ATT_MODE */ 578 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 579 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 580 } else { 581 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 582 } 583 584 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 585 break; 586 case IMX6SX: 587 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 588 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 589 break; 590 case IMX6QP: 591 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 592 IMX6Q_GPR1_PCIE_SW_RST, 0); 593 594 usleep_range(200, 500); 595 break; 596 case IMX6Q: /* Nothing to do */ 597 break; 598 } 599 600 return; 601 602 err_ref_clk: 603 clk_disable_unprepare(imx6_pcie->pcie); 604 err_pcie: 605 clk_disable_unprepare(imx6_pcie->pcie_bus); 606 err_pcie_bus: 607 clk_disable_unprepare(imx6_pcie->pcie_phy); 608 err_pcie_phy: 609 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { 610 ret = regulator_disable(imx6_pcie->vpcie); 611 if (ret) 612 dev_err(dev, "failed to disable vpcie regulator: %d\n", 613 ret); 614 } 615 } 616 617 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 618 { 619 unsigned int mask, val; 620 621 if (imx6_pcie->drvdata->variant == IMX8MQ && 622 imx6_pcie->controller_id == 1) { 623 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; 624 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 625 PCI_EXP_TYPE_ROOT_PORT); 626 } else { 627 mask = IMX6Q_GPR12_DEVICE_TYPE; 628 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, 629 PCI_EXP_TYPE_ROOT_PORT); 630 } 631 632 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); 633 } 634 635 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 636 { 637 switch (imx6_pcie->drvdata->variant) { 638 case IMX8MQ: 639 /* 640 * TODO: Currently this code assumes external 641 * oscillator is being used 642 */ 643 regmap_update_bits(imx6_pcie->iomuxc_gpr, 644 imx6_pcie_grp_offset(imx6_pcie), 645 IMX8MQ_GPR_PCIE_REF_USE_PAD, 646 IMX8MQ_GPR_PCIE_REF_USE_PAD); 647 break; 648 case IMX7D: 649 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 650 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 651 break; 652 case IMX6SX: 653 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 654 IMX6SX_GPR12_PCIE_RX_EQ_MASK, 655 IMX6SX_GPR12_PCIE_RX_EQ_2); 656 /* FALLTHROUGH */ 657 default: 658 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 659 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 660 661 /* configure constant input signal to the pcie ctrl and phy */ 662 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 663 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 664 665 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 666 IMX6Q_GPR8_TX_DEEMPH_GEN1, 667 imx6_pcie->tx_deemph_gen1 << 0); 668 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 669 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 670 imx6_pcie->tx_deemph_gen2_3p5db << 6); 671 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 672 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 673 imx6_pcie->tx_deemph_gen2_6db << 12); 674 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 675 IMX6Q_GPR8_TX_SWING_FULL, 676 imx6_pcie->tx_swing_full << 18); 677 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 678 IMX6Q_GPR8_TX_SWING_LOW, 679 imx6_pcie->tx_swing_low << 25); 680 break; 681 } 682 683 imx6_pcie_configure_type(imx6_pcie); 684 } 685 686 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 687 { 688 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); 689 int mult, div; 690 u32 val; 691 692 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 693 return 0; 694 695 switch (phy_rate) { 696 case 125000000: 697 /* 698 * The default settings of the MPLL are for a 125MHz input 699 * clock, so no need to reconfigure anything in that case. 700 */ 701 return 0; 702 case 100000000: 703 mult = 25; 704 div = 0; 705 break; 706 case 200000000: 707 mult = 25; 708 div = 1; 709 break; 710 default: 711 dev_err(imx6_pcie->pci->dev, 712 "Unsupported PHY reference clock rate %lu\n", phy_rate); 713 return -EINVAL; 714 } 715 716 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 717 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 718 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 719 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 720 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 721 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 722 723 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 724 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 725 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 726 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 727 val |= PCIE_PHY_ATEOVRD_EN; 728 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 729 730 return 0; 731 } 732 733 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) 734 { 735 struct dw_pcie *pci = imx6_pcie->pci; 736 struct device *dev = pci->dev; 737 738 /* check if the link is up or not */ 739 if (!dw_pcie_wait_for_link(pci)) 740 return 0; 741 742 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 743 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 744 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 745 return -ETIMEDOUT; 746 } 747 748 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 749 { 750 struct dw_pcie *pci = imx6_pcie->pci; 751 struct device *dev = pci->dev; 752 u32 tmp; 753 unsigned int retries; 754 755 for (retries = 0; retries < 200; retries++) { 756 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 757 /* Test if the speed change finished. */ 758 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 759 return 0; 760 usleep_range(100, 1000); 761 } 762 763 dev_err(dev, "Speed change timeout\n"); 764 return -EINVAL; 765 } 766 767 static void imx6_pcie_ltssm_enable(struct device *dev) 768 { 769 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 770 771 switch (imx6_pcie->drvdata->variant) { 772 case IMX6Q: 773 case IMX6SX: 774 case IMX6QP: 775 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 776 IMX6Q_GPR12_PCIE_CTL_2, 777 IMX6Q_GPR12_PCIE_CTL_2); 778 break; 779 case IMX7D: 780 case IMX8MQ: 781 reset_control_deassert(imx6_pcie->apps_reset); 782 break; 783 } 784 } 785 786 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 787 { 788 struct dw_pcie *pci = imx6_pcie->pci; 789 struct device *dev = pci->dev; 790 u32 tmp; 791 int ret; 792 793 /* 794 * Force Gen1 operation when starting the link. In case the link is 795 * started in Gen2 mode, there is a possibility the devices on the 796 * bus will not be detected at all. This happens with PCIe switches. 797 */ 798 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); 799 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 800 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; 801 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); 802 803 /* Start LTSSM. */ 804 imx6_pcie_ltssm_enable(dev); 805 806 ret = imx6_pcie_wait_for_link(imx6_pcie); 807 if (ret) 808 goto err_reset_phy; 809 810 if (imx6_pcie->link_gen == 2) { 811 /* Allow Gen2 mode after the link is up. */ 812 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); 813 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 814 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; 815 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); 816 817 /* 818 * Start Directed Speed Change so the best possible 819 * speed both link partners support can be negotiated. 820 */ 821 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 822 tmp |= PORT_LOGIC_SPEED_CHANGE; 823 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 824 825 if (imx6_pcie->drvdata->flags & 826 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 827 /* 828 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 829 * from i.MX6 family when no link speed transition 830 * occurs and we go Gen1 -> yep, Gen1. The difference 831 * is that, in such case, it will not be cleared by HW 832 * which will cause the following code to report false 833 * failure. 834 */ 835 836 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 837 if (ret) { 838 dev_err(dev, "Failed to bring link up!\n"); 839 goto err_reset_phy; 840 } 841 } 842 843 /* Make sure link training is finished as well! */ 844 ret = imx6_pcie_wait_for_link(imx6_pcie); 845 if (ret) { 846 dev_err(dev, "Failed to bring link up!\n"); 847 goto err_reset_phy; 848 } 849 } else { 850 dev_info(dev, "Link: Gen2 disabled\n"); 851 } 852 853 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR); 854 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); 855 return 0; 856 857 err_reset_phy: 858 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 859 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 860 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 861 imx6_pcie_reset_phy(imx6_pcie); 862 return ret; 863 } 864 865 static int imx6_pcie_host_init(struct pcie_port *pp) 866 { 867 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 868 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 869 870 imx6_pcie_assert_core_reset(imx6_pcie); 871 imx6_pcie_init_phy(imx6_pcie); 872 imx6_pcie_deassert_core_reset(imx6_pcie); 873 imx6_setup_phy_mpll(imx6_pcie); 874 dw_pcie_setup_rc(pp); 875 imx6_pcie_establish_link(imx6_pcie); 876 877 if (IS_ENABLED(CONFIG_PCI_MSI)) 878 dw_pcie_msi_init(pp); 879 880 return 0; 881 } 882 883 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 884 .host_init = imx6_pcie_host_init, 885 }; 886 887 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, 888 struct platform_device *pdev) 889 { 890 struct dw_pcie *pci = imx6_pcie->pci; 891 struct pcie_port *pp = &pci->pp; 892 struct device *dev = &pdev->dev; 893 int ret; 894 895 if (IS_ENABLED(CONFIG_PCI_MSI)) { 896 pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 897 if (pp->msi_irq <= 0) { 898 dev_err(dev, "failed to get MSI irq\n"); 899 return -ENODEV; 900 } 901 } 902 903 pp->ops = &imx6_pcie_host_ops; 904 905 ret = dw_pcie_host_init(pp); 906 if (ret) { 907 dev_err(dev, "failed to initialize host\n"); 908 return ret; 909 } 910 911 return 0; 912 } 913 914 static const struct dw_pcie_ops dw_pcie_ops = { 915 /* No special ops needed, but pcie-designware still expects this struct */ 916 }; 917 918 #ifdef CONFIG_PM_SLEEP 919 static void imx6_pcie_ltssm_disable(struct device *dev) 920 { 921 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 922 923 switch (imx6_pcie->drvdata->variant) { 924 case IMX6SX: 925 case IMX6QP: 926 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 927 IMX6Q_GPR12_PCIE_CTL_2, 0); 928 break; 929 case IMX7D: 930 reset_control_assert(imx6_pcie->apps_reset); 931 break; 932 default: 933 dev_err(dev, "ltssm_disable not supported\n"); 934 } 935 } 936 937 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 938 { 939 struct device *dev = imx6_pcie->pci->dev; 940 941 /* Some variants have a turnoff reset in DT */ 942 if (imx6_pcie->turnoff_reset) { 943 reset_control_assert(imx6_pcie->turnoff_reset); 944 reset_control_deassert(imx6_pcie->turnoff_reset); 945 goto pm_turnoff_sleep; 946 } 947 948 /* Others poke directly at IOMUXC registers */ 949 switch (imx6_pcie->drvdata->variant) { 950 case IMX6SX: 951 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 952 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 953 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 954 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 955 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 956 break; 957 default: 958 dev_err(dev, "PME_Turn_Off not implemented\n"); 959 return; 960 } 961 962 /* 963 * Components with an upstream port must respond to 964 * PME_Turn_Off with PME_TO_Ack but we can't check. 965 * 966 * The standard recommends a 1-10ms timeout after which to 967 * proceed anyway as if acks were received. 968 */ 969 pm_turnoff_sleep: 970 usleep_range(1000, 10000); 971 } 972 973 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 974 { 975 clk_disable_unprepare(imx6_pcie->pcie); 976 clk_disable_unprepare(imx6_pcie->pcie_phy); 977 clk_disable_unprepare(imx6_pcie->pcie_bus); 978 979 switch (imx6_pcie->drvdata->variant) { 980 case IMX6SX: 981 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 982 break; 983 case IMX7D: 984 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 985 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 986 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 987 break; 988 case IMX8MQ: 989 clk_disable_unprepare(imx6_pcie->pcie_aux); 990 break; 991 default: 992 break; 993 } 994 } 995 996 static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie) 997 { 998 return (imx6_pcie->drvdata->variant == IMX7D || 999 imx6_pcie->drvdata->variant == IMX6SX); 1000 } 1001 1002 static int imx6_pcie_suspend_noirq(struct device *dev) 1003 { 1004 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1005 1006 if (!imx6_pcie_supports_suspend(imx6_pcie)) 1007 return 0; 1008 1009 imx6_pcie_pm_turnoff(imx6_pcie); 1010 imx6_pcie_clk_disable(imx6_pcie); 1011 imx6_pcie_ltssm_disable(dev); 1012 1013 return 0; 1014 } 1015 1016 static int imx6_pcie_resume_noirq(struct device *dev) 1017 { 1018 int ret; 1019 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1020 struct pcie_port *pp = &imx6_pcie->pci->pp; 1021 1022 if (!imx6_pcie_supports_suspend(imx6_pcie)) 1023 return 0; 1024 1025 imx6_pcie_assert_core_reset(imx6_pcie); 1026 imx6_pcie_init_phy(imx6_pcie); 1027 imx6_pcie_deassert_core_reset(imx6_pcie); 1028 dw_pcie_setup_rc(pp); 1029 1030 ret = imx6_pcie_establish_link(imx6_pcie); 1031 if (ret < 0) 1032 dev_info(dev, "pcie link is down after resume.\n"); 1033 1034 return 0; 1035 } 1036 #endif 1037 1038 static const struct dev_pm_ops imx6_pcie_pm_ops = { 1039 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1040 imx6_pcie_resume_noirq) 1041 }; 1042 1043 static int imx6_pcie_probe(struct platform_device *pdev) 1044 { 1045 struct device *dev = &pdev->dev; 1046 struct dw_pcie *pci; 1047 struct imx6_pcie *imx6_pcie; 1048 struct device_node *np; 1049 struct resource *dbi_base; 1050 struct device_node *node = dev->of_node; 1051 int ret; 1052 u16 val; 1053 1054 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1055 if (!imx6_pcie) 1056 return -ENOMEM; 1057 1058 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1059 if (!pci) 1060 return -ENOMEM; 1061 1062 pci->dev = dev; 1063 pci->ops = &dw_pcie_ops; 1064 1065 imx6_pcie->pci = pci; 1066 imx6_pcie->drvdata = of_device_get_match_data(dev); 1067 1068 /* Find the PHY if one is defined, only imx7d uses it */ 1069 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1070 if (np) { 1071 struct resource res; 1072 1073 ret = of_address_to_resource(np, 0, &res); 1074 if (ret) { 1075 dev_err(dev, "Unable to map PCIe PHY\n"); 1076 return ret; 1077 } 1078 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1079 if (IS_ERR(imx6_pcie->phy_base)) { 1080 dev_err(dev, "Unable to map PCIe PHY\n"); 1081 return PTR_ERR(imx6_pcie->phy_base); 1082 } 1083 } 1084 1085 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1086 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); 1087 if (IS_ERR(pci->dbi_base)) 1088 return PTR_ERR(pci->dbi_base); 1089 1090 /* Fetch GPIOs */ 1091 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 1092 imx6_pcie->gpio_active_high = of_property_read_bool(node, 1093 "reset-gpio-active-high"); 1094 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 1095 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 1096 imx6_pcie->gpio_active_high ? 1097 GPIOF_OUT_INIT_HIGH : 1098 GPIOF_OUT_INIT_LOW, 1099 "PCIe reset"); 1100 if (ret) { 1101 dev_err(dev, "unable to get reset gpio\n"); 1102 return ret; 1103 } 1104 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 1105 return imx6_pcie->reset_gpio; 1106 } 1107 1108 /* Fetch clocks */ 1109 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); 1110 if (IS_ERR(imx6_pcie->pcie_phy)) { 1111 dev_err(dev, "pcie_phy clock source missing or invalid\n"); 1112 return PTR_ERR(imx6_pcie->pcie_phy); 1113 } 1114 1115 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); 1116 if (IS_ERR(imx6_pcie->pcie_bus)) { 1117 dev_err(dev, "pcie_bus clock source missing or invalid\n"); 1118 return PTR_ERR(imx6_pcie->pcie_bus); 1119 } 1120 1121 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); 1122 if (IS_ERR(imx6_pcie->pcie)) { 1123 dev_err(dev, "pcie clock source missing or invalid\n"); 1124 return PTR_ERR(imx6_pcie->pcie); 1125 } 1126 1127 switch (imx6_pcie->drvdata->variant) { 1128 case IMX6SX: 1129 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 1130 "pcie_inbound_axi"); 1131 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { 1132 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n"); 1133 return PTR_ERR(imx6_pcie->pcie_inbound_axi); 1134 } 1135 break; 1136 case IMX8MQ: 1137 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1138 if (IS_ERR(imx6_pcie->pcie_aux)) { 1139 dev_err(dev, "pcie_aux clock source missing or invalid\n"); 1140 return PTR_ERR(imx6_pcie->pcie_aux); 1141 } 1142 /* fall through */ 1143 case IMX7D: 1144 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1145 imx6_pcie->controller_id = 1; 1146 1147 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 1148 "pciephy"); 1149 if (IS_ERR(imx6_pcie->pciephy_reset)) { 1150 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 1151 return PTR_ERR(imx6_pcie->pciephy_reset); 1152 } 1153 1154 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1155 "apps"); 1156 if (IS_ERR(imx6_pcie->apps_reset)) { 1157 dev_err(dev, "Failed to get PCIE APPS reset control\n"); 1158 return PTR_ERR(imx6_pcie->apps_reset); 1159 } 1160 break; 1161 default: 1162 break; 1163 } 1164 1165 /* Grab turnoff reset */ 1166 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1167 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1168 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1169 return PTR_ERR(imx6_pcie->turnoff_reset); 1170 } 1171 1172 /* Grab GPR config register range */ 1173 imx6_pcie->iomuxc_gpr = 1174 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 1175 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1176 dev_err(dev, "unable to find iomuxc registers\n"); 1177 return PTR_ERR(imx6_pcie->iomuxc_gpr); 1178 } 1179 1180 /* Grab PCIe PHY Tx Settings */ 1181 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1182 &imx6_pcie->tx_deemph_gen1)) 1183 imx6_pcie->tx_deemph_gen1 = 0; 1184 1185 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1186 &imx6_pcie->tx_deemph_gen2_3p5db)) 1187 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1188 1189 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1190 &imx6_pcie->tx_deemph_gen2_6db)) 1191 imx6_pcie->tx_deemph_gen2_6db = 20; 1192 1193 if (of_property_read_u32(node, "fsl,tx-swing-full", 1194 &imx6_pcie->tx_swing_full)) 1195 imx6_pcie->tx_swing_full = 127; 1196 1197 if (of_property_read_u32(node, "fsl,tx-swing-low", 1198 &imx6_pcie->tx_swing_low)) 1199 imx6_pcie->tx_swing_low = 127; 1200 1201 /* Limit link speed */ 1202 ret = of_property_read_u32(node, "fsl,max-link-speed", 1203 &imx6_pcie->link_gen); 1204 if (ret) 1205 imx6_pcie->link_gen = 1; 1206 1207 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1208 if (IS_ERR(imx6_pcie->vpcie)) { 1209 if (PTR_ERR(imx6_pcie->vpcie) == -EPROBE_DEFER) 1210 return -EPROBE_DEFER; 1211 imx6_pcie->vpcie = NULL; 1212 } 1213 1214 platform_set_drvdata(pdev, imx6_pcie); 1215 1216 ret = imx6_pcie_attach_pd(dev); 1217 if (ret) 1218 return ret; 1219 1220 ret = imx6_add_pcie_port(imx6_pcie, pdev); 1221 if (ret < 0) 1222 return ret; 1223 1224 if (pci_msi_enabled()) { 1225 val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP + 1226 PCI_MSI_FLAGS); 1227 val |= PCI_MSI_FLAGS_ENABLE; 1228 dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS, 1229 val); 1230 } 1231 1232 return 0; 1233 } 1234 1235 static void imx6_pcie_shutdown(struct platform_device *pdev) 1236 { 1237 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1238 1239 /* bring down link, so bootloader gets clean state in case of reboot */ 1240 imx6_pcie_assert_core_reset(imx6_pcie); 1241 } 1242 1243 static const struct imx6_pcie_drvdata drvdata[] = { 1244 [IMX6Q] = { 1245 .variant = IMX6Q, 1246 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1247 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1248 }, 1249 [IMX6SX] = { 1250 .variant = IMX6SX, 1251 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1252 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1253 }, 1254 [IMX6QP] = { 1255 .variant = IMX6QP, 1256 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1257 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1258 }, 1259 [IMX7D] = { 1260 .variant = IMX7D, 1261 }, 1262 [IMX8MQ] = { 1263 .variant = IMX8MQ, 1264 }, 1265 }; 1266 1267 static const struct of_device_id imx6_pcie_of_match[] = { 1268 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1269 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1270 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1271 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1272 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } , 1273 {}, 1274 }; 1275 1276 static struct platform_driver imx6_pcie_driver = { 1277 .driver = { 1278 .name = "imx6q-pcie", 1279 .of_match_table = imx6_pcie_of_match, 1280 .suppress_bind_attrs = true, 1281 .pm = &imx6_pcie_pm_ops, 1282 }, 1283 .probe = imx6_pcie_probe, 1284 .shutdown = imx6_pcie_shutdown, 1285 }; 1286 1287 static int __init imx6_pcie_init(void) 1288 { 1289 #ifdef CONFIG_ARM 1290 /* 1291 * Since probe() can be deferred we need to make sure that 1292 * hook_fault_code is not called after __init memory is freed 1293 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1294 * we can install the handler here without risking it 1295 * accessing some uninitialized driver state. 1296 */ 1297 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1298 "external abort on non-linefetch"); 1299 #endif 1300 1301 return platform_driver_register(&imx6_pcie_driver); 1302 } 1303 device_initcall(imx6_pcie_init); 1304