1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * http://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio.h> 14 #include <linux/kernel.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 17 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 18 #include <linux/module.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of_device.h> 21 #include <linux/pci.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/resource.h> 26 #include <linux/signal.h> 27 #include <linux/types.h> 28 #include <linux/interrupt.h> 29 #include <linux/reset.h> 30 #include <linux/pm_domain.h> 31 #include <linux/pm_runtime.h> 32 33 #include "pcie-designware.h" 34 35 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 36 37 enum imx6_pcie_variants { 38 IMX6Q, 39 IMX6SX, 40 IMX6QP, 41 IMX7D, 42 }; 43 44 struct imx6_pcie { 45 struct dw_pcie *pci; 46 int reset_gpio; 47 bool gpio_active_high; 48 struct clk *pcie_bus; 49 struct clk *pcie_phy; 50 struct clk *pcie_inbound_axi; 51 struct clk *pcie; 52 struct regmap *iomuxc_gpr; 53 struct reset_control *pciephy_reset; 54 struct reset_control *apps_reset; 55 struct reset_control *turnoff_reset; 56 enum imx6_pcie_variants variant; 57 u32 tx_deemph_gen1; 58 u32 tx_deemph_gen2_3p5db; 59 u32 tx_deemph_gen2_6db; 60 u32 tx_swing_full; 61 u32 tx_swing_low; 62 int link_gen; 63 struct regulator *vpcie; 64 65 /* power domain for pcie */ 66 struct device *pd_pcie; 67 /* power domain for pcie phy */ 68 struct device *pd_pcie_phy; 69 }; 70 71 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 72 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000 73 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50 74 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 75 76 /* PCIe Root Complex registers (memory-mapped) */ 77 #define PCIE_RC_IMX6_MSI_CAP 0x50 78 #define PCIE_RC_LCR 0x7c 79 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 80 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 81 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf 82 83 #define PCIE_RC_LCSR 0x80 84 85 /* PCIe Port Logic registers (memory-mapped) */ 86 #define PL_OFFSET 0x700 87 #define PCIE_PL_PFLR (PL_OFFSET + 0x08) 88 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) 89 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) 90 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) 91 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) 92 93 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 94 #define PCIE_PHY_CTRL_DATA_LOC 0 95 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 96 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 97 #define PCIE_PHY_CTRL_WR_LOC 18 98 #define PCIE_PHY_CTRL_RD_LOC 19 99 100 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 101 #define PCIE_PHY_STAT_ACK_LOC 16 102 103 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 104 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) 105 106 /* PHY registers (not memory-mapped) */ 107 #define PCIE_PHY_ATEOVRD 0x10 108 #define PCIE_PHY_ATEOVRD_EN (0x1 << 2) 109 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 110 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 111 112 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 113 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 114 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 115 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD (0x1 << 9) 116 117 #define PCIE_PHY_RX_ASIC_OUT 0x100D 118 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 119 120 #define PHY_RX_OVRD_IN_LO 0x1005 121 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) 122 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) 123 124 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) 125 { 126 struct dw_pcie *pci = imx6_pcie->pci; 127 u32 val; 128 u32 max_iterations = 10; 129 u32 wait_counter = 0; 130 131 do { 132 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 133 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 134 wait_counter++; 135 136 if (val == exp_val) 137 return 0; 138 139 udelay(1); 140 } while (wait_counter < max_iterations); 141 142 return -ETIMEDOUT; 143 } 144 145 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 146 { 147 struct dw_pcie *pci = imx6_pcie->pci; 148 u32 val; 149 int ret; 150 151 val = addr << PCIE_PHY_CTRL_DATA_LOC; 152 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 153 154 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 155 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 156 157 ret = pcie_phy_poll_ack(imx6_pcie, 1); 158 if (ret) 159 return ret; 160 161 val = addr << PCIE_PHY_CTRL_DATA_LOC; 162 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 163 164 return pcie_phy_poll_ack(imx6_pcie, 0); 165 } 166 167 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 168 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) 169 { 170 struct dw_pcie *pci = imx6_pcie->pci; 171 u32 val, phy_ctl; 172 int ret; 173 174 ret = pcie_phy_wait_ack(imx6_pcie, addr); 175 if (ret) 176 return ret; 177 178 /* assert Read signal */ 179 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 180 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 181 182 ret = pcie_phy_poll_ack(imx6_pcie, 1); 183 if (ret) 184 return ret; 185 186 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 187 *data = val & 0xffff; 188 189 /* deassert Read signal */ 190 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 191 192 return pcie_phy_poll_ack(imx6_pcie, 0); 193 } 194 195 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) 196 { 197 struct dw_pcie *pci = imx6_pcie->pci; 198 u32 var; 199 int ret; 200 201 /* write addr */ 202 /* cap addr */ 203 ret = pcie_phy_wait_ack(imx6_pcie, addr); 204 if (ret) 205 return ret; 206 207 var = data << PCIE_PHY_CTRL_DATA_LOC; 208 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 209 210 /* capture data */ 211 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 213 214 ret = pcie_phy_poll_ack(imx6_pcie, 1); 215 if (ret) 216 return ret; 217 218 /* deassert cap data */ 219 var = data << PCIE_PHY_CTRL_DATA_LOC; 220 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 221 222 /* wait for ack de-assertion */ 223 ret = pcie_phy_poll_ack(imx6_pcie, 0); 224 if (ret) 225 return ret; 226 227 /* assert wr signal */ 228 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 230 231 /* wait for ack */ 232 ret = pcie_phy_poll_ack(imx6_pcie, 1); 233 if (ret) 234 return ret; 235 236 /* deassert wr signal */ 237 var = data << PCIE_PHY_CTRL_DATA_LOC; 238 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 239 240 /* wait for ack de-assertion */ 241 ret = pcie_phy_poll_ack(imx6_pcie, 0); 242 if (ret) 243 return ret; 244 245 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 246 247 return 0; 248 } 249 250 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 251 { 252 u32 tmp; 253 254 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 255 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 256 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 257 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 258 259 usleep_range(2000, 3000); 260 261 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 262 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 263 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 264 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 265 } 266 267 /* Added for PCI abort handling */ 268 static int imx6q_pcie_abort_handler(unsigned long addr, 269 unsigned int fsr, struct pt_regs *regs) 270 { 271 unsigned long pc = instruction_pointer(regs); 272 unsigned long instr = *(unsigned long *)pc; 273 int reg = (instr >> 12) & 15; 274 275 /* 276 * If the instruction being executed was a read, 277 * make it look like it read all-ones. 278 */ 279 if ((instr & 0x0c100000) == 0x04100000) { 280 unsigned long val; 281 282 if (instr & 0x00400000) 283 val = 255; 284 else 285 val = -1; 286 287 regs->uregs[reg] = val; 288 regs->ARM_pc += 4; 289 return 0; 290 } 291 292 if ((instr & 0x0e100090) == 0x00100090) { 293 regs->uregs[reg] = -1; 294 regs->ARM_pc += 4; 295 return 0; 296 } 297 298 return 1; 299 } 300 301 static int imx6_pcie_attach_pd(struct device *dev) 302 { 303 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 304 struct device_link *link; 305 306 /* Do nothing when in a single power domain */ 307 if (dev->pm_domain) 308 return 0; 309 310 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 311 if (IS_ERR(imx6_pcie->pd_pcie)) 312 return PTR_ERR(imx6_pcie->pd_pcie); 313 /* Do nothing when power domain missing */ 314 if (!imx6_pcie->pd_pcie) 315 return 0; 316 link = device_link_add(dev, imx6_pcie->pd_pcie, 317 DL_FLAG_STATELESS | 318 DL_FLAG_PM_RUNTIME | 319 DL_FLAG_RPM_ACTIVE); 320 if (!link) { 321 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 322 return -EINVAL; 323 } 324 325 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 326 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 327 return PTR_ERR(imx6_pcie->pd_pcie_phy); 328 329 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 330 DL_FLAG_STATELESS | 331 DL_FLAG_PM_RUNTIME | 332 DL_FLAG_RPM_ACTIVE); 333 if (!link) { 334 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 335 return -EINVAL; 336 } 337 338 return 0; 339 } 340 341 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 342 { 343 struct device *dev = imx6_pcie->pci->dev; 344 345 switch (imx6_pcie->variant) { 346 case IMX7D: 347 reset_control_assert(imx6_pcie->pciephy_reset); 348 reset_control_assert(imx6_pcie->apps_reset); 349 break; 350 case IMX6SX: 351 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 352 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 353 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 354 /* Force PCIe PHY reset */ 355 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 356 IMX6SX_GPR5_PCIE_BTNRST_RESET, 357 IMX6SX_GPR5_PCIE_BTNRST_RESET); 358 break; 359 case IMX6QP: 360 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 361 IMX6Q_GPR1_PCIE_SW_RST, 362 IMX6Q_GPR1_PCIE_SW_RST); 363 break; 364 case IMX6Q: 365 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 366 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 367 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 368 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 369 break; 370 } 371 372 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { 373 int ret = regulator_disable(imx6_pcie->vpcie); 374 375 if (ret) 376 dev_err(dev, "failed to disable vpcie regulator: %d\n", 377 ret); 378 } 379 } 380 381 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 382 { 383 struct dw_pcie *pci = imx6_pcie->pci; 384 struct device *dev = pci->dev; 385 int ret = 0; 386 387 switch (imx6_pcie->variant) { 388 case IMX6SX: 389 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 390 if (ret) { 391 dev_err(dev, "unable to enable pcie_axi clock\n"); 392 break; 393 } 394 395 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 396 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 397 break; 398 case IMX6QP: /* FALLTHROUGH */ 399 case IMX6Q: 400 /* power up core phy and enable ref clock */ 401 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 402 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 403 /* 404 * the async reset input need ref clock to sync internally, 405 * when the ref clock comes after reset, internal synced 406 * reset time is too short, cannot meet the requirement. 407 * add one ~10us delay here. 408 */ 409 udelay(10); 410 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 411 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 412 break; 413 case IMX7D: 414 break; 415 } 416 417 return ret; 418 } 419 420 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 421 { 422 u32 val; 423 unsigned int retries; 424 struct device *dev = imx6_pcie->pci->dev; 425 426 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) { 427 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val); 428 429 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED) 430 return; 431 432 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN, 433 PHY_PLL_LOCK_WAIT_USLEEP_MAX); 434 } 435 436 dev_err(dev, "PCIe PLL lock timeout\n"); 437 } 438 439 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 440 { 441 struct dw_pcie *pci = imx6_pcie->pci; 442 struct device *dev = pci->dev; 443 int ret; 444 445 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { 446 ret = regulator_enable(imx6_pcie->vpcie); 447 if (ret) { 448 dev_err(dev, "failed to enable vpcie regulator: %d\n", 449 ret); 450 return; 451 } 452 } 453 454 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 455 if (ret) { 456 dev_err(dev, "unable to enable pcie_phy clock\n"); 457 goto err_pcie_phy; 458 } 459 460 ret = clk_prepare_enable(imx6_pcie->pcie_bus); 461 if (ret) { 462 dev_err(dev, "unable to enable pcie_bus clock\n"); 463 goto err_pcie_bus; 464 } 465 466 ret = clk_prepare_enable(imx6_pcie->pcie); 467 if (ret) { 468 dev_err(dev, "unable to enable pcie clock\n"); 469 goto err_pcie; 470 } 471 472 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 473 if (ret) { 474 dev_err(dev, "unable to enable pcie ref clock\n"); 475 goto err_ref_clk; 476 } 477 478 /* allow the clocks to stabilize */ 479 usleep_range(200, 500); 480 481 /* Some boards don't have PCIe reset GPIO. */ 482 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 483 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 484 imx6_pcie->gpio_active_high); 485 msleep(100); 486 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 487 !imx6_pcie->gpio_active_high); 488 } 489 490 switch (imx6_pcie->variant) { 491 case IMX7D: 492 reset_control_deassert(imx6_pcie->pciephy_reset); 493 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 494 break; 495 case IMX6SX: 496 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 497 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 498 break; 499 case IMX6QP: 500 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 501 IMX6Q_GPR1_PCIE_SW_RST, 0); 502 503 usleep_range(200, 500); 504 break; 505 case IMX6Q: /* Nothing to do */ 506 break; 507 } 508 509 return; 510 511 err_ref_clk: 512 clk_disable_unprepare(imx6_pcie->pcie); 513 err_pcie: 514 clk_disable_unprepare(imx6_pcie->pcie_bus); 515 err_pcie_bus: 516 clk_disable_unprepare(imx6_pcie->pcie_phy); 517 err_pcie_phy: 518 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { 519 ret = regulator_disable(imx6_pcie->vpcie); 520 if (ret) 521 dev_err(dev, "failed to disable vpcie regulator: %d\n", 522 ret); 523 } 524 } 525 526 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 527 { 528 switch (imx6_pcie->variant) { 529 case IMX7D: 530 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 531 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 532 break; 533 case IMX6SX: 534 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 535 IMX6SX_GPR12_PCIE_RX_EQ_MASK, 536 IMX6SX_GPR12_PCIE_RX_EQ_2); 537 /* FALLTHROUGH */ 538 default: 539 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 540 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 541 542 /* configure constant input signal to the pcie ctrl and phy */ 543 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 544 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 545 546 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 547 IMX6Q_GPR8_TX_DEEMPH_GEN1, 548 imx6_pcie->tx_deemph_gen1 << 0); 549 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 550 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 551 imx6_pcie->tx_deemph_gen2_3p5db << 6); 552 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 553 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 554 imx6_pcie->tx_deemph_gen2_6db << 12); 555 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 556 IMX6Q_GPR8_TX_SWING_FULL, 557 imx6_pcie->tx_swing_full << 18); 558 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 559 IMX6Q_GPR8_TX_SWING_LOW, 560 imx6_pcie->tx_swing_low << 25); 561 break; 562 } 563 564 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 565 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); 566 } 567 568 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 569 { 570 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); 571 int mult, div; 572 u32 val; 573 574 switch (phy_rate) { 575 case 125000000: 576 /* 577 * The default settings of the MPLL are for a 125MHz input 578 * clock, so no need to reconfigure anything in that case. 579 */ 580 return 0; 581 case 100000000: 582 mult = 25; 583 div = 0; 584 break; 585 case 200000000: 586 mult = 25; 587 div = 1; 588 break; 589 default: 590 dev_err(imx6_pcie->pci->dev, 591 "Unsupported PHY reference clock rate %lu\n", phy_rate); 592 return -EINVAL; 593 } 594 595 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 596 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 597 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 598 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 599 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 600 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 601 602 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 603 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 604 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 605 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 606 val |= PCIE_PHY_ATEOVRD_EN; 607 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 608 609 return 0; 610 } 611 612 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) 613 { 614 struct dw_pcie *pci = imx6_pcie->pci; 615 struct device *dev = pci->dev; 616 617 /* check if the link is up or not */ 618 if (!dw_pcie_wait_for_link(pci)) 619 return 0; 620 621 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 622 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 623 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 624 return -ETIMEDOUT; 625 } 626 627 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 628 { 629 struct dw_pcie *pci = imx6_pcie->pci; 630 struct device *dev = pci->dev; 631 u32 tmp; 632 unsigned int retries; 633 634 for (retries = 0; retries < 200; retries++) { 635 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 636 /* Test if the speed change finished. */ 637 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 638 return 0; 639 usleep_range(100, 1000); 640 } 641 642 dev_err(dev, "Speed change timeout\n"); 643 return -EINVAL; 644 } 645 646 static void imx6_pcie_ltssm_enable(struct device *dev) 647 { 648 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 649 650 switch (imx6_pcie->variant) { 651 case IMX6Q: 652 case IMX6SX: 653 case IMX6QP: 654 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 655 IMX6Q_GPR12_PCIE_CTL_2, 656 IMX6Q_GPR12_PCIE_CTL_2); 657 break; 658 case IMX7D: 659 reset_control_deassert(imx6_pcie->apps_reset); 660 break; 661 } 662 } 663 664 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 665 { 666 struct dw_pcie *pci = imx6_pcie->pci; 667 struct device *dev = pci->dev; 668 u32 tmp; 669 int ret; 670 671 /* 672 * Force Gen1 operation when starting the link. In case the link is 673 * started in Gen2 mode, there is a possibility the devices on the 674 * bus will not be detected at all. This happens with PCIe switches. 675 */ 676 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); 677 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 678 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; 679 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); 680 681 /* Start LTSSM. */ 682 imx6_pcie_ltssm_enable(dev); 683 684 ret = imx6_pcie_wait_for_link(imx6_pcie); 685 if (ret) 686 goto err_reset_phy; 687 688 if (imx6_pcie->link_gen == 2) { 689 /* Allow Gen2 mode after the link is up. */ 690 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); 691 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 692 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; 693 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); 694 695 /* 696 * Start Directed Speed Change so the best possible 697 * speed both link partners support can be negotiated. 698 */ 699 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 700 tmp |= PORT_LOGIC_SPEED_CHANGE; 701 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 702 703 if (imx6_pcie->variant != IMX7D) { 704 /* 705 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 706 * from i.MX6 family when no link speed transition 707 * occurs and we go Gen1 -> yep, Gen1. The difference 708 * is that, in such case, it will not be cleared by HW 709 * which will cause the following code to report false 710 * failure. 711 */ 712 713 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 714 if (ret) { 715 dev_err(dev, "Failed to bring link up!\n"); 716 goto err_reset_phy; 717 } 718 } 719 720 /* Make sure link training is finished as well! */ 721 ret = imx6_pcie_wait_for_link(imx6_pcie); 722 if (ret) { 723 dev_err(dev, "Failed to bring link up!\n"); 724 goto err_reset_phy; 725 } 726 } else { 727 dev_info(dev, "Link: Gen2 disabled\n"); 728 } 729 730 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR); 731 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); 732 return 0; 733 734 err_reset_phy: 735 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 736 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 737 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 738 imx6_pcie_reset_phy(imx6_pcie); 739 return ret; 740 } 741 742 static int imx6_pcie_host_init(struct pcie_port *pp) 743 { 744 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 745 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 746 747 imx6_pcie_assert_core_reset(imx6_pcie); 748 imx6_pcie_init_phy(imx6_pcie); 749 imx6_pcie_deassert_core_reset(imx6_pcie); 750 imx6_setup_phy_mpll(imx6_pcie); 751 dw_pcie_setup_rc(pp); 752 imx6_pcie_establish_link(imx6_pcie); 753 754 if (IS_ENABLED(CONFIG_PCI_MSI)) 755 dw_pcie_msi_init(pp); 756 757 return 0; 758 } 759 760 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 761 .host_init = imx6_pcie_host_init, 762 }; 763 764 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, 765 struct platform_device *pdev) 766 { 767 struct dw_pcie *pci = imx6_pcie->pci; 768 struct pcie_port *pp = &pci->pp; 769 struct device *dev = &pdev->dev; 770 int ret; 771 772 if (IS_ENABLED(CONFIG_PCI_MSI)) { 773 pp->msi_irq = platform_get_irq_byname(pdev, "msi"); 774 if (pp->msi_irq <= 0) { 775 dev_err(dev, "failed to get MSI irq\n"); 776 return -ENODEV; 777 } 778 } 779 780 pp->ops = &imx6_pcie_host_ops; 781 782 ret = dw_pcie_host_init(pp); 783 if (ret) { 784 dev_err(dev, "failed to initialize host\n"); 785 return ret; 786 } 787 788 return 0; 789 } 790 791 static const struct dw_pcie_ops dw_pcie_ops = { 792 /* No special ops needed, but pcie-designware still expects this struct */ 793 }; 794 795 #ifdef CONFIG_PM_SLEEP 796 static void imx6_pcie_ltssm_disable(struct device *dev) 797 { 798 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 799 800 switch (imx6_pcie->variant) { 801 case IMX6SX: 802 case IMX6QP: 803 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 804 IMX6Q_GPR12_PCIE_CTL_2, 0); 805 break; 806 case IMX7D: 807 reset_control_assert(imx6_pcie->apps_reset); 808 break; 809 default: 810 dev_err(dev, "ltssm_disable not supported\n"); 811 } 812 } 813 814 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 815 { 816 struct device *dev = imx6_pcie->pci->dev; 817 818 /* Some variants have a turnoff reset in DT */ 819 if (imx6_pcie->turnoff_reset) { 820 reset_control_assert(imx6_pcie->turnoff_reset); 821 reset_control_deassert(imx6_pcie->turnoff_reset); 822 goto pm_turnoff_sleep; 823 } 824 825 /* Others poke directly at IOMUXC registers */ 826 switch (imx6_pcie->variant) { 827 case IMX6SX: 828 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 829 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 830 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 831 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 832 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 833 break; 834 default: 835 dev_err(dev, "PME_Turn_Off not implemented\n"); 836 return; 837 } 838 839 /* 840 * Components with an upstream port must respond to 841 * PME_Turn_Off with PME_TO_Ack but we can't check. 842 * 843 * The standard recommends a 1-10ms timeout after which to 844 * proceed anyway as if acks were received. 845 */ 846 pm_turnoff_sleep: 847 usleep_range(1000, 10000); 848 } 849 850 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 851 { 852 clk_disable_unprepare(imx6_pcie->pcie); 853 clk_disable_unprepare(imx6_pcie->pcie_phy); 854 clk_disable_unprepare(imx6_pcie->pcie_bus); 855 856 switch (imx6_pcie->variant) { 857 case IMX6SX: 858 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 859 break; 860 case IMX7D: 861 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 862 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 863 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 864 break; 865 default: 866 break; 867 } 868 } 869 870 static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie) 871 { 872 return (imx6_pcie->variant == IMX7D || 873 imx6_pcie->variant == IMX6SX); 874 } 875 876 static int imx6_pcie_suspend_noirq(struct device *dev) 877 { 878 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 879 880 if (!imx6_pcie_supports_suspend(imx6_pcie)) 881 return 0; 882 883 imx6_pcie_pm_turnoff(imx6_pcie); 884 imx6_pcie_clk_disable(imx6_pcie); 885 imx6_pcie_ltssm_disable(dev); 886 887 return 0; 888 } 889 890 static int imx6_pcie_resume_noirq(struct device *dev) 891 { 892 int ret; 893 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 894 struct pcie_port *pp = &imx6_pcie->pci->pp; 895 896 if (!imx6_pcie_supports_suspend(imx6_pcie)) 897 return 0; 898 899 imx6_pcie_assert_core_reset(imx6_pcie); 900 imx6_pcie_init_phy(imx6_pcie); 901 imx6_pcie_deassert_core_reset(imx6_pcie); 902 dw_pcie_setup_rc(pp); 903 904 ret = imx6_pcie_establish_link(imx6_pcie); 905 if (ret < 0) 906 dev_info(dev, "pcie link is down after resume.\n"); 907 908 return 0; 909 } 910 #endif 911 912 static const struct dev_pm_ops imx6_pcie_pm_ops = { 913 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 914 imx6_pcie_resume_noirq) 915 }; 916 917 static int imx6_pcie_probe(struct platform_device *pdev) 918 { 919 struct device *dev = &pdev->dev; 920 struct dw_pcie *pci; 921 struct imx6_pcie *imx6_pcie; 922 struct resource *dbi_base; 923 struct device_node *node = dev->of_node; 924 int ret; 925 u16 val; 926 927 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 928 if (!imx6_pcie) 929 return -ENOMEM; 930 931 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 932 if (!pci) 933 return -ENOMEM; 934 935 pci->dev = dev; 936 pci->ops = &dw_pcie_ops; 937 938 imx6_pcie->pci = pci; 939 imx6_pcie->variant = 940 (enum imx6_pcie_variants)of_device_get_match_data(dev); 941 942 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 943 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); 944 if (IS_ERR(pci->dbi_base)) 945 return PTR_ERR(pci->dbi_base); 946 947 /* Fetch GPIOs */ 948 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 949 imx6_pcie->gpio_active_high = of_property_read_bool(node, 950 "reset-gpio-active-high"); 951 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 952 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 953 imx6_pcie->gpio_active_high ? 954 GPIOF_OUT_INIT_HIGH : 955 GPIOF_OUT_INIT_LOW, 956 "PCIe reset"); 957 if (ret) { 958 dev_err(dev, "unable to get reset gpio\n"); 959 return ret; 960 } 961 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 962 return imx6_pcie->reset_gpio; 963 } 964 965 /* Fetch clocks */ 966 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); 967 if (IS_ERR(imx6_pcie->pcie_phy)) { 968 dev_err(dev, "pcie_phy clock source missing or invalid\n"); 969 return PTR_ERR(imx6_pcie->pcie_phy); 970 } 971 972 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); 973 if (IS_ERR(imx6_pcie->pcie_bus)) { 974 dev_err(dev, "pcie_bus clock source missing or invalid\n"); 975 return PTR_ERR(imx6_pcie->pcie_bus); 976 } 977 978 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); 979 if (IS_ERR(imx6_pcie->pcie)) { 980 dev_err(dev, "pcie clock source missing or invalid\n"); 981 return PTR_ERR(imx6_pcie->pcie); 982 } 983 984 switch (imx6_pcie->variant) { 985 case IMX6SX: 986 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 987 "pcie_inbound_axi"); 988 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { 989 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n"); 990 return PTR_ERR(imx6_pcie->pcie_inbound_axi); 991 } 992 break; 993 case IMX7D: 994 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 995 "pciephy"); 996 if (IS_ERR(imx6_pcie->pciephy_reset)) { 997 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 998 return PTR_ERR(imx6_pcie->pciephy_reset); 999 } 1000 1001 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1002 "apps"); 1003 if (IS_ERR(imx6_pcie->apps_reset)) { 1004 dev_err(dev, "Failed to get PCIE APPS reset control\n"); 1005 return PTR_ERR(imx6_pcie->apps_reset); 1006 } 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 /* Grab turnoff reset */ 1013 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1014 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1015 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1016 return PTR_ERR(imx6_pcie->turnoff_reset); 1017 } 1018 1019 /* Grab GPR config register range */ 1020 imx6_pcie->iomuxc_gpr = 1021 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 1022 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1023 dev_err(dev, "unable to find iomuxc registers\n"); 1024 return PTR_ERR(imx6_pcie->iomuxc_gpr); 1025 } 1026 1027 /* Grab PCIe PHY Tx Settings */ 1028 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1029 &imx6_pcie->tx_deemph_gen1)) 1030 imx6_pcie->tx_deemph_gen1 = 0; 1031 1032 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1033 &imx6_pcie->tx_deemph_gen2_3p5db)) 1034 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1035 1036 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1037 &imx6_pcie->tx_deemph_gen2_6db)) 1038 imx6_pcie->tx_deemph_gen2_6db = 20; 1039 1040 if (of_property_read_u32(node, "fsl,tx-swing-full", 1041 &imx6_pcie->tx_swing_full)) 1042 imx6_pcie->tx_swing_full = 127; 1043 1044 if (of_property_read_u32(node, "fsl,tx-swing-low", 1045 &imx6_pcie->tx_swing_low)) 1046 imx6_pcie->tx_swing_low = 127; 1047 1048 /* Limit link speed */ 1049 ret = of_property_read_u32(node, "fsl,max-link-speed", 1050 &imx6_pcie->link_gen); 1051 if (ret) 1052 imx6_pcie->link_gen = 1; 1053 1054 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1055 if (IS_ERR(imx6_pcie->vpcie)) { 1056 if (PTR_ERR(imx6_pcie->vpcie) == -EPROBE_DEFER) 1057 return -EPROBE_DEFER; 1058 imx6_pcie->vpcie = NULL; 1059 } 1060 1061 platform_set_drvdata(pdev, imx6_pcie); 1062 1063 ret = imx6_pcie_attach_pd(dev); 1064 if (ret) 1065 return ret; 1066 1067 ret = imx6_add_pcie_port(imx6_pcie, pdev); 1068 if (ret < 0) 1069 return ret; 1070 1071 if (pci_msi_enabled()) { 1072 val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP + 1073 PCI_MSI_FLAGS); 1074 val |= PCI_MSI_FLAGS_ENABLE; 1075 dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS, 1076 val); 1077 } 1078 1079 return 0; 1080 } 1081 1082 static void imx6_pcie_shutdown(struct platform_device *pdev) 1083 { 1084 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1085 1086 /* bring down link, so bootloader gets clean state in case of reboot */ 1087 imx6_pcie_assert_core_reset(imx6_pcie); 1088 } 1089 1090 static const struct of_device_id imx6_pcie_of_match[] = { 1091 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, }, 1092 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, }, 1093 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, }, 1094 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, }, 1095 {}, 1096 }; 1097 1098 static struct platform_driver imx6_pcie_driver = { 1099 .driver = { 1100 .name = "imx6q-pcie", 1101 .of_match_table = imx6_pcie_of_match, 1102 .suppress_bind_attrs = true, 1103 .pm = &imx6_pcie_pm_ops, 1104 }, 1105 .probe = imx6_pcie_probe, 1106 .shutdown = imx6_pcie_shutdown, 1107 }; 1108 1109 static int __init imx6_pcie_init(void) 1110 { 1111 /* 1112 * Since probe() can be deferred we need to make sure that 1113 * hook_fault_code is not called after __init memory is freed 1114 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1115 * we can install the handler here without risking it 1116 * accessing some uninitialized driver state. 1117 */ 1118 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1119 "external abort on non-linefetch"); 1120 1121 return platform_driver_register(&imx6_pcie_driver); 1122 } 1123 device_initcall(imx6_pcie_init); 1124