1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * https://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19 #include <linux/module.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_device.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 #include <linux/types.h> 30 #include <linux/interrupt.h> 31 #include <linux/reset.h> 32 #include <linux/phy/phy.h> 33 #include <linux/pm_domain.h> 34 #include <linux/pm_runtime.h> 35 36 #include "pcie-designware.h" 37 38 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 40 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 41 #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) 42 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 43 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 44 45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 46 47 enum imx6_pcie_variants { 48 IMX6Q, 49 IMX6SX, 50 IMX6QP, 51 IMX7D, 52 IMX8MQ, 53 IMX8MM, 54 }; 55 56 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 57 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 58 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 59 60 struct imx6_pcie_drvdata { 61 enum imx6_pcie_variants variant; 62 u32 flags; 63 int dbi_length; 64 }; 65 66 struct imx6_pcie { 67 struct dw_pcie *pci; 68 int reset_gpio; 69 bool gpio_active_high; 70 bool link_is_up; 71 struct clk *pcie_bus; 72 struct clk *pcie_phy; 73 struct clk *pcie_inbound_axi; 74 struct clk *pcie; 75 struct clk *pcie_aux; 76 struct regmap *iomuxc_gpr; 77 u32 controller_id; 78 struct reset_control *pciephy_reset; 79 struct reset_control *apps_reset; 80 struct reset_control *turnoff_reset; 81 u32 tx_deemph_gen1; 82 u32 tx_deemph_gen2_3p5db; 83 u32 tx_deemph_gen2_6db; 84 u32 tx_swing_full; 85 u32 tx_swing_low; 86 struct regulator *vpcie; 87 struct regulator *vph; 88 void __iomem *phy_base; 89 90 /* power domain for pcie */ 91 struct device *pd_pcie; 92 /* power domain for pcie phy */ 93 struct device *pd_pcie_phy; 94 struct phy *phy; 95 const struct imx6_pcie_drvdata *drvdata; 96 }; 97 98 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 99 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 100 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 101 102 /* PCIe Port Logic registers (memory-mapped) */ 103 #define PL_OFFSET 0x700 104 105 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 106 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 107 #define PCIE_PHY_CTRL_CAP_ADR BIT(16) 108 #define PCIE_PHY_CTRL_CAP_DAT BIT(17) 109 #define PCIE_PHY_CTRL_WR BIT(18) 110 #define PCIE_PHY_CTRL_RD BIT(19) 111 112 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 113 #define PCIE_PHY_STAT_ACK BIT(16) 114 115 /* PHY registers (not memory-mapped) */ 116 #define PCIE_PHY_ATEOVRD 0x10 117 #define PCIE_PHY_ATEOVRD_EN BIT(2) 118 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 119 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 120 121 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 122 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 123 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 124 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 125 126 #define PCIE_PHY_RX_ASIC_OUT 0x100D 127 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 128 129 /* iMX7 PCIe PHY registers */ 130 #define PCIE_PHY_CMN_REG4 0x14 131 /* These are probably the bits that *aren't* DCC_FB_EN */ 132 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 133 134 #define PCIE_PHY_CMN_REG15 0x54 135 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 136 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 137 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 138 139 #define PCIE_PHY_CMN_REG24 0x90 140 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 141 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 142 143 #define PCIE_PHY_CMN_REG26 0x98 144 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 145 146 #define PHY_RX_OVRD_IN_LO 0x1005 147 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 148 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 149 150 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 151 { 152 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 153 imx6_pcie->drvdata->variant != IMX8MM); 154 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 155 } 156 157 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 158 { 159 unsigned int mask, val; 160 161 if (imx6_pcie->drvdata->variant == IMX8MQ && 162 imx6_pcie->controller_id == 1) { 163 mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; 164 val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 165 PCI_EXP_TYPE_ROOT_PORT); 166 } else { 167 mask = IMX6Q_GPR12_DEVICE_TYPE; 168 val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, 169 PCI_EXP_TYPE_ROOT_PORT); 170 } 171 172 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); 173 } 174 175 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 176 { 177 struct dw_pcie *pci = imx6_pcie->pci; 178 bool val; 179 u32 max_iterations = 10; 180 u32 wait_counter = 0; 181 182 do { 183 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 184 PCIE_PHY_STAT_ACK; 185 wait_counter++; 186 187 if (val == exp_val) 188 return 0; 189 190 udelay(1); 191 } while (wait_counter < max_iterations); 192 193 return -ETIMEDOUT; 194 } 195 196 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 197 { 198 struct dw_pcie *pci = imx6_pcie->pci; 199 u32 val; 200 int ret; 201 202 val = PCIE_PHY_CTRL_DATA(addr); 203 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 204 205 val |= PCIE_PHY_CTRL_CAP_ADR; 206 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 207 208 ret = pcie_phy_poll_ack(imx6_pcie, true); 209 if (ret) 210 return ret; 211 212 val = PCIE_PHY_CTRL_DATA(addr); 213 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 214 215 return pcie_phy_poll_ack(imx6_pcie, false); 216 } 217 218 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 219 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 220 { 221 struct dw_pcie *pci = imx6_pcie->pci; 222 u32 phy_ctl; 223 int ret; 224 225 ret = pcie_phy_wait_ack(imx6_pcie, addr); 226 if (ret) 227 return ret; 228 229 /* assert Read signal */ 230 phy_ctl = PCIE_PHY_CTRL_RD; 231 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 232 233 ret = pcie_phy_poll_ack(imx6_pcie, true); 234 if (ret) 235 return ret; 236 237 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 238 239 /* deassert Read signal */ 240 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 241 242 return pcie_phy_poll_ack(imx6_pcie, false); 243 } 244 245 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 246 { 247 struct dw_pcie *pci = imx6_pcie->pci; 248 u32 var; 249 int ret; 250 251 /* write addr */ 252 /* cap addr */ 253 ret = pcie_phy_wait_ack(imx6_pcie, addr); 254 if (ret) 255 return ret; 256 257 var = PCIE_PHY_CTRL_DATA(data); 258 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 259 260 /* capture data */ 261 var |= PCIE_PHY_CTRL_CAP_DAT; 262 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 263 264 ret = pcie_phy_poll_ack(imx6_pcie, true); 265 if (ret) 266 return ret; 267 268 /* deassert cap data */ 269 var = PCIE_PHY_CTRL_DATA(data); 270 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 271 272 /* wait for ack de-assertion */ 273 ret = pcie_phy_poll_ack(imx6_pcie, false); 274 if (ret) 275 return ret; 276 277 /* assert wr signal */ 278 var = PCIE_PHY_CTRL_WR; 279 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 280 281 /* wait for ack */ 282 ret = pcie_phy_poll_ack(imx6_pcie, true); 283 if (ret) 284 return ret; 285 286 /* deassert wr signal */ 287 var = PCIE_PHY_CTRL_DATA(data); 288 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 289 290 /* wait for ack de-assertion */ 291 ret = pcie_phy_poll_ack(imx6_pcie, false); 292 if (ret) 293 return ret; 294 295 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 296 297 return 0; 298 } 299 300 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 301 { 302 switch (imx6_pcie->drvdata->variant) { 303 case IMX8MM: 304 /* 305 * The PHY initialization had been done in the PHY 306 * driver, break here directly. 307 */ 308 break; 309 case IMX8MQ: 310 /* 311 * TODO: Currently this code assumes external 312 * oscillator is being used 313 */ 314 regmap_update_bits(imx6_pcie->iomuxc_gpr, 315 imx6_pcie_grp_offset(imx6_pcie), 316 IMX8MQ_GPR_PCIE_REF_USE_PAD, 317 IMX8MQ_GPR_PCIE_REF_USE_PAD); 318 /* 319 * Regarding the datasheet, the PCIE_VPH is suggested 320 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the 321 * VREG_BYPASS should be cleared to zero. 322 */ 323 if (imx6_pcie->vph && 324 regulator_get_voltage(imx6_pcie->vph) > 3000000) 325 regmap_update_bits(imx6_pcie->iomuxc_gpr, 326 imx6_pcie_grp_offset(imx6_pcie), 327 IMX8MQ_GPR_PCIE_VREG_BYPASS, 328 0); 329 break; 330 case IMX7D: 331 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 332 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 333 break; 334 case IMX6SX: 335 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 336 IMX6SX_GPR12_PCIE_RX_EQ_MASK, 337 IMX6SX_GPR12_PCIE_RX_EQ_2); 338 fallthrough; 339 default: 340 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 341 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 342 343 /* configure constant input signal to the pcie ctrl and phy */ 344 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 345 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 346 347 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 348 IMX6Q_GPR8_TX_DEEMPH_GEN1, 349 imx6_pcie->tx_deemph_gen1 << 0); 350 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 351 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 352 imx6_pcie->tx_deemph_gen2_3p5db << 6); 353 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 354 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 355 imx6_pcie->tx_deemph_gen2_6db << 12); 356 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 357 IMX6Q_GPR8_TX_SWING_FULL, 358 imx6_pcie->tx_swing_full << 18); 359 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 360 IMX6Q_GPR8_TX_SWING_LOW, 361 imx6_pcie->tx_swing_low << 25); 362 break; 363 } 364 365 imx6_pcie_configure_type(imx6_pcie); 366 } 367 368 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 369 { 370 u32 val; 371 struct device *dev = imx6_pcie->pci->dev; 372 373 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 374 IOMUXC_GPR22, val, 375 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 376 PHY_PLL_LOCK_WAIT_USLEEP_MAX, 377 PHY_PLL_LOCK_WAIT_TIMEOUT)) 378 dev_err(dev, "PCIe PLL lock timeout\n"); 379 } 380 381 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 382 { 383 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); 384 int mult, div; 385 u16 val; 386 387 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 388 return 0; 389 390 switch (phy_rate) { 391 case 125000000: 392 /* 393 * The default settings of the MPLL are for a 125MHz input 394 * clock, so no need to reconfigure anything in that case. 395 */ 396 return 0; 397 case 100000000: 398 mult = 25; 399 div = 0; 400 break; 401 case 200000000: 402 mult = 25; 403 div = 1; 404 break; 405 default: 406 dev_err(imx6_pcie->pci->dev, 407 "Unsupported PHY reference clock rate %lu\n", phy_rate); 408 return -EINVAL; 409 } 410 411 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 412 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 413 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 414 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 415 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 416 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 417 418 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 419 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 420 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 421 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 422 val |= PCIE_PHY_ATEOVRD_EN; 423 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 424 425 return 0; 426 } 427 428 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 429 { 430 u16 tmp; 431 432 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 433 return; 434 435 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 436 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 437 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 438 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 439 440 usleep_range(2000, 3000); 441 442 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 443 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 444 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 445 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 446 } 447 448 #ifdef CONFIG_ARM 449 /* Added for PCI abort handling */ 450 static int imx6q_pcie_abort_handler(unsigned long addr, 451 unsigned int fsr, struct pt_regs *regs) 452 { 453 unsigned long pc = instruction_pointer(regs); 454 unsigned long instr = *(unsigned long *)pc; 455 int reg = (instr >> 12) & 15; 456 457 /* 458 * If the instruction being executed was a read, 459 * make it look like it read all-ones. 460 */ 461 if ((instr & 0x0c100000) == 0x04100000) { 462 unsigned long val; 463 464 if (instr & 0x00400000) 465 val = 255; 466 else 467 val = -1; 468 469 regs->uregs[reg] = val; 470 regs->ARM_pc += 4; 471 return 0; 472 } 473 474 if ((instr & 0x0e100090) == 0x00100090) { 475 regs->uregs[reg] = -1; 476 regs->ARM_pc += 4; 477 return 0; 478 } 479 480 return 1; 481 } 482 #endif 483 484 static int imx6_pcie_attach_pd(struct device *dev) 485 { 486 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 487 struct device_link *link; 488 489 /* Do nothing when in a single power domain */ 490 if (dev->pm_domain) 491 return 0; 492 493 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 494 if (IS_ERR(imx6_pcie->pd_pcie)) 495 return PTR_ERR(imx6_pcie->pd_pcie); 496 /* Do nothing when power domain missing */ 497 if (!imx6_pcie->pd_pcie) 498 return 0; 499 link = device_link_add(dev, imx6_pcie->pd_pcie, 500 DL_FLAG_STATELESS | 501 DL_FLAG_PM_RUNTIME | 502 DL_FLAG_RPM_ACTIVE); 503 if (!link) { 504 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 505 return -EINVAL; 506 } 507 508 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 509 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 510 return PTR_ERR(imx6_pcie->pd_pcie_phy); 511 512 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 513 DL_FLAG_STATELESS | 514 DL_FLAG_PM_RUNTIME | 515 DL_FLAG_RPM_ACTIVE); 516 if (!link) { 517 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 518 return -EINVAL; 519 } 520 521 return 0; 522 } 523 524 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 525 { 526 struct dw_pcie *pci = imx6_pcie->pci; 527 struct device *dev = pci->dev; 528 unsigned int offset; 529 int ret = 0; 530 531 switch (imx6_pcie->drvdata->variant) { 532 case IMX6SX: 533 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); 534 if (ret) { 535 dev_err(dev, "unable to enable pcie_axi clock\n"); 536 break; 537 } 538 539 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 540 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 541 break; 542 case IMX6QP: 543 case IMX6Q: 544 /* power up core phy and enable ref clock */ 545 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 546 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 547 /* 548 * the async reset input need ref clock to sync internally, 549 * when the ref clock comes after reset, internal synced 550 * reset time is too short, cannot meet the requirement. 551 * add one ~10us delay here. 552 */ 553 usleep_range(10, 100); 554 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 555 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 556 break; 557 case IMX7D: 558 break; 559 case IMX8MM: 560 case IMX8MQ: 561 ret = clk_prepare_enable(imx6_pcie->pcie_aux); 562 if (ret) { 563 dev_err(dev, "unable to enable pcie_aux clock\n"); 564 break; 565 } 566 567 offset = imx6_pcie_grp_offset(imx6_pcie); 568 /* 569 * Set the over ride low and enabled 570 * make sure that REF_CLK is turned on. 571 */ 572 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 573 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 574 0); 575 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 576 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 577 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 578 break; 579 } 580 581 return ret; 582 } 583 584 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 585 { 586 switch (imx6_pcie->drvdata->variant) { 587 case IMX6SX: 588 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); 589 break; 590 case IMX6QP: 591 case IMX6Q: 592 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 593 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 594 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 595 IMX6Q_GPR1_PCIE_TEST_PD, 596 IMX6Q_GPR1_PCIE_TEST_PD); 597 break; 598 case IMX7D: 599 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 600 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 601 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 602 break; 603 case IMX8MM: 604 case IMX8MQ: 605 clk_disable_unprepare(imx6_pcie->pcie_aux); 606 break; 607 default: 608 break; 609 } 610 } 611 612 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 613 { 614 struct dw_pcie *pci = imx6_pcie->pci; 615 struct device *dev = pci->dev; 616 int ret; 617 618 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 619 if (ret) { 620 dev_err(dev, "unable to enable pcie_phy clock\n"); 621 return ret; 622 } 623 624 ret = clk_prepare_enable(imx6_pcie->pcie_bus); 625 if (ret) { 626 dev_err(dev, "unable to enable pcie_bus clock\n"); 627 goto err_pcie_bus; 628 } 629 630 ret = clk_prepare_enable(imx6_pcie->pcie); 631 if (ret) { 632 dev_err(dev, "unable to enable pcie clock\n"); 633 goto err_pcie; 634 } 635 636 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 637 if (ret) { 638 dev_err(dev, "unable to enable pcie ref clock\n"); 639 goto err_ref_clk; 640 } 641 642 /* allow the clocks to stabilize */ 643 usleep_range(200, 500); 644 return 0; 645 646 err_ref_clk: 647 clk_disable_unprepare(imx6_pcie->pcie); 648 err_pcie: 649 clk_disable_unprepare(imx6_pcie->pcie_bus); 650 err_pcie_bus: 651 clk_disable_unprepare(imx6_pcie->pcie_phy); 652 653 return ret; 654 } 655 656 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 657 { 658 imx6_pcie_disable_ref_clk(imx6_pcie); 659 clk_disable_unprepare(imx6_pcie->pcie); 660 clk_disable_unprepare(imx6_pcie->pcie_bus); 661 clk_disable_unprepare(imx6_pcie->pcie_phy); 662 } 663 664 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 665 { 666 switch (imx6_pcie->drvdata->variant) { 667 case IMX7D: 668 case IMX8MQ: 669 reset_control_assert(imx6_pcie->pciephy_reset); 670 fallthrough; 671 case IMX8MM: 672 reset_control_assert(imx6_pcie->apps_reset); 673 break; 674 case IMX6SX: 675 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 676 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 677 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 678 /* Force PCIe PHY reset */ 679 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 680 IMX6SX_GPR5_PCIE_BTNRST_RESET, 681 IMX6SX_GPR5_PCIE_BTNRST_RESET); 682 break; 683 case IMX6QP: 684 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 685 IMX6Q_GPR1_PCIE_SW_RST, 686 IMX6Q_GPR1_PCIE_SW_RST); 687 break; 688 case IMX6Q: 689 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 690 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 691 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 692 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 693 break; 694 } 695 696 /* Some boards don't have PCIe reset GPIO. */ 697 if (gpio_is_valid(imx6_pcie->reset_gpio)) 698 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 699 imx6_pcie->gpio_active_high); 700 } 701 702 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 703 { 704 struct dw_pcie *pci = imx6_pcie->pci; 705 struct device *dev = pci->dev; 706 707 switch (imx6_pcie->drvdata->variant) { 708 case IMX8MQ: 709 reset_control_deassert(imx6_pcie->pciephy_reset); 710 break; 711 case IMX7D: 712 reset_control_deassert(imx6_pcie->pciephy_reset); 713 714 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 715 * oscillate, especially when cold. This turns off "Duty-cycle 716 * Corrector" and other mysterious undocumented things. 717 */ 718 if (likely(imx6_pcie->phy_base)) { 719 /* De-assert DCC_FB_EN */ 720 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 721 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 722 /* Assert RX_EQS and RX_EQS_SEL */ 723 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 724 | PCIE_PHY_CMN_REG24_RX_EQ, 725 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 726 /* Assert ATT_MODE */ 727 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 728 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 729 } else { 730 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 731 } 732 733 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 734 break; 735 case IMX6SX: 736 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 737 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 738 break; 739 case IMX6QP: 740 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 741 IMX6Q_GPR1_PCIE_SW_RST, 0); 742 743 usleep_range(200, 500); 744 break; 745 case IMX6Q: /* Nothing to do */ 746 case IMX8MM: 747 break; 748 } 749 750 /* Some boards don't have PCIe reset GPIO. */ 751 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 752 msleep(100); 753 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 754 !imx6_pcie->gpio_active_high); 755 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 756 msleep(100); 757 } 758 759 return 0; 760 } 761 762 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 763 { 764 struct dw_pcie *pci = imx6_pcie->pci; 765 struct device *dev = pci->dev; 766 u32 tmp; 767 unsigned int retries; 768 769 for (retries = 0; retries < 200; retries++) { 770 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 771 /* Test if the speed change finished. */ 772 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 773 return 0; 774 usleep_range(100, 1000); 775 } 776 777 dev_err(dev, "Speed change timeout\n"); 778 return -ETIMEDOUT; 779 } 780 781 static void imx6_pcie_ltssm_enable(struct device *dev) 782 { 783 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 784 785 switch (imx6_pcie->drvdata->variant) { 786 case IMX6Q: 787 case IMX6SX: 788 case IMX6QP: 789 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 790 IMX6Q_GPR12_PCIE_CTL_2, 791 IMX6Q_GPR12_PCIE_CTL_2); 792 break; 793 case IMX7D: 794 case IMX8MQ: 795 case IMX8MM: 796 reset_control_deassert(imx6_pcie->apps_reset); 797 break; 798 } 799 } 800 801 static void imx6_pcie_ltssm_disable(struct device *dev) 802 { 803 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 804 805 switch (imx6_pcie->drvdata->variant) { 806 case IMX6Q: 807 case IMX6SX: 808 case IMX6QP: 809 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 810 IMX6Q_GPR12_PCIE_CTL_2, 0); 811 break; 812 case IMX7D: 813 case IMX8MQ: 814 case IMX8MM: 815 reset_control_assert(imx6_pcie->apps_reset); 816 break; 817 } 818 } 819 820 static int imx6_pcie_start_link(struct dw_pcie *pci) 821 { 822 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 823 struct device *dev = pci->dev; 824 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 825 u32 tmp; 826 int ret; 827 828 /* 829 * Force Gen1 operation when starting the link. In case the link is 830 * started in Gen2 mode, there is a possibility the devices on the 831 * bus will not be detected at all. This happens with PCIe switches. 832 */ 833 dw_pcie_dbi_ro_wr_en(pci); 834 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 835 tmp &= ~PCI_EXP_LNKCAP_SLS; 836 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 837 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 838 dw_pcie_dbi_ro_wr_dis(pci); 839 840 /* Start LTSSM. */ 841 imx6_pcie_ltssm_enable(dev); 842 843 ret = dw_pcie_wait_for_link(pci); 844 if (ret) 845 goto err_reset_phy; 846 847 if (pci->link_gen > 1) { 848 /* Allow faster modes after the link is up */ 849 dw_pcie_dbi_ro_wr_en(pci); 850 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 851 tmp &= ~PCI_EXP_LNKCAP_SLS; 852 tmp |= pci->link_gen; 853 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 854 855 /* 856 * Start Directed Speed Change so the best possible 857 * speed both link partners support can be negotiated. 858 */ 859 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 860 tmp |= PORT_LOGIC_SPEED_CHANGE; 861 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 862 dw_pcie_dbi_ro_wr_dis(pci); 863 864 if (imx6_pcie->drvdata->flags & 865 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 866 /* 867 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 868 * from i.MX6 family when no link speed transition 869 * occurs and we go Gen1 -> yep, Gen1. The difference 870 * is that, in such case, it will not be cleared by HW 871 * which will cause the following code to report false 872 * failure. 873 */ 874 875 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 876 if (ret) { 877 dev_err(dev, "Failed to bring link up!\n"); 878 goto err_reset_phy; 879 } 880 } 881 882 /* Make sure link training is finished as well! */ 883 ret = dw_pcie_wait_for_link(pci); 884 if (ret) 885 goto err_reset_phy; 886 } else { 887 dev_info(dev, "Link: Only Gen1 is enabled\n"); 888 } 889 890 imx6_pcie->link_is_up = true; 891 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 892 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 893 return 0; 894 895 err_reset_phy: 896 imx6_pcie->link_is_up = false; 897 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 898 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 899 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 900 imx6_pcie_reset_phy(imx6_pcie); 901 return 0; 902 } 903 904 static void imx6_pcie_stop_link(struct dw_pcie *pci) 905 { 906 struct device *dev = pci->dev; 907 908 /* Turn off PCIe LTSSM */ 909 imx6_pcie_ltssm_disable(dev); 910 } 911 912 static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 913 { 914 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 915 struct device *dev = pci->dev; 916 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 917 int ret; 918 919 if (imx6_pcie->vpcie) { 920 ret = regulator_enable(imx6_pcie->vpcie); 921 if (ret) { 922 dev_err(dev, "failed to enable vpcie regulator: %d\n", 923 ret); 924 return ret; 925 } 926 } 927 928 imx6_pcie_assert_core_reset(imx6_pcie); 929 imx6_pcie_init_phy(imx6_pcie); 930 931 ret = imx6_pcie_clk_enable(imx6_pcie); 932 if (ret) { 933 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 934 goto err_reg_disable; 935 } 936 937 if (imx6_pcie->phy) { 938 ret = phy_power_on(imx6_pcie->phy); 939 if (ret) { 940 dev_err(dev, "pcie PHY power up failed\n"); 941 goto err_clk_disable; 942 } 943 } 944 945 ret = imx6_pcie_deassert_core_reset(imx6_pcie); 946 if (ret < 0) { 947 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 948 goto err_phy_off; 949 } 950 951 if (imx6_pcie->phy) { 952 ret = phy_init(imx6_pcie->phy); 953 if (ret) { 954 dev_err(dev, "waiting for PHY ready timeout!\n"); 955 goto err_phy_off; 956 } 957 } 958 imx6_setup_phy_mpll(imx6_pcie); 959 960 return 0; 961 962 err_phy_off: 963 if (imx6_pcie->phy) 964 phy_power_off(imx6_pcie->phy); 965 err_clk_disable: 966 imx6_pcie_clk_disable(imx6_pcie); 967 err_reg_disable: 968 if (imx6_pcie->vpcie) 969 regulator_disable(imx6_pcie->vpcie); 970 return ret; 971 } 972 973 static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 974 { 975 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 976 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 977 978 if (imx6_pcie->phy) { 979 if (phy_power_off(imx6_pcie->phy)) 980 dev_err(pci->dev, "unable to power off PHY\n"); 981 phy_exit(imx6_pcie->phy); 982 } 983 imx6_pcie_clk_disable(imx6_pcie); 984 985 if (imx6_pcie->vpcie) 986 regulator_disable(imx6_pcie->vpcie); 987 } 988 989 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 990 .host_init = imx6_pcie_host_init, 991 }; 992 993 static const struct dw_pcie_ops dw_pcie_ops = { 994 .start_link = imx6_pcie_start_link, 995 }; 996 997 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 998 { 999 struct device *dev = imx6_pcie->pci->dev; 1000 1001 /* Some variants have a turnoff reset in DT */ 1002 if (imx6_pcie->turnoff_reset) { 1003 reset_control_assert(imx6_pcie->turnoff_reset); 1004 reset_control_deassert(imx6_pcie->turnoff_reset); 1005 goto pm_turnoff_sleep; 1006 } 1007 1008 /* Others poke directly at IOMUXC registers */ 1009 switch (imx6_pcie->drvdata->variant) { 1010 case IMX6SX: 1011 case IMX6QP: 1012 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1013 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 1014 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 1015 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1016 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 1017 break; 1018 default: 1019 dev_err(dev, "PME_Turn_Off not implemented\n"); 1020 return; 1021 } 1022 1023 /* 1024 * Components with an upstream port must respond to 1025 * PME_Turn_Off with PME_TO_Ack but we can't check. 1026 * 1027 * The standard recommends a 1-10ms timeout after which to 1028 * proceed anyway as if acks were received. 1029 */ 1030 pm_turnoff_sleep: 1031 usleep_range(1000, 10000); 1032 } 1033 1034 static int imx6_pcie_suspend_noirq(struct device *dev) 1035 { 1036 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1037 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1038 1039 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1040 return 0; 1041 1042 imx6_pcie_pm_turnoff(imx6_pcie); 1043 imx6_pcie_stop_link(imx6_pcie->pci); 1044 imx6_pcie_host_exit(pp); 1045 1046 return 0; 1047 } 1048 1049 static int imx6_pcie_resume_noirq(struct device *dev) 1050 { 1051 int ret; 1052 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1053 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1054 1055 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1056 return 0; 1057 1058 ret = imx6_pcie_host_init(pp); 1059 if (ret) 1060 return ret; 1061 dw_pcie_setup_rc(pp); 1062 1063 if (imx6_pcie->link_is_up) 1064 imx6_pcie_start_link(imx6_pcie->pci); 1065 1066 return 0; 1067 } 1068 1069 static const struct dev_pm_ops imx6_pcie_pm_ops = { 1070 NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1071 imx6_pcie_resume_noirq) 1072 }; 1073 1074 static int imx6_pcie_probe(struct platform_device *pdev) 1075 { 1076 struct device *dev = &pdev->dev; 1077 struct dw_pcie *pci; 1078 struct imx6_pcie *imx6_pcie; 1079 struct device_node *np; 1080 struct resource *dbi_base; 1081 struct device_node *node = dev->of_node; 1082 int ret; 1083 u16 val; 1084 1085 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1086 if (!imx6_pcie) 1087 return -ENOMEM; 1088 1089 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1090 if (!pci) 1091 return -ENOMEM; 1092 1093 pci->dev = dev; 1094 pci->ops = &dw_pcie_ops; 1095 pci->pp.ops = &imx6_pcie_host_ops; 1096 1097 imx6_pcie->pci = pci; 1098 imx6_pcie->drvdata = of_device_get_match_data(dev); 1099 1100 /* Find the PHY if one is defined, only imx7d uses it */ 1101 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1102 if (np) { 1103 struct resource res; 1104 1105 ret = of_address_to_resource(np, 0, &res); 1106 if (ret) { 1107 dev_err(dev, "Unable to map PCIe PHY\n"); 1108 return ret; 1109 } 1110 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1111 if (IS_ERR(imx6_pcie->phy_base)) 1112 return PTR_ERR(imx6_pcie->phy_base); 1113 } 1114 1115 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1116 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); 1117 if (IS_ERR(pci->dbi_base)) 1118 return PTR_ERR(pci->dbi_base); 1119 1120 /* Fetch GPIOs */ 1121 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 1122 imx6_pcie->gpio_active_high = of_property_read_bool(node, 1123 "reset-gpio-active-high"); 1124 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 1125 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 1126 imx6_pcie->gpio_active_high ? 1127 GPIOF_OUT_INIT_HIGH : 1128 GPIOF_OUT_INIT_LOW, 1129 "PCIe reset"); 1130 if (ret) { 1131 dev_err(dev, "unable to get reset gpio\n"); 1132 return ret; 1133 } 1134 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 1135 return imx6_pcie->reset_gpio; 1136 } 1137 1138 /* Fetch clocks */ 1139 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); 1140 if (IS_ERR(imx6_pcie->pcie_bus)) 1141 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), 1142 "pcie_bus clock source missing or invalid\n"); 1143 1144 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); 1145 if (IS_ERR(imx6_pcie->pcie)) 1146 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), 1147 "pcie clock source missing or invalid\n"); 1148 1149 switch (imx6_pcie->drvdata->variant) { 1150 case IMX6SX: 1151 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, 1152 "pcie_inbound_axi"); 1153 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) 1154 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), 1155 "pcie_inbound_axi clock missing or invalid\n"); 1156 break; 1157 case IMX8MQ: 1158 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1159 if (IS_ERR(imx6_pcie->pcie_aux)) 1160 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1161 "pcie_aux clock source missing or invalid\n"); 1162 fallthrough; 1163 case IMX7D: 1164 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1165 imx6_pcie->controller_id = 1; 1166 1167 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, 1168 "pciephy"); 1169 if (IS_ERR(imx6_pcie->pciephy_reset)) { 1170 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 1171 return PTR_ERR(imx6_pcie->pciephy_reset); 1172 } 1173 1174 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1175 "apps"); 1176 if (IS_ERR(imx6_pcie->apps_reset)) { 1177 dev_err(dev, "Failed to get PCIE APPS reset control\n"); 1178 return PTR_ERR(imx6_pcie->apps_reset); 1179 } 1180 break; 1181 case IMX8MM: 1182 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); 1183 if (IS_ERR(imx6_pcie->pcie_aux)) 1184 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), 1185 "pcie_aux clock source missing or invalid\n"); 1186 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, 1187 "apps"); 1188 if (IS_ERR(imx6_pcie->apps_reset)) 1189 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 1190 "failed to get pcie apps reset control\n"); 1191 1192 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1193 if (IS_ERR(imx6_pcie->phy)) 1194 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 1195 "failed to get pcie phy\n"); 1196 1197 break; 1198 default: 1199 break; 1200 } 1201 /* Don't fetch the pcie_phy clock, if it has abstract PHY driver */ 1202 if (imx6_pcie->phy == NULL) { 1203 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); 1204 if (IS_ERR(imx6_pcie->pcie_phy)) 1205 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), 1206 "pcie_phy clock source missing or invalid\n"); 1207 } 1208 1209 1210 /* Grab turnoff reset */ 1211 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1212 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1213 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1214 return PTR_ERR(imx6_pcie->turnoff_reset); 1215 } 1216 1217 /* Grab GPR config register range */ 1218 imx6_pcie->iomuxc_gpr = 1219 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 1220 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1221 dev_err(dev, "unable to find iomuxc registers\n"); 1222 return PTR_ERR(imx6_pcie->iomuxc_gpr); 1223 } 1224 1225 /* Grab PCIe PHY Tx Settings */ 1226 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1227 &imx6_pcie->tx_deemph_gen1)) 1228 imx6_pcie->tx_deemph_gen1 = 0; 1229 1230 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1231 &imx6_pcie->tx_deemph_gen2_3p5db)) 1232 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1233 1234 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1235 &imx6_pcie->tx_deemph_gen2_6db)) 1236 imx6_pcie->tx_deemph_gen2_6db = 20; 1237 1238 if (of_property_read_u32(node, "fsl,tx-swing-full", 1239 &imx6_pcie->tx_swing_full)) 1240 imx6_pcie->tx_swing_full = 127; 1241 1242 if (of_property_read_u32(node, "fsl,tx-swing-low", 1243 &imx6_pcie->tx_swing_low)) 1244 imx6_pcie->tx_swing_low = 127; 1245 1246 /* Limit link speed */ 1247 pci->link_gen = 1; 1248 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1249 1250 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1251 if (IS_ERR(imx6_pcie->vpcie)) { 1252 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1253 return PTR_ERR(imx6_pcie->vpcie); 1254 imx6_pcie->vpcie = NULL; 1255 } 1256 1257 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1258 if (IS_ERR(imx6_pcie->vph)) { 1259 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1260 return PTR_ERR(imx6_pcie->vph); 1261 imx6_pcie->vph = NULL; 1262 } 1263 1264 platform_set_drvdata(pdev, imx6_pcie); 1265 1266 ret = imx6_pcie_attach_pd(dev); 1267 if (ret) 1268 return ret; 1269 1270 ret = dw_pcie_host_init(&pci->pp); 1271 if (ret < 0) 1272 return ret; 1273 1274 if (pci_msi_enabled()) { 1275 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1276 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1277 val |= PCI_MSI_FLAGS_ENABLE; 1278 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1279 } 1280 1281 return 0; 1282 } 1283 1284 static void imx6_pcie_shutdown(struct platform_device *pdev) 1285 { 1286 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1287 1288 /* bring down link, so bootloader gets clean state in case of reboot */ 1289 imx6_pcie_assert_core_reset(imx6_pcie); 1290 } 1291 1292 static const struct imx6_pcie_drvdata drvdata[] = { 1293 [IMX6Q] = { 1294 .variant = IMX6Q, 1295 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1296 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1297 .dbi_length = 0x200, 1298 }, 1299 [IMX6SX] = { 1300 .variant = IMX6SX, 1301 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1302 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1303 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1304 }, 1305 [IMX6QP] = { 1306 .variant = IMX6QP, 1307 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1308 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1309 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1310 .dbi_length = 0x200, 1311 }, 1312 [IMX7D] = { 1313 .variant = IMX7D, 1314 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1315 }, 1316 [IMX8MQ] = { 1317 .variant = IMX8MQ, 1318 }, 1319 [IMX8MM] = { 1320 .variant = IMX8MM, 1321 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1322 }, 1323 }; 1324 1325 static const struct of_device_id imx6_pcie_of_match[] = { 1326 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1327 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1328 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1329 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1330 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1331 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 1332 {}, 1333 }; 1334 1335 static struct platform_driver imx6_pcie_driver = { 1336 .driver = { 1337 .name = "imx6q-pcie", 1338 .of_match_table = imx6_pcie_of_match, 1339 .suppress_bind_attrs = true, 1340 .pm = &imx6_pcie_pm_ops, 1341 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1342 }, 1343 .probe = imx6_pcie_probe, 1344 .shutdown = imx6_pcie_shutdown, 1345 }; 1346 1347 static void imx6_pcie_quirk(struct pci_dev *dev) 1348 { 1349 struct pci_bus *bus = dev->bus; 1350 struct dw_pcie_rp *pp = bus->sysdata; 1351 1352 /* Bus parent is the PCI bridge, its parent is this platform driver */ 1353 if (!bus->dev.parent || !bus->dev.parent->parent) 1354 return; 1355 1356 /* Make sure we only quirk devices associated with this driver */ 1357 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1358 return; 1359 1360 if (pci_is_root_bus(bus)) { 1361 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1362 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1363 1364 /* 1365 * Limit config length to avoid the kernel reading beyond 1366 * the register set and causing an abort on i.MX 6Quad 1367 */ 1368 if (imx6_pcie->drvdata->dbi_length) { 1369 dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1370 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1371 dev->cfg_size); 1372 } 1373 } 1374 } 1375 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1376 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1377 1378 static int __init imx6_pcie_init(void) 1379 { 1380 #ifdef CONFIG_ARM 1381 /* 1382 * Since probe() can be deferred we need to make sure that 1383 * hook_fault_code is not called after __init memory is freed 1384 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1385 * we can install the handler here without risking it 1386 * accessing some uninitialized driver state. 1387 */ 1388 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1389 "external abort on non-linefetch"); 1390 #endif 1391 1392 return platform_driver_register(&imx6_pcie_driver); 1393 } 1394 device_initcall(imx6_pcie_init); 1395