1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Kishon Vijay Abraham I <kishon@ti.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/of_device.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of_pci.h> 21 #include <linux/pci.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/resource.h> 26 #include <linux/types.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 #include <linux/gpio/consumer.h> 30 31 #include "../../pci.h" 32 #include "pcie-designware.h" 33 34 /* PCIe controller wrapper DRA7XX configuration registers */ 35 36 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 37 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 38 #define ERR_SYS BIT(0) 39 #define ERR_FATAL BIT(1) 40 #define ERR_NONFATAL BIT(2) 41 #define ERR_COR BIT(3) 42 #define ERR_AXI BIT(4) 43 #define ERR_ECRC BIT(5) 44 #define PME_TURN_OFF BIT(8) 45 #define PME_TO_ACK BIT(9) 46 #define PM_PME BIT(10) 47 #define LINK_REQ_RST BIT(11) 48 #define LINK_UP_EVT BIT(12) 49 #define CFG_BME_EVT BIT(13) 50 #define CFG_MSE_EVT BIT(14) 51 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \ 52 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \ 53 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT) 54 55 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034 56 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038 57 #define INTA BIT(0) 58 #define INTB BIT(1) 59 #define INTC BIT(2) 60 #define INTD BIT(3) 61 #define MSI BIT(4) 62 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD) 63 64 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100 65 #define DEVICE_TYPE_EP 0x0 66 #define DEVICE_TYPE_LEG_EP 0x1 67 #define DEVICE_TYPE_RC 0x4 68 69 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104 70 #define LTSSM_EN 0x1 71 72 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C 73 #define LINK_UP BIT(16) 74 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF 75 76 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 77 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 78 79 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c 80 #define MSI_REQ_GRANT BIT(0) 81 #define MSI_VECTOR_SHIFT 7 82 83 #define PCIE_1LANE_2LANE_SELECTION BIT(13) 84 #define PCIE_B1C0_MODE_SEL BIT(2) 85 #define PCIE_B0_B1_TSYNCEN BIT(0) 86 87 struct dra7xx_pcie { 88 struct dw_pcie *pci; 89 void __iomem *base; /* DT ti_conf */ 90 int phy_count; /* DT phy-names count */ 91 struct phy **phy; 92 struct irq_domain *irq_domain; 93 enum dw_pcie_device_mode mode; 94 }; 95 96 struct dra7xx_pcie_of_data { 97 enum dw_pcie_device_mode mode; 98 u32 b1co_mode_sel_mask; 99 }; 100 101 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) 102 103 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) 104 { 105 return readl(pcie->base + offset); 106 } 107 108 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, 109 u32 value) 110 { 111 writel(value, pcie->base + offset); 112 } 113 114 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr) 115 { 116 return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; 117 } 118 119 static int dra7xx_pcie_link_up(struct dw_pcie *pci) 120 { 121 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 122 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); 123 124 return !!(reg & LINK_UP); 125 } 126 127 static void dra7xx_pcie_stop_link(struct dw_pcie *pci) 128 { 129 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 130 u32 reg; 131 132 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 133 reg &= ~LTSSM_EN; 134 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 135 } 136 137 static int dra7xx_pcie_establish_link(struct dw_pcie *pci) 138 { 139 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 140 struct device *dev = pci->dev; 141 u32 reg; 142 143 if (dw_pcie_link_up(pci)) { 144 dev_err(dev, "link is already up\n"); 145 return 0; 146 } 147 148 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 149 reg |= LTSSM_EN; 150 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 151 152 return 0; 153 } 154 155 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) 156 { 157 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, 158 LEG_EP_INTERRUPTS | MSI); 159 160 dra7xx_pcie_writel(dra7xx, 161 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, 162 MSI | LEG_EP_INTERRUPTS); 163 } 164 165 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) 166 { 167 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, 168 INTERRUPTS); 169 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, 170 INTERRUPTS); 171 } 172 173 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) 174 { 175 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 176 dra7xx_pcie_enable_msi_interrupts(dra7xx); 177 } 178 179 static int dra7xx_pcie_host_init(struct pcie_port *pp) 180 { 181 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 182 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 183 184 dra7xx_pcie_enable_interrupts(dra7xx); 185 186 return 0; 187 } 188 189 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 190 irq_hw_number_t hwirq) 191 { 192 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 193 irq_set_chip_data(irq, domain->host_data); 194 195 return 0; 196 } 197 198 static const struct irq_domain_ops intx_domain_ops = { 199 .map = dra7xx_pcie_intx_map, 200 .xlate = pci_irqd_intx_xlate, 201 }; 202 203 static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index) 204 { 205 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 206 unsigned long val; 207 int pos; 208 209 val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + 210 (index * MSI_REG_CTRL_BLOCK_SIZE)); 211 if (!val) 212 return 0; 213 214 pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 0); 215 while (pos != MAX_MSI_IRQS_PER_CTRL) { 216 generic_handle_domain_irq(pp->irq_domain, 217 (index * MAX_MSI_IRQS_PER_CTRL) + pos); 218 pos++; 219 pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos); 220 } 221 222 return 1; 223 } 224 225 static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp) 226 { 227 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 228 int ret, i, count, num_ctrls; 229 230 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 231 232 /** 233 * Need to make sure all MSI status bits read 0 before exiting. 234 * Else, new MSI IRQs are not registered by the wrapper. Have an 235 * upperbound for the loop and exit the IRQ in case of IRQ flood 236 * to avoid locking up system in interrupt context. 237 */ 238 count = 0; 239 do { 240 ret = 0; 241 242 for (i = 0; i < num_ctrls; i++) 243 ret |= dra7xx_pcie_handle_msi(pp, i); 244 count++; 245 } while (ret && count <= 1000); 246 247 if (count > 1000) 248 dev_warn_ratelimited(pci->dev, 249 "Too many MSI IRQs to handle\n"); 250 } 251 252 static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc) 253 { 254 struct irq_chip *chip = irq_desc_get_chip(desc); 255 struct dra7xx_pcie *dra7xx; 256 struct dw_pcie *pci; 257 struct pcie_port *pp; 258 unsigned long reg; 259 u32 bit; 260 261 chained_irq_enter(chip, desc); 262 263 pp = irq_desc_get_handler_data(desc); 264 pci = to_dw_pcie_from_pp(pp); 265 dra7xx = to_dra7xx_pcie(pci); 266 267 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); 268 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); 269 270 switch (reg) { 271 case MSI: 272 dra7xx_pcie_handle_msi_irq(pp); 273 break; 274 case INTA: 275 case INTB: 276 case INTC: 277 case INTD: 278 for_each_set_bit(bit, ®, PCI_NUM_INTX) 279 generic_handle_domain_irq(dra7xx->irq_domain, bit); 280 break; 281 } 282 283 chained_irq_exit(chip, desc); 284 } 285 286 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) 287 { 288 struct dra7xx_pcie *dra7xx = arg; 289 struct dw_pcie *pci = dra7xx->pci; 290 struct device *dev = pci->dev; 291 struct dw_pcie_ep *ep = &pci->ep; 292 u32 reg; 293 294 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); 295 296 if (reg & ERR_SYS) 297 dev_dbg(dev, "System Error\n"); 298 299 if (reg & ERR_FATAL) 300 dev_dbg(dev, "Fatal Error\n"); 301 302 if (reg & ERR_NONFATAL) 303 dev_dbg(dev, "Non Fatal Error\n"); 304 305 if (reg & ERR_COR) 306 dev_dbg(dev, "Correctable Error\n"); 307 308 if (reg & ERR_AXI) 309 dev_dbg(dev, "AXI tag lookup fatal Error\n"); 310 311 if (reg & ERR_ECRC) 312 dev_dbg(dev, "ECRC Error\n"); 313 314 if (reg & PME_TURN_OFF) 315 dev_dbg(dev, 316 "Power Management Event Turn-Off message received\n"); 317 318 if (reg & PME_TO_ACK) 319 dev_dbg(dev, 320 "Power Management Turn-Off Ack message received\n"); 321 322 if (reg & PM_PME) 323 dev_dbg(dev, "PM Power Management Event message received\n"); 324 325 if (reg & LINK_REQ_RST) 326 dev_dbg(dev, "Link Request Reset\n"); 327 328 if (reg & LINK_UP_EVT) { 329 if (dra7xx->mode == DW_PCIE_EP_TYPE) 330 dw_pcie_ep_linkup(ep); 331 dev_dbg(dev, "Link-up state change\n"); 332 } 333 334 if (reg & CFG_BME_EVT) 335 dev_dbg(dev, "CFG 'Bus Master Enable' change\n"); 336 337 if (reg & CFG_MSE_EVT) 338 dev_dbg(dev, "CFG 'Memory Space Enable' change\n"); 339 340 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); 341 342 return IRQ_HANDLED; 343 } 344 345 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) 346 { 347 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 348 struct device *dev = pci->dev; 349 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 350 struct device_node *node = dev->of_node; 351 struct device_node *pcie_intc_node = of_get_next_child(node, NULL); 352 353 if (!pcie_intc_node) { 354 dev_err(dev, "No PCIe Intc node found\n"); 355 return -ENODEV; 356 } 357 358 irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler, 359 pp); 360 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 361 &intx_domain_ops, pp); 362 of_node_put(pcie_intc_node); 363 if (!dra7xx->irq_domain) { 364 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 365 return -ENODEV; 366 } 367 368 return 0; 369 } 370 371 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { 372 .host_init = dra7xx_pcie_host_init, 373 }; 374 375 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) 376 { 377 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 378 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 379 enum pci_barno bar; 380 381 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 382 dw_pcie_ep_reset_bar(pci, bar); 383 384 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 385 } 386 387 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx) 388 { 389 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1); 390 mdelay(1); 391 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1); 392 } 393 394 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, 395 u8 interrupt_num) 396 { 397 u32 reg; 398 399 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT; 400 reg |= MSI_REQ_GRANT; 401 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg); 402 } 403 404 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 405 enum pci_epc_irq_type type, u16 interrupt_num) 406 { 407 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 408 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 409 410 switch (type) { 411 case PCI_EPC_IRQ_LEGACY: 412 dra7xx_pcie_raise_legacy_irq(dra7xx); 413 break; 414 case PCI_EPC_IRQ_MSI: 415 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num); 416 break; 417 default: 418 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 419 } 420 421 return 0; 422 } 423 424 static const struct pci_epc_features dra7xx_pcie_epc_features = { 425 .linkup_notifier = true, 426 .msi_capable = true, 427 .msix_capable = false, 428 }; 429 430 static const struct pci_epc_features* 431 dra7xx_pcie_get_features(struct dw_pcie_ep *ep) 432 { 433 return &dra7xx_pcie_epc_features; 434 } 435 436 static const struct dw_pcie_ep_ops pcie_ep_ops = { 437 .ep_init = dra7xx_pcie_ep_init, 438 .raise_irq = dra7xx_pcie_raise_irq, 439 .get_features = dra7xx_pcie_get_features, 440 }; 441 442 static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, 443 struct platform_device *pdev) 444 { 445 int ret; 446 struct dw_pcie_ep *ep; 447 struct device *dev = &pdev->dev; 448 struct dw_pcie *pci = dra7xx->pci; 449 450 ep = &pci->ep; 451 ep->ops = &pcie_ep_ops; 452 453 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics"); 454 if (IS_ERR(pci->dbi_base)) 455 return PTR_ERR(pci->dbi_base); 456 457 pci->dbi_base2 = 458 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2"); 459 if (IS_ERR(pci->dbi_base2)) 460 return PTR_ERR(pci->dbi_base2); 461 462 ret = dw_pcie_ep_init(ep); 463 if (ret) { 464 dev_err(dev, "failed to initialize endpoint\n"); 465 return ret; 466 } 467 468 return 0; 469 } 470 471 static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 472 struct platform_device *pdev) 473 { 474 int ret; 475 struct dw_pcie *pci = dra7xx->pci; 476 struct pcie_port *pp = &pci->pp; 477 struct device *dev = pci->dev; 478 479 pp->irq = platform_get_irq(pdev, 1); 480 if (pp->irq < 0) 481 return pp->irq; 482 483 /* MSI IRQ is muxed */ 484 pp->msi_irq = -ENODEV; 485 486 ret = dra7xx_pcie_init_irq_domain(pp); 487 if (ret < 0) 488 return ret; 489 490 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics"); 491 if (IS_ERR(pci->dbi_base)) 492 return PTR_ERR(pci->dbi_base); 493 494 pp->ops = &dra7xx_pcie_host_ops; 495 496 ret = dw_pcie_host_init(pp); 497 if (ret) { 498 dev_err(dev, "failed to initialize host\n"); 499 return ret; 500 } 501 502 return 0; 503 } 504 505 static const struct dw_pcie_ops dw_pcie_ops = { 506 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, 507 .start_link = dra7xx_pcie_establish_link, 508 .stop_link = dra7xx_pcie_stop_link, 509 .link_up = dra7xx_pcie_link_up, 510 }; 511 512 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) 513 { 514 int phy_count = dra7xx->phy_count; 515 516 while (phy_count--) { 517 phy_power_off(dra7xx->phy[phy_count]); 518 phy_exit(dra7xx->phy[phy_count]); 519 } 520 } 521 522 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) 523 { 524 int phy_count = dra7xx->phy_count; 525 int ret; 526 int i; 527 528 for (i = 0; i < phy_count; i++) { 529 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE); 530 if (ret < 0) 531 goto err_phy; 532 533 ret = phy_init(dra7xx->phy[i]); 534 if (ret < 0) 535 goto err_phy; 536 537 ret = phy_power_on(dra7xx->phy[i]); 538 if (ret < 0) { 539 phy_exit(dra7xx->phy[i]); 540 goto err_phy; 541 } 542 } 543 544 return 0; 545 546 err_phy: 547 while (--i >= 0) { 548 phy_power_off(dra7xx->phy[i]); 549 phy_exit(dra7xx->phy[i]); 550 } 551 552 return ret; 553 } 554 555 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = { 556 .mode = DW_PCIE_RC_TYPE, 557 }; 558 559 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { 560 .mode = DW_PCIE_EP_TYPE, 561 }; 562 563 static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = { 564 .b1co_mode_sel_mask = BIT(2), 565 .mode = DW_PCIE_RC_TYPE, 566 }; 567 568 static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = { 569 .b1co_mode_sel_mask = GENMASK(3, 2), 570 .mode = DW_PCIE_RC_TYPE, 571 }; 572 573 static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = { 574 .b1co_mode_sel_mask = BIT(2), 575 .mode = DW_PCIE_EP_TYPE, 576 }; 577 578 static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = { 579 .b1co_mode_sel_mask = GENMASK(3, 2), 580 .mode = DW_PCIE_EP_TYPE, 581 }; 582 583 static const struct of_device_id of_dra7xx_pcie_match[] = { 584 { 585 .compatible = "ti,dra7-pcie", 586 .data = &dra7xx_pcie_rc_of_data, 587 }, 588 { 589 .compatible = "ti,dra7-pcie-ep", 590 .data = &dra7xx_pcie_ep_of_data, 591 }, 592 { 593 .compatible = "ti,dra746-pcie-rc", 594 .data = &dra746_pcie_rc_of_data, 595 }, 596 { 597 .compatible = "ti,dra726-pcie-rc", 598 .data = &dra726_pcie_rc_of_data, 599 }, 600 { 601 .compatible = "ti,dra746-pcie-ep", 602 .data = &dra746_pcie_ep_of_data, 603 }, 604 { 605 .compatible = "ti,dra726-pcie-ep", 606 .data = &dra726_pcie_ep_of_data, 607 }, 608 {}, 609 }; 610 611 /* 612 * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 613 * @dra7xx: the dra7xx device where the workaround should be applied 614 * 615 * Access to the PCIe slave port that are not 32-bit aligned will result 616 * in incorrect mapping to TLP Address and Byte enable fields. Therefore, 617 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or 618 * 0x3. 619 * 620 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. 621 */ 622 static int dra7xx_pcie_unaligned_memaccess(struct device *dev) 623 { 624 int ret; 625 struct device_node *np = dev->of_node; 626 struct of_phandle_args args; 627 struct regmap *regmap; 628 629 regmap = syscon_regmap_lookup_by_phandle(np, 630 "ti,syscon-unaligned-access"); 631 if (IS_ERR(regmap)) { 632 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); 633 return -EINVAL; 634 } 635 636 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access", 637 2, 0, &args); 638 if (ret) { 639 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n"); 640 return ret; 641 } 642 643 ret = regmap_update_bits(regmap, args.args[0], args.args[1], 644 args.args[1]); 645 if (ret) 646 dev_err(dev, "failed to enable unaligned access\n"); 647 648 of_node_put(args.np); 649 650 return ret; 651 } 652 653 static int dra7xx_pcie_configure_two_lane(struct device *dev, 654 u32 b1co_mode_sel_mask) 655 { 656 struct device_node *np = dev->of_node; 657 struct regmap *pcie_syscon; 658 unsigned int pcie_reg; 659 u32 mask; 660 u32 val; 661 662 pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel"); 663 if (IS_ERR(pcie_syscon)) { 664 dev_err(dev, "unable to get ti,syscon-lane-sel\n"); 665 return -EINVAL; 666 } 667 668 if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1, 669 &pcie_reg)) { 670 dev_err(dev, "couldn't get lane selection reg offset\n"); 671 return -EINVAL; 672 } 673 674 mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN; 675 val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN; 676 regmap_update_bits(pcie_syscon, pcie_reg, mask, val); 677 678 return 0; 679 } 680 681 static int dra7xx_pcie_probe(struct platform_device *pdev) 682 { 683 u32 reg; 684 int ret; 685 int irq; 686 int i; 687 int phy_count; 688 struct phy **phy; 689 struct device_link **link; 690 void __iomem *base; 691 struct dw_pcie *pci; 692 struct dra7xx_pcie *dra7xx; 693 struct device *dev = &pdev->dev; 694 struct device_node *np = dev->of_node; 695 char name[10]; 696 struct gpio_desc *reset; 697 const struct of_device_id *match; 698 const struct dra7xx_pcie_of_data *data; 699 enum dw_pcie_device_mode mode; 700 u32 b1co_mode_sel_mask; 701 702 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); 703 if (!match) 704 return -EINVAL; 705 706 data = (struct dra7xx_pcie_of_data *)match->data; 707 mode = (enum dw_pcie_device_mode)data->mode; 708 b1co_mode_sel_mask = data->b1co_mode_sel_mask; 709 710 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); 711 if (!dra7xx) 712 return -ENOMEM; 713 714 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 715 if (!pci) 716 return -ENOMEM; 717 718 pci->dev = dev; 719 pci->ops = &dw_pcie_ops; 720 721 irq = platform_get_irq(pdev, 0); 722 if (irq < 0) 723 return irq; 724 725 base = devm_platform_ioremap_resource_byname(pdev, "ti_conf"); 726 if (IS_ERR(base)) 727 return PTR_ERR(base); 728 729 phy_count = of_property_count_strings(np, "phy-names"); 730 if (phy_count < 0) { 731 dev_err(dev, "unable to find the strings\n"); 732 return phy_count; 733 } 734 735 phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); 736 if (!phy) 737 return -ENOMEM; 738 739 link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); 740 if (!link) 741 return -ENOMEM; 742 743 for (i = 0; i < phy_count; i++) { 744 snprintf(name, sizeof(name), "pcie-phy%d", i); 745 phy[i] = devm_phy_get(dev, name); 746 if (IS_ERR(phy[i])) 747 return PTR_ERR(phy[i]); 748 749 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 750 if (!link[i]) { 751 ret = -EINVAL; 752 goto err_link; 753 } 754 } 755 756 dra7xx->base = base; 757 dra7xx->phy = phy; 758 dra7xx->pci = pci; 759 dra7xx->phy_count = phy_count; 760 761 if (phy_count == 2) { 762 ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask); 763 if (ret < 0) 764 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */ 765 } 766 767 ret = dra7xx_pcie_enable_phy(dra7xx); 768 if (ret) { 769 dev_err(dev, "failed to enable phy\n"); 770 return ret; 771 } 772 773 platform_set_drvdata(pdev, dra7xx); 774 775 pm_runtime_enable(dev); 776 ret = pm_runtime_get_sync(dev); 777 if (ret < 0) { 778 dev_err(dev, "pm_runtime_get_sync failed\n"); 779 goto err_get_sync; 780 } 781 782 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); 783 if (IS_ERR(reset)) { 784 ret = PTR_ERR(reset); 785 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 786 goto err_gpio; 787 } 788 789 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 790 reg &= ~LTSSM_EN; 791 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 792 793 switch (mode) { 794 case DW_PCIE_RC_TYPE: 795 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) { 796 ret = -ENODEV; 797 goto err_gpio; 798 } 799 800 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, 801 DEVICE_TYPE_RC); 802 803 ret = dra7xx_pcie_unaligned_memaccess(dev); 804 if (ret) 805 dev_err(dev, "WA for Errata i870 not applied\n"); 806 807 ret = dra7xx_add_pcie_port(dra7xx, pdev); 808 if (ret < 0) 809 goto err_gpio; 810 break; 811 case DW_PCIE_EP_TYPE: 812 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) { 813 ret = -ENODEV; 814 goto err_gpio; 815 } 816 817 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, 818 DEVICE_TYPE_EP); 819 820 ret = dra7xx_pcie_unaligned_memaccess(dev); 821 if (ret) 822 goto err_gpio; 823 824 ret = dra7xx_add_pcie_ep(dra7xx, pdev); 825 if (ret < 0) 826 goto err_gpio; 827 break; 828 default: 829 dev_err(dev, "INVALID device type %d\n", mode); 830 } 831 dra7xx->mode = mode; 832 833 ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, 834 IRQF_SHARED, "dra7xx-pcie-main", dra7xx); 835 if (ret) { 836 dev_err(dev, "failed to request irq\n"); 837 goto err_gpio; 838 } 839 840 return 0; 841 842 err_gpio: 843 err_get_sync: 844 pm_runtime_put(dev); 845 pm_runtime_disable(dev); 846 dra7xx_pcie_disable_phy(dra7xx); 847 848 err_link: 849 while (--i >= 0) 850 device_link_del(link[i]); 851 852 return ret; 853 } 854 855 #ifdef CONFIG_PM_SLEEP 856 static int dra7xx_pcie_suspend(struct device *dev) 857 { 858 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 859 struct dw_pcie *pci = dra7xx->pci; 860 u32 val; 861 862 if (dra7xx->mode != DW_PCIE_RC_TYPE) 863 return 0; 864 865 /* clear MSE */ 866 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 867 val &= ~PCI_COMMAND_MEMORY; 868 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 869 870 return 0; 871 } 872 873 static int dra7xx_pcie_resume(struct device *dev) 874 { 875 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 876 struct dw_pcie *pci = dra7xx->pci; 877 u32 val; 878 879 if (dra7xx->mode != DW_PCIE_RC_TYPE) 880 return 0; 881 882 /* set MSE */ 883 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 884 val |= PCI_COMMAND_MEMORY; 885 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 886 887 return 0; 888 } 889 890 static int dra7xx_pcie_suspend_noirq(struct device *dev) 891 { 892 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 893 894 dra7xx_pcie_disable_phy(dra7xx); 895 896 return 0; 897 } 898 899 static int dra7xx_pcie_resume_noirq(struct device *dev) 900 { 901 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 902 int ret; 903 904 ret = dra7xx_pcie_enable_phy(dra7xx); 905 if (ret) { 906 dev_err(dev, "failed to enable phy\n"); 907 return ret; 908 } 909 910 return 0; 911 } 912 #endif 913 914 static void dra7xx_pcie_shutdown(struct platform_device *pdev) 915 { 916 struct device *dev = &pdev->dev; 917 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 918 int ret; 919 920 dra7xx_pcie_stop_link(dra7xx->pci); 921 922 ret = pm_runtime_put_sync(dev); 923 if (ret < 0) 924 dev_dbg(dev, "pm_runtime_put_sync failed\n"); 925 926 pm_runtime_disable(dev); 927 dra7xx_pcie_disable_phy(dra7xx); 928 } 929 930 static const struct dev_pm_ops dra7xx_pcie_pm_ops = { 931 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume) 932 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq, 933 dra7xx_pcie_resume_noirq) 934 }; 935 936 static struct platform_driver dra7xx_pcie_driver = { 937 .probe = dra7xx_pcie_probe, 938 .driver = { 939 .name = "dra7-pcie", 940 .of_match_table = of_dra7xx_pcie_match, 941 .suppress_bind_attrs = true, 942 .pm = &dra7xx_pcie_pm_ops, 943 }, 944 .shutdown = dra7xx_pcie_shutdown, 945 }; 946 builtin_platform_driver(dra7xx_pcie_driver); 947