1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Kishon Vijay Abraham I <kishon@ti.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/of_device.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of_pci.h> 21 #include <linux/pci.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/resource.h> 26 #include <linux/types.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/regmap.h> 29 30 #include "../../pci.h" 31 #include "pcie-designware.h" 32 33 /* PCIe controller wrapper DRA7XX configuration registers */ 34 35 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 36 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 37 #define ERR_SYS BIT(0) 38 #define ERR_FATAL BIT(1) 39 #define ERR_NONFATAL BIT(2) 40 #define ERR_COR BIT(3) 41 #define ERR_AXI BIT(4) 42 #define ERR_ECRC BIT(5) 43 #define PME_TURN_OFF BIT(8) 44 #define PME_TO_ACK BIT(9) 45 #define PM_PME BIT(10) 46 #define LINK_REQ_RST BIT(11) 47 #define LINK_UP_EVT BIT(12) 48 #define CFG_BME_EVT BIT(13) 49 #define CFG_MSE_EVT BIT(14) 50 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \ 51 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \ 52 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT) 53 54 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034 55 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038 56 #define INTA BIT(0) 57 #define INTB BIT(1) 58 #define INTC BIT(2) 59 #define INTD BIT(3) 60 #define MSI BIT(4) 61 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD) 62 63 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100 64 #define DEVICE_TYPE_EP 0x0 65 #define DEVICE_TYPE_LEG_EP 0x1 66 #define DEVICE_TYPE_RC 0x4 67 68 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104 69 #define LTSSM_EN 0x1 70 71 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C 72 #define LINK_UP BIT(16) 73 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF 74 75 #define EXP_CAP_ID_OFFSET 0x70 76 77 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 78 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 79 80 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c 81 #define MSI_REQ_GRANT BIT(0) 82 #define MSI_VECTOR_SHIFT 7 83 84 #define PCIE_1LANE_2LANE_SELECTION BIT(13) 85 #define PCIE_B1C0_MODE_SEL BIT(2) 86 #define PCIE_B0_B1_TSYNCEN BIT(0) 87 88 struct dra7xx_pcie { 89 struct dw_pcie *pci; 90 void __iomem *base; /* DT ti_conf */ 91 int phy_count; /* DT phy-names count */ 92 struct phy **phy; 93 int link_gen; 94 struct irq_domain *irq_domain; 95 enum dw_pcie_device_mode mode; 96 }; 97 98 struct dra7xx_pcie_of_data { 99 enum dw_pcie_device_mode mode; 100 u32 b1co_mode_sel_mask; 101 }; 102 103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) 104 105 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) 106 { 107 return readl(pcie->base + offset); 108 } 109 110 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, 111 u32 value) 112 { 113 writel(value, pcie->base + offset); 114 } 115 116 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr) 117 { 118 return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; 119 } 120 121 static int dra7xx_pcie_link_up(struct dw_pcie *pci) 122 { 123 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 124 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); 125 126 return !!(reg & LINK_UP); 127 } 128 129 static void dra7xx_pcie_stop_link(struct dw_pcie *pci) 130 { 131 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 132 u32 reg; 133 134 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 135 reg &= ~LTSSM_EN; 136 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 137 } 138 139 static int dra7xx_pcie_establish_link(struct dw_pcie *pci) 140 { 141 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 142 struct device *dev = pci->dev; 143 u32 reg; 144 u32 exp_cap_off = EXP_CAP_ID_OFFSET; 145 146 if (dw_pcie_link_up(pci)) { 147 dev_err(dev, "link is already up\n"); 148 return 0; 149 } 150 151 if (dra7xx->link_gen == 1) { 152 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, 153 4, ®); 154 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { 155 reg &= ~((u32)PCI_EXP_LNKCAP_SLS); 156 reg |= PCI_EXP_LNKCAP_SLS_2_5GB; 157 dw_pcie_write(pci->dbi_base + exp_cap_off + 158 PCI_EXP_LNKCAP, 4, reg); 159 } 160 161 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, 162 2, ®); 163 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { 164 reg &= ~((u32)PCI_EXP_LNKCAP_SLS); 165 reg |= PCI_EXP_LNKCAP_SLS_2_5GB; 166 dw_pcie_write(pci->dbi_base + exp_cap_off + 167 PCI_EXP_LNKCTL2, 2, reg); 168 } 169 } 170 171 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 172 reg |= LTSSM_EN; 173 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 174 175 return 0; 176 } 177 178 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) 179 { 180 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, 181 LEG_EP_INTERRUPTS | MSI); 182 183 dra7xx_pcie_writel(dra7xx, 184 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, 185 MSI | LEG_EP_INTERRUPTS); 186 } 187 188 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) 189 { 190 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, 191 INTERRUPTS); 192 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, 193 INTERRUPTS); 194 } 195 196 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) 197 { 198 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 199 dra7xx_pcie_enable_msi_interrupts(dra7xx); 200 } 201 202 static int dra7xx_pcie_host_init(struct pcie_port *pp) 203 { 204 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 205 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 206 207 dw_pcie_setup_rc(pp); 208 209 dra7xx_pcie_establish_link(pci); 210 dw_pcie_wait_for_link(pci); 211 dw_pcie_msi_init(pp); 212 dra7xx_pcie_enable_interrupts(dra7xx); 213 214 return 0; 215 } 216 217 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { 218 .host_init = dra7xx_pcie_host_init, 219 }; 220 221 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 222 irq_hw_number_t hwirq) 223 { 224 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 225 irq_set_chip_data(irq, domain->host_data); 226 227 return 0; 228 } 229 230 static const struct irq_domain_ops intx_domain_ops = { 231 .map = dra7xx_pcie_intx_map, 232 .xlate = pci_irqd_intx_xlate, 233 }; 234 235 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) 236 { 237 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 238 struct device *dev = pci->dev; 239 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 240 struct device_node *node = dev->of_node; 241 struct device_node *pcie_intc_node = of_get_next_child(node, NULL); 242 243 if (!pcie_intc_node) { 244 dev_err(dev, "No PCIe Intc node found\n"); 245 return -ENODEV; 246 } 247 248 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 249 &intx_domain_ops, pp); 250 of_node_put(pcie_intc_node); 251 if (!dra7xx->irq_domain) { 252 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 253 return -ENODEV; 254 } 255 256 return 0; 257 } 258 259 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) 260 { 261 struct dra7xx_pcie *dra7xx = arg; 262 struct dw_pcie *pci = dra7xx->pci; 263 struct pcie_port *pp = &pci->pp; 264 unsigned long reg; 265 u32 virq, bit; 266 267 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); 268 269 switch (reg) { 270 case MSI: 271 dw_handle_msi_irq(pp); 272 break; 273 case INTA: 274 case INTB: 275 case INTC: 276 case INTD: 277 for_each_set_bit(bit, ®, PCI_NUM_INTX) { 278 virq = irq_find_mapping(dra7xx->irq_domain, bit); 279 if (virq) 280 generic_handle_irq(virq); 281 } 282 break; 283 } 284 285 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); 286 287 return IRQ_HANDLED; 288 } 289 290 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) 291 { 292 struct dra7xx_pcie *dra7xx = arg; 293 struct dw_pcie *pci = dra7xx->pci; 294 struct device *dev = pci->dev; 295 struct dw_pcie_ep *ep = &pci->ep; 296 u32 reg; 297 298 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); 299 300 if (reg & ERR_SYS) 301 dev_dbg(dev, "System Error\n"); 302 303 if (reg & ERR_FATAL) 304 dev_dbg(dev, "Fatal Error\n"); 305 306 if (reg & ERR_NONFATAL) 307 dev_dbg(dev, "Non Fatal Error\n"); 308 309 if (reg & ERR_COR) 310 dev_dbg(dev, "Correctable Error\n"); 311 312 if (reg & ERR_AXI) 313 dev_dbg(dev, "AXI tag lookup fatal Error\n"); 314 315 if (reg & ERR_ECRC) 316 dev_dbg(dev, "ECRC Error\n"); 317 318 if (reg & PME_TURN_OFF) 319 dev_dbg(dev, 320 "Power Management Event Turn-Off message received\n"); 321 322 if (reg & PME_TO_ACK) 323 dev_dbg(dev, 324 "Power Management Turn-Off Ack message received\n"); 325 326 if (reg & PM_PME) 327 dev_dbg(dev, "PM Power Management Event message received\n"); 328 329 if (reg & LINK_REQ_RST) 330 dev_dbg(dev, "Link Request Reset\n"); 331 332 if (reg & LINK_UP_EVT) { 333 if (dra7xx->mode == DW_PCIE_EP_TYPE) 334 dw_pcie_ep_linkup(ep); 335 dev_dbg(dev, "Link-up state change\n"); 336 } 337 338 if (reg & CFG_BME_EVT) 339 dev_dbg(dev, "CFG 'Bus Master Enable' change\n"); 340 341 if (reg & CFG_MSE_EVT) 342 dev_dbg(dev, "CFG 'Memory Space Enable' change\n"); 343 344 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); 345 346 return IRQ_HANDLED; 347 } 348 349 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) 350 { 351 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 352 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 353 enum pci_barno bar; 354 355 for (bar = BAR_0; bar <= BAR_5; bar++) 356 dw_pcie_ep_reset_bar(pci, bar); 357 358 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 359 } 360 361 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx) 362 { 363 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1); 364 mdelay(1); 365 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1); 366 } 367 368 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, 369 u8 interrupt_num) 370 { 371 u32 reg; 372 373 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT; 374 reg |= MSI_REQ_GRANT; 375 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg); 376 } 377 378 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 379 enum pci_epc_irq_type type, u16 interrupt_num) 380 { 381 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 382 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 383 384 switch (type) { 385 case PCI_EPC_IRQ_LEGACY: 386 dra7xx_pcie_raise_legacy_irq(dra7xx); 387 break; 388 case PCI_EPC_IRQ_MSI: 389 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num); 390 break; 391 default: 392 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 393 } 394 395 return 0; 396 } 397 398 static const struct pci_epc_features dra7xx_pcie_epc_features = { 399 .linkup_notifier = true, 400 .msi_capable = true, 401 .msix_capable = false, 402 }; 403 404 static const struct pci_epc_features* 405 dra7xx_pcie_get_features(struct dw_pcie_ep *ep) 406 { 407 return &dra7xx_pcie_epc_features; 408 } 409 410 static const struct dw_pcie_ep_ops pcie_ep_ops = { 411 .ep_init = dra7xx_pcie_ep_init, 412 .raise_irq = dra7xx_pcie_raise_irq, 413 .get_features = dra7xx_pcie_get_features, 414 }; 415 416 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, 417 struct platform_device *pdev) 418 { 419 int ret; 420 struct dw_pcie_ep *ep; 421 struct resource *res; 422 struct device *dev = &pdev->dev; 423 struct dw_pcie *pci = dra7xx->pci; 424 425 ep = &pci->ep; 426 ep->ops = &pcie_ep_ops; 427 428 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics"); 429 pci->dbi_base = devm_ioremap_resource(dev, res); 430 if (IS_ERR(pci->dbi_base)) 431 return PTR_ERR(pci->dbi_base); 432 433 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2"); 434 pci->dbi_base2 = devm_ioremap_resource(dev, res); 435 if (IS_ERR(pci->dbi_base2)) 436 return PTR_ERR(pci->dbi_base2); 437 438 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 439 if (!res) 440 return -EINVAL; 441 442 ep->phys_base = res->start; 443 ep->addr_size = resource_size(res); 444 445 ret = dw_pcie_ep_init(ep); 446 if (ret) { 447 dev_err(dev, "failed to initialize endpoint\n"); 448 return ret; 449 } 450 451 return 0; 452 } 453 454 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, 455 struct platform_device *pdev) 456 { 457 int ret; 458 struct dw_pcie *pci = dra7xx->pci; 459 struct pcie_port *pp = &pci->pp; 460 struct device *dev = pci->dev; 461 struct resource *res; 462 463 pp->irq = platform_get_irq(pdev, 1); 464 if (pp->irq < 0) { 465 dev_err(dev, "missing IRQ resource\n"); 466 return pp->irq; 467 } 468 469 ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler, 470 IRQF_SHARED | IRQF_NO_THREAD, 471 "dra7-pcie-msi", dra7xx); 472 if (ret) { 473 dev_err(dev, "failed to request irq\n"); 474 return ret; 475 } 476 477 ret = dra7xx_pcie_init_irq_domain(pp); 478 if (ret < 0) 479 return ret; 480 481 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics"); 482 pci->dbi_base = devm_ioremap_resource(dev, res); 483 if (IS_ERR(pci->dbi_base)) 484 return PTR_ERR(pci->dbi_base); 485 486 pp->ops = &dra7xx_pcie_host_ops; 487 488 ret = dw_pcie_host_init(pp); 489 if (ret) { 490 dev_err(dev, "failed to initialize host\n"); 491 return ret; 492 } 493 494 return 0; 495 } 496 497 static const struct dw_pcie_ops dw_pcie_ops = { 498 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, 499 .start_link = dra7xx_pcie_establish_link, 500 .stop_link = dra7xx_pcie_stop_link, 501 .link_up = dra7xx_pcie_link_up, 502 }; 503 504 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) 505 { 506 int phy_count = dra7xx->phy_count; 507 508 while (phy_count--) { 509 phy_power_off(dra7xx->phy[phy_count]); 510 phy_exit(dra7xx->phy[phy_count]); 511 } 512 } 513 514 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) 515 { 516 int phy_count = dra7xx->phy_count; 517 int ret; 518 int i; 519 520 for (i = 0; i < phy_count; i++) { 521 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE); 522 if (ret < 0) 523 goto err_phy; 524 525 ret = phy_init(dra7xx->phy[i]); 526 if (ret < 0) 527 goto err_phy; 528 529 ret = phy_power_on(dra7xx->phy[i]); 530 if (ret < 0) { 531 phy_exit(dra7xx->phy[i]); 532 goto err_phy; 533 } 534 } 535 536 return 0; 537 538 err_phy: 539 while (--i >= 0) { 540 phy_power_off(dra7xx->phy[i]); 541 phy_exit(dra7xx->phy[i]); 542 } 543 544 return ret; 545 } 546 547 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = { 548 .mode = DW_PCIE_RC_TYPE, 549 }; 550 551 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { 552 .mode = DW_PCIE_EP_TYPE, 553 }; 554 555 static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = { 556 .b1co_mode_sel_mask = BIT(2), 557 .mode = DW_PCIE_RC_TYPE, 558 }; 559 560 static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = { 561 .b1co_mode_sel_mask = GENMASK(3, 2), 562 .mode = DW_PCIE_RC_TYPE, 563 }; 564 565 static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = { 566 .b1co_mode_sel_mask = BIT(2), 567 .mode = DW_PCIE_EP_TYPE, 568 }; 569 570 static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = { 571 .b1co_mode_sel_mask = GENMASK(3, 2), 572 .mode = DW_PCIE_EP_TYPE, 573 }; 574 575 static const struct of_device_id of_dra7xx_pcie_match[] = { 576 { 577 .compatible = "ti,dra7-pcie", 578 .data = &dra7xx_pcie_rc_of_data, 579 }, 580 { 581 .compatible = "ti,dra7-pcie-ep", 582 .data = &dra7xx_pcie_ep_of_data, 583 }, 584 { 585 .compatible = "ti,dra746-pcie-rc", 586 .data = &dra746_pcie_rc_of_data, 587 }, 588 { 589 .compatible = "ti,dra726-pcie-rc", 590 .data = &dra726_pcie_rc_of_data, 591 }, 592 { 593 .compatible = "ti,dra746-pcie-ep", 594 .data = &dra746_pcie_ep_of_data, 595 }, 596 { 597 .compatible = "ti,dra726-pcie-ep", 598 .data = &dra726_pcie_ep_of_data, 599 }, 600 {}, 601 }; 602 603 /* 604 * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 605 * @dra7xx: the dra7xx device where the workaround should be applied 606 * 607 * Access to the PCIe slave port that are not 32-bit aligned will result 608 * in incorrect mapping to TLP Address and Byte enable fields. Therefore, 609 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or 610 * 0x3. 611 * 612 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. 613 */ 614 static int dra7xx_pcie_unaligned_memaccess(struct device *dev) 615 { 616 int ret; 617 struct device_node *np = dev->of_node; 618 struct of_phandle_args args; 619 struct regmap *regmap; 620 621 regmap = syscon_regmap_lookup_by_phandle(np, 622 "ti,syscon-unaligned-access"); 623 if (IS_ERR(regmap)) { 624 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); 625 return -EINVAL; 626 } 627 628 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access", 629 2, 0, &args); 630 if (ret) { 631 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n"); 632 return ret; 633 } 634 635 ret = regmap_update_bits(regmap, args.args[0], args.args[1], 636 args.args[1]); 637 if (ret) 638 dev_err(dev, "failed to enable unaligned access\n"); 639 640 of_node_put(args.np); 641 642 return ret; 643 } 644 645 static int dra7xx_pcie_configure_two_lane(struct device *dev, 646 u32 b1co_mode_sel_mask) 647 { 648 struct device_node *np = dev->of_node; 649 struct regmap *pcie_syscon; 650 unsigned int pcie_reg; 651 u32 mask; 652 u32 val; 653 654 pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel"); 655 if (IS_ERR(pcie_syscon)) { 656 dev_err(dev, "unable to get ti,syscon-lane-sel\n"); 657 return -EINVAL; 658 } 659 660 if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1, 661 &pcie_reg)) { 662 dev_err(dev, "couldn't get lane selection reg offset\n"); 663 return -EINVAL; 664 } 665 666 mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN; 667 val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN; 668 regmap_update_bits(pcie_syscon, pcie_reg, mask, val); 669 670 return 0; 671 } 672 673 static int __init dra7xx_pcie_probe(struct platform_device *pdev) 674 { 675 u32 reg; 676 int ret; 677 int irq; 678 int i; 679 int phy_count; 680 struct phy **phy; 681 struct device_link **link; 682 void __iomem *base; 683 struct resource *res; 684 struct dw_pcie *pci; 685 struct dra7xx_pcie *dra7xx; 686 struct device *dev = &pdev->dev; 687 struct device_node *np = dev->of_node; 688 char name[10]; 689 struct gpio_desc *reset; 690 const struct of_device_id *match; 691 const struct dra7xx_pcie_of_data *data; 692 enum dw_pcie_device_mode mode; 693 u32 b1co_mode_sel_mask; 694 695 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); 696 if (!match) 697 return -EINVAL; 698 699 data = (struct dra7xx_pcie_of_data *)match->data; 700 mode = (enum dw_pcie_device_mode)data->mode; 701 b1co_mode_sel_mask = data->b1co_mode_sel_mask; 702 703 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); 704 if (!dra7xx) 705 return -ENOMEM; 706 707 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 708 if (!pci) 709 return -ENOMEM; 710 711 pci->dev = dev; 712 pci->ops = &dw_pcie_ops; 713 714 irq = platform_get_irq(pdev, 0); 715 if (irq < 0) { 716 dev_err(dev, "missing IRQ resource: %d\n", irq); 717 return irq; 718 } 719 720 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf"); 721 base = devm_ioremap_nocache(dev, res->start, resource_size(res)); 722 if (!base) 723 return -ENOMEM; 724 725 phy_count = of_property_count_strings(np, "phy-names"); 726 if (phy_count < 0) { 727 dev_err(dev, "unable to find the strings\n"); 728 return phy_count; 729 } 730 731 phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); 732 if (!phy) 733 return -ENOMEM; 734 735 link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); 736 if (!link) 737 return -ENOMEM; 738 739 for (i = 0; i < phy_count; i++) { 740 snprintf(name, sizeof(name), "pcie-phy%d", i); 741 phy[i] = devm_phy_get(dev, name); 742 if (IS_ERR(phy[i])) 743 return PTR_ERR(phy[i]); 744 745 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 746 if (!link[i]) { 747 ret = -EINVAL; 748 goto err_link; 749 } 750 } 751 752 dra7xx->base = base; 753 dra7xx->phy = phy; 754 dra7xx->pci = pci; 755 dra7xx->phy_count = phy_count; 756 757 if (phy_count == 2) { 758 ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask); 759 if (ret < 0) 760 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */ 761 } 762 763 ret = dra7xx_pcie_enable_phy(dra7xx); 764 if (ret) { 765 dev_err(dev, "failed to enable phy\n"); 766 return ret; 767 } 768 769 platform_set_drvdata(pdev, dra7xx); 770 771 pm_runtime_enable(dev); 772 ret = pm_runtime_get_sync(dev); 773 if (ret < 0) { 774 dev_err(dev, "pm_runtime_get_sync failed\n"); 775 goto err_get_sync; 776 } 777 778 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); 779 if (IS_ERR(reset)) { 780 ret = PTR_ERR(reset); 781 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 782 goto err_gpio; 783 } 784 785 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); 786 reg &= ~LTSSM_EN; 787 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 788 789 dra7xx->link_gen = of_pci_get_max_link_speed(np); 790 if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2) 791 dra7xx->link_gen = 2; 792 793 switch (mode) { 794 case DW_PCIE_RC_TYPE: 795 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) { 796 ret = -ENODEV; 797 goto err_gpio; 798 } 799 800 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, 801 DEVICE_TYPE_RC); 802 803 ret = dra7xx_pcie_unaligned_memaccess(dev); 804 if (ret) 805 dev_err(dev, "WA for Errata i870 not applied\n"); 806 807 ret = dra7xx_add_pcie_port(dra7xx, pdev); 808 if (ret < 0) 809 goto err_gpio; 810 break; 811 case DW_PCIE_EP_TYPE: 812 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) { 813 ret = -ENODEV; 814 goto err_gpio; 815 } 816 817 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, 818 DEVICE_TYPE_EP); 819 820 ret = dra7xx_pcie_unaligned_memaccess(dev); 821 if (ret) 822 goto err_gpio; 823 824 ret = dra7xx_add_pcie_ep(dra7xx, pdev); 825 if (ret < 0) 826 goto err_gpio; 827 break; 828 default: 829 dev_err(dev, "INVALID device type %d\n", mode); 830 } 831 dra7xx->mode = mode; 832 833 ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, 834 IRQF_SHARED, "dra7xx-pcie-main", dra7xx); 835 if (ret) { 836 dev_err(dev, "failed to request irq\n"); 837 goto err_gpio; 838 } 839 840 return 0; 841 842 err_gpio: 843 pm_runtime_put(dev); 844 845 err_get_sync: 846 pm_runtime_disable(dev); 847 dra7xx_pcie_disable_phy(dra7xx); 848 849 err_link: 850 while (--i >= 0) 851 device_link_del(link[i]); 852 853 return ret; 854 } 855 856 #ifdef CONFIG_PM_SLEEP 857 static int dra7xx_pcie_suspend(struct device *dev) 858 { 859 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 860 struct dw_pcie *pci = dra7xx->pci; 861 u32 val; 862 863 if (dra7xx->mode != DW_PCIE_RC_TYPE) 864 return 0; 865 866 /* clear MSE */ 867 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 868 val &= ~PCI_COMMAND_MEMORY; 869 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 870 871 return 0; 872 } 873 874 static int dra7xx_pcie_resume(struct device *dev) 875 { 876 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 877 struct dw_pcie *pci = dra7xx->pci; 878 u32 val; 879 880 if (dra7xx->mode != DW_PCIE_RC_TYPE) 881 return 0; 882 883 /* set MSE */ 884 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 885 val |= PCI_COMMAND_MEMORY; 886 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 887 888 return 0; 889 } 890 891 static int dra7xx_pcie_suspend_noirq(struct device *dev) 892 { 893 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 894 895 dra7xx_pcie_disable_phy(dra7xx); 896 897 return 0; 898 } 899 900 static int dra7xx_pcie_resume_noirq(struct device *dev) 901 { 902 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 903 int ret; 904 905 ret = dra7xx_pcie_enable_phy(dra7xx); 906 if (ret) { 907 dev_err(dev, "failed to enable phy\n"); 908 return ret; 909 } 910 911 return 0; 912 } 913 #endif 914 915 static void dra7xx_pcie_shutdown(struct platform_device *pdev) 916 { 917 struct device *dev = &pdev->dev; 918 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 919 int ret; 920 921 dra7xx_pcie_stop_link(dra7xx->pci); 922 923 ret = pm_runtime_put_sync(dev); 924 if (ret < 0) 925 dev_dbg(dev, "pm_runtime_put_sync failed\n"); 926 927 pm_runtime_disable(dev); 928 dra7xx_pcie_disable_phy(dra7xx); 929 } 930 931 static const struct dev_pm_ops dra7xx_pcie_pm_ops = { 932 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume) 933 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq, 934 dra7xx_pcie_resume_noirq) 935 }; 936 937 static struct platform_driver dra7xx_pcie_driver = { 938 .driver = { 939 .name = "dra7-pcie", 940 .of_match_table = of_dra7xx_pcie_match, 941 .suppress_bind_attrs = true, 942 .pm = &dra7xx_pcie_pm_ops, 943 }, 944 .shutdown = dra7xx_pcie_shutdown, 945 }; 946 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe); 947