1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (c) 2017 Cadence 3 // Cadence PCIe controller driver. 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> 5 6 #ifndef _PCIE_CADENCE_H 7 #define _PCIE_CADENCE_H 8 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/phy/phy.h> 12 13 /* Parameters for the waiting for link up routine */ 14 #define LINK_WAIT_MAX_RETRIES 10 15 #define LINK_WAIT_USLEEP_MIN 90000 16 #define LINK_WAIT_USLEEP_MAX 100000 17 18 /* 19 * Local Management Registers 20 */ 21 #define CDNS_PCIE_LM_BASE 0x00100000 22 23 /* Vendor ID Register */ 24 #define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) 25 #define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) 26 #define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 27 #define CDNS_PCIE_LM_ID_VENDOR(vid) \ 28 (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) 29 #define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) 30 #define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 31 #define CDNS_PCIE_LM_ID_SUBSYS(sub) \ 32 (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) 33 34 /* Root Port Requestor ID Register */ 35 #define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) 36 #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) 37 #define CDNS_PCIE_LM_RP_RID_SHIFT 0 38 #define CDNS_PCIE_LM_RP_RID_(rid) \ 39 (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) 40 41 /* Endpoint Bus and Device Number Register */ 42 #define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) 43 #define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) 44 #define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 45 #define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) 46 #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 47 48 /* Endpoint Function f BAR b Configuration Registers */ 49 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ 50 (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) 51 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ 52 (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) 53 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ 54 (GENMASK(4, 0) << ((b) * 8)) 55 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ 56 (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) 57 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ 58 (GENMASK(7, 5) << ((b) * 8)) 59 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ 60 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) 61 62 /* Endpoint Function Configuration Register */ 63 #define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) 64 65 /* Root Complex BAR Configuration Register */ 66 #define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) 67 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) 68 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ 69 (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) 70 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) 71 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ 72 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) 73 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) 74 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ 75 (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) 76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) 77 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ 78 (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) 79 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) 80 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 81 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) 82 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) 83 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 84 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) 85 #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) 86 87 /* BAR control values applicable to both Endpoint Function and Root Complex */ 88 #define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 89 #define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 90 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 91 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 92 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 93 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 94 95 #define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ 96 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) 97 #define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ 98 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) 99 #define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ 100 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) 101 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ 102 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) 103 #define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ 104 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) 105 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ 106 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) 107 #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ 108 (((aperture) - 2) << ((bar) * 8)) 109 110 /* 111 * Endpoint Function Registers (PCI configuration space for endpoint functions) 112 */ 113 #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) 114 115 #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 116 #define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 117 118 /* 119 * Root Port Registers (PCI configuration space for the root port function) 120 */ 121 #define CDNS_PCIE_RP_BASE 0x00200000 122 #define CDNS_PCIE_RP_CAP_OFFSET 0xc0 123 124 /* 125 * Address Translation Registers 126 */ 127 #define CDNS_PCIE_AT_BASE 0x00400000 128 129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */ 130 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ 131 (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) 132 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) 133 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ 134 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) 135 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) 136 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ 137 (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) 138 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) 139 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ 140 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) 141 142 /* Region r Outbound AXI to PCIe Address Translation Register 1 */ 143 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ 144 (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) 145 146 /* Region r Outbound PCIe Descriptor Register 0 */ 147 #define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ 148 (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) 149 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) 150 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 151 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 152 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa 153 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb 154 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc 155 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd 156 /* Bit 23 MUST be set in RC mode. */ 157 #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) 158 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) 159 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ 160 (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) 161 162 /* Region r Outbound PCIe Descriptor Register 1 */ 163 #define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ 164 (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) 165 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) 166 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ 167 ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) 168 169 /* Region r AXI Region Base Address Register 0 */ 170 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ 171 (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) 172 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) 173 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ 174 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) 175 176 /* Region r AXI Region Base Address Register 1 */ 177 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ 178 (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) 179 180 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */ 181 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ 182 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) 183 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) 184 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ 185 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) 186 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ 187 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) 188 189 /* AXI link down register */ 190 #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) 191 192 enum cdns_pcie_rp_bar { 193 RP_BAR_UNDEFINED = -1, 194 RP_BAR0, 195 RP_BAR1, 196 RP_NO_BAR 197 }; 198 199 #define CDNS_PCIE_RP_MAX_IB 0x3 200 #define CDNS_PCIE_MAX_OB 32 201 202 struct cdns_pcie_rp_ib_bar { 203 u64 size; 204 bool free; 205 }; 206 207 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ 208 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ 209 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) 210 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ 211 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) 212 213 /* Normal/Vendor specific message access: offset inside some outbound region */ 214 #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) 215 #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ 216 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) 217 #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) 218 #define CDNS_PCIE_NORMAL_MSG_CODE(code) \ 219 (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) 220 #define CDNS_PCIE_MSG_NO_DATA BIT(16) 221 222 struct cdns_pcie; 223 224 enum cdns_pcie_msg_code { 225 MSG_CODE_ASSERT_INTA = 0x20, 226 MSG_CODE_ASSERT_INTB = 0x21, 227 MSG_CODE_ASSERT_INTC = 0x22, 228 MSG_CODE_ASSERT_INTD = 0x23, 229 MSG_CODE_DEASSERT_INTA = 0x24, 230 MSG_CODE_DEASSERT_INTB = 0x25, 231 MSG_CODE_DEASSERT_INTC = 0x26, 232 MSG_CODE_DEASSERT_INTD = 0x27, 233 }; 234 235 enum cdns_pcie_msg_routing { 236 /* Route to Root Complex */ 237 MSG_ROUTING_TO_RC, 238 239 /* Use Address Routing */ 240 MSG_ROUTING_BY_ADDR, 241 242 /* Use ID Routing */ 243 MSG_ROUTING_BY_ID, 244 245 /* Route as Broadcast Message from Root Complex */ 246 MSG_ROUTING_BCAST, 247 248 /* Local message; terminate at receiver (INTx messages) */ 249 MSG_ROUTING_LOCAL, 250 251 /* Gather & route to Root Complex (PME_TO_Ack message) */ 252 MSG_ROUTING_GATHER, 253 }; 254 255 struct cdns_pcie_ops { 256 int (*start_link)(struct cdns_pcie *pcie); 257 void (*stop_link)(struct cdns_pcie *pcie); 258 bool (*link_up)(struct cdns_pcie *pcie); 259 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); 260 }; 261 262 /** 263 * struct cdns_pcie - private data for Cadence PCIe controller drivers 264 * @reg_base: IO mapped register base 265 * @mem_res: start/end offsets in the physical system memory to map PCI accesses 266 * @dev: PCIe controller 267 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. 268 * @phy_count: number of supported PHY devices 269 * @phy: list of pointers to specific PHY control blocks 270 * @link: list of pointers to corresponding device link representations 271 * @ops: Platform-specific ops to control various inputs from Cadence PCIe 272 * wrapper 273 */ 274 struct cdns_pcie { 275 void __iomem *reg_base; 276 struct resource *mem_res; 277 struct device *dev; 278 bool is_rc; 279 int phy_count; 280 struct phy **phy; 281 struct device_link **link; 282 const struct cdns_pcie_ops *ops; 283 }; 284 285 /** 286 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver 287 * @pcie: Cadence PCIe controller 288 * @dev: pointer to PCIe device 289 * @cfg_res: start/end offsets in the physical system memory to map PCI 290 * configuration space accesses 291 * @cfg_base: IO mapped window to access the PCI configuration space of a 292 * single function at a time 293 * @vendor_id: PCI vendor ID 294 * @device_id: PCI device ID 295 * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or 296 * available 297 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 298 */ 299 struct cdns_pcie_rc { 300 struct cdns_pcie pcie; 301 struct resource *cfg_res; 302 void __iomem *cfg_base; 303 u32 vendor_id; 304 u32 device_id; 305 bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; 306 bool quirk_retrain_flag; 307 }; 308 309 /** 310 * struct cdns_pcie_epf - Structure to hold info about endpoint function 311 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers 312 */ 313 struct cdns_pcie_epf { 314 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; 315 }; 316 317 /** 318 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver 319 * @pcie: Cadence PCIe controller 320 * @max_regions: maximum number of regions supported by hardware 321 * @ob_region_map: bitmask of mapped outbound regions 322 * @ob_addr: base addresses in the AXI bus where the outbound regions start 323 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ 324 * dedicated outbound regions is mapped. 325 * @irq_cpu_addr: base address in the CPU space where a write access triggers 326 * the sending of a memory write (MSI) / normal message (legacy 327 * IRQ) TLP through the PCIe bus. 328 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ 329 * dedicated outbound region. 330 * @irq_pci_fn: the latest PCI function that has updated the mapping of 331 * the MSI/legacy IRQ dedicated outbound region. 332 * @irq_pending: bitmask of asserted legacy IRQs. 333 * @lock: spin lock to disable interrupts while modifying PCIe controller 334 * registers fields (RMW) accessible by both remote RC and EP to 335 * minimize time between read and write 336 * @epf: Structure to hold info about endpoint function 337 */ 338 struct cdns_pcie_ep { 339 struct cdns_pcie pcie; 340 u32 max_regions; 341 unsigned long ob_region_map; 342 phys_addr_t *ob_addr; 343 phys_addr_t irq_phys_addr; 344 void __iomem *irq_cpu_addr; 345 u64 irq_pci_addr; 346 u8 irq_pci_fn; 347 u8 irq_pending; 348 /* protect writing to PCI_STATUS while raising legacy interrupts */ 349 spinlock_t lock; 350 struct cdns_pcie_epf *epf; 351 }; 352 353 354 /* Register access */ 355 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) 356 { 357 writel(value, pcie->reg_base + reg); 358 } 359 360 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) 361 { 362 return readl(pcie->reg_base + reg); 363 } 364 365 static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) 366 { 367 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); 368 unsigned int offset = (unsigned long)addr & 0x3; 369 u32 val = readl(aligned_addr); 370 371 if (!IS_ALIGNED((uintptr_t)addr, size)) { 372 pr_warn("Address %p and size %d are not aligned\n", addr, size); 373 return 0; 374 } 375 376 if (size > 2) 377 return val; 378 379 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); 380 } 381 382 static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) 383 { 384 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); 385 unsigned int offset = (unsigned long)addr & 0x3; 386 u32 mask; 387 u32 val; 388 389 if (!IS_ALIGNED((uintptr_t)addr, size)) { 390 pr_warn("Address %p and size %d are not aligned\n", addr, size); 391 return; 392 } 393 394 if (size > 2) { 395 writel(value, addr); 396 return; 397 } 398 399 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); 400 val = readl(aligned_addr) & mask; 401 val |= value << (offset * 8); 402 writel(val, aligned_addr); 403 } 404 405 /* Root Port register access */ 406 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, 407 u32 reg, u8 value) 408 { 409 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 410 411 cdns_pcie_write_sz(addr, 0x1, value); 412 } 413 414 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, 415 u32 reg, u16 value) 416 { 417 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 418 419 cdns_pcie_write_sz(addr, 0x2, value); 420 } 421 422 static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) 423 { 424 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; 425 426 return cdns_pcie_read_sz(addr, 0x2); 427 } 428 429 /* Endpoint Function register access */ 430 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, 431 u32 reg, u8 value) 432 { 433 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 434 435 cdns_pcie_write_sz(addr, 0x1, value); 436 } 437 438 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, 439 u32 reg, u16 value) 440 { 441 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 442 443 cdns_pcie_write_sz(addr, 0x2, value); 444 } 445 446 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, 447 u32 reg, u32 value) 448 { 449 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); 450 } 451 452 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) 453 { 454 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; 455 456 return cdns_pcie_read_sz(addr, 0x2); 457 } 458 459 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) 460 { 461 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); 462 } 463 464 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) 465 { 466 if (pcie->ops->start_link) 467 return pcie->ops->start_link(pcie); 468 469 return 0; 470 } 471 472 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) 473 { 474 if (pcie->ops->stop_link) 475 pcie->ops->stop_link(pcie); 476 } 477 478 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) 479 { 480 if (pcie->ops->link_up) 481 return pcie->ops->link_up(pcie); 482 483 return true; 484 } 485 486 #ifdef CONFIG_PCIE_CADENCE_HOST 487 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); 488 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 489 int where); 490 #else 491 static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 492 { 493 return 0; 494 } 495 496 static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, 497 int where) 498 { 499 return NULL; 500 } 501 #endif 502 503 #ifdef CONFIG_PCIE_CADENCE_EP 504 int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); 505 #else 506 static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 507 { 508 return 0; 509 } 510 #endif 511 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, 512 u32 r, bool is_io, 513 u64 cpu_addr, u64 pci_addr, size_t size); 514 515 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, 516 u8 busnr, u8 fn, 517 u32 r, u64 cpu_addr); 518 519 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); 520 void cdns_pcie_disable_phy(struct cdns_pcie *pcie); 521 int cdns_pcie_enable_phy(struct cdns_pcie *pcie); 522 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); 523 extern const struct dev_pm_ops cdns_pcie_pm_ops; 524 525 #endif /* _PCIE_CADENCE_H */ 526