1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/io.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/pci.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 22 #include "../../pci.h" 23 #include "pcie-cadence.h" 24 25 #define ENABLE_REG_SYS_2 0x108 26 #define STATUS_REG_SYS_2 0x508 27 #define STATUS_CLR_REG_SYS_2 0x708 28 #define LINK_DOWN BIT(1) 29 #define J7200_LINK_DOWN BIT(10) 30 31 #define J721E_PCIE_USER_CMD_STATUS 0x4 32 #define LINK_TRAINING_ENABLE BIT(0) 33 34 #define J721E_PCIE_USER_LINKSTATUS 0x14 35 #define LINK_STATUS GENMASK(1, 0) 36 37 enum link_status { 38 NO_RECEIVERS_DETECTED, 39 LINK_TRAINING_IN_PROGRESS, 40 LINK_UP_DL_IN_PROGRESS, 41 LINK_UP_DL_COMPLETED, 42 }; 43 44 #define J721E_MODE_RC BIT(7) 45 #define LANE_COUNT_MASK BIT(8) 46 #define LANE_COUNT(n) ((n) << 8) 47 48 #define GENERATION_SEL_MASK GENMASK(1, 0) 49 50 #define MAX_LANES 2 51 52 struct j721e_pcie { 53 struct cdns_pcie *cdns_pcie; 54 struct clk *refclk; 55 u32 mode; 56 u32 num_lanes; 57 void __iomem *user_cfg_base; 58 void __iomem *intd_cfg_base; 59 u32 linkdown_irq_regfield; 60 }; 61 62 enum j721e_pcie_mode { 63 PCI_MODE_RC, 64 PCI_MODE_EP, 65 }; 66 67 struct j721e_pcie_data { 68 enum j721e_pcie_mode mode; 69 unsigned int quirk_retrain_flag:1; 70 unsigned int quirk_detect_quiet_flag:1; 71 unsigned int quirk_disable_flr:1; 72 u32 linkdown_irq_regfield; 73 unsigned int byte_access_allowed:1; 74 }; 75 76 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 77 { 78 return readl(pcie->user_cfg_base + offset); 79 } 80 81 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 82 u32 value) 83 { 84 writel(value, pcie->user_cfg_base + offset); 85 } 86 87 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 88 { 89 return readl(pcie->intd_cfg_base + offset); 90 } 91 92 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 93 u32 value) 94 { 95 writel(value, pcie->intd_cfg_base + offset); 96 } 97 98 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 99 { 100 struct j721e_pcie *pcie = priv; 101 struct device *dev = pcie->cdns_pcie->dev; 102 u32 reg; 103 104 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 105 if (!(reg & pcie->linkdown_irq_regfield)) 106 return IRQ_NONE; 107 108 dev_err(dev, "LINK DOWN!\n"); 109 110 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); 111 return IRQ_HANDLED; 112 } 113 114 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 115 { 116 u32 reg; 117 118 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 119 reg |= pcie->linkdown_irq_regfield; 120 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 121 } 122 123 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 124 { 125 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 126 u32 reg; 127 128 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 129 reg |= LINK_TRAINING_ENABLE; 130 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 131 132 return 0; 133 } 134 135 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 136 { 137 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 138 u32 reg; 139 140 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 141 reg &= ~LINK_TRAINING_ENABLE; 142 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 143 } 144 145 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 146 { 147 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 148 u32 reg; 149 150 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 151 reg &= LINK_STATUS; 152 if (reg == LINK_UP_DL_COMPLETED) 153 return true; 154 155 return false; 156 } 157 158 static const struct cdns_pcie_ops j721e_pcie_ops = { 159 .start_link = j721e_pcie_start_link, 160 .stop_link = j721e_pcie_stop_link, 161 .link_up = j721e_pcie_link_up, 162 }; 163 164 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 165 unsigned int offset) 166 { 167 struct device *dev = pcie->cdns_pcie->dev; 168 u32 mask = J721E_MODE_RC; 169 u32 mode = pcie->mode; 170 u32 val = 0; 171 int ret = 0; 172 173 if (mode == PCI_MODE_RC) 174 val = J721E_MODE_RC; 175 176 ret = regmap_update_bits(syscon, offset, mask, val); 177 if (ret) 178 dev_err(dev, "failed to set pcie mode\n"); 179 180 return ret; 181 } 182 183 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 184 struct regmap *syscon, unsigned int offset) 185 { 186 struct device *dev = pcie->cdns_pcie->dev; 187 struct device_node *np = dev->of_node; 188 int link_speed; 189 u32 val = 0; 190 int ret; 191 192 link_speed = of_pci_get_max_link_speed(np); 193 if (link_speed < 2) 194 link_speed = 2; 195 196 val = link_speed - 1; 197 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 198 if (ret) 199 dev_err(dev, "failed to set link speed\n"); 200 201 return ret; 202 } 203 204 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 205 struct regmap *syscon, unsigned int offset) 206 { 207 struct device *dev = pcie->cdns_pcie->dev; 208 u32 lanes = pcie->num_lanes; 209 u32 val = 0; 210 int ret; 211 212 val = LANE_COUNT(lanes - 1); 213 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); 214 if (ret) 215 dev_err(dev, "failed to set link count\n"); 216 217 return ret; 218 } 219 220 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 221 { 222 struct device *dev = pcie->cdns_pcie->dev; 223 struct device_node *node = dev->of_node; 224 struct of_phandle_args args; 225 unsigned int offset = 0; 226 struct regmap *syscon; 227 int ret; 228 229 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 230 if (IS_ERR(syscon)) { 231 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 232 return PTR_ERR(syscon); 233 } 234 235 /* Do not error out to maintain old DT compatibility */ 236 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 237 0, &args); 238 if (!ret) 239 offset = args.args[0]; 240 241 ret = j721e_pcie_set_mode(pcie, syscon, offset); 242 if (ret < 0) { 243 dev_err(dev, "Failed to set pci mode\n"); 244 return ret; 245 } 246 247 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 248 if (ret < 0) { 249 dev_err(dev, "Failed to set link speed\n"); 250 return ret; 251 } 252 253 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 254 if (ret < 0) { 255 dev_err(dev, "Failed to set num-lanes\n"); 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 263 int where, int size, u32 *value) 264 { 265 if (pci_is_root_bus(bus)) 266 return pci_generic_config_read32(bus, devfn, where, size, 267 value); 268 269 return pci_generic_config_read(bus, devfn, where, size, value); 270 } 271 272 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 273 int where, int size, u32 value) 274 { 275 if (pci_is_root_bus(bus)) 276 return pci_generic_config_write32(bus, devfn, where, size, 277 value); 278 279 return pci_generic_config_write(bus, devfn, where, size, value); 280 } 281 282 static struct pci_ops cdns_ti_pcie_host_ops = { 283 .map_bus = cdns_pci_map_bus, 284 .read = cdns_ti_pcie_config_read, 285 .write = cdns_ti_pcie_config_write, 286 }; 287 288 static const struct j721e_pcie_data j721e_pcie_rc_data = { 289 .mode = PCI_MODE_RC, 290 .quirk_retrain_flag = true, 291 .byte_access_allowed = false, 292 .linkdown_irq_regfield = LINK_DOWN, 293 }; 294 295 static const struct j721e_pcie_data j721e_pcie_ep_data = { 296 .mode = PCI_MODE_EP, 297 .linkdown_irq_regfield = LINK_DOWN, 298 }; 299 300 static const struct j721e_pcie_data j7200_pcie_rc_data = { 301 .mode = PCI_MODE_RC, 302 .quirk_detect_quiet_flag = true, 303 .linkdown_irq_regfield = J7200_LINK_DOWN, 304 .byte_access_allowed = true, 305 }; 306 307 static const struct j721e_pcie_data j7200_pcie_ep_data = { 308 .mode = PCI_MODE_EP, 309 .quirk_detect_quiet_flag = true, 310 .quirk_disable_flr = true, 311 }; 312 313 static const struct j721e_pcie_data am64_pcie_rc_data = { 314 .mode = PCI_MODE_RC, 315 .linkdown_irq_regfield = J7200_LINK_DOWN, 316 .byte_access_allowed = true, 317 }; 318 319 static const struct j721e_pcie_data am64_pcie_ep_data = { 320 .mode = PCI_MODE_EP, 321 .linkdown_irq_regfield = J7200_LINK_DOWN, 322 }; 323 324 static const struct of_device_id of_j721e_pcie_match[] = { 325 { 326 .compatible = "ti,j721e-pcie-host", 327 .data = &j721e_pcie_rc_data, 328 }, 329 { 330 .compatible = "ti,j721e-pcie-ep", 331 .data = &j721e_pcie_ep_data, 332 }, 333 { 334 .compatible = "ti,j7200-pcie-host", 335 .data = &j7200_pcie_rc_data, 336 }, 337 { 338 .compatible = "ti,j7200-pcie-ep", 339 .data = &j7200_pcie_ep_data, 340 }, 341 { 342 .compatible = "ti,am64-pcie-host", 343 .data = &am64_pcie_rc_data, 344 }, 345 { 346 .compatible = "ti,am64-pcie-ep", 347 .data = &am64_pcie_ep_data, 348 }, 349 {}, 350 }; 351 352 static int j721e_pcie_probe(struct platform_device *pdev) 353 { 354 struct device *dev = &pdev->dev; 355 struct device_node *node = dev->of_node; 356 struct pci_host_bridge *bridge; 357 const struct j721e_pcie_data *data; 358 struct cdns_pcie *cdns_pcie; 359 struct j721e_pcie *pcie; 360 struct cdns_pcie_rc *rc = NULL; 361 struct cdns_pcie_ep *ep = NULL; 362 struct gpio_desc *gpiod; 363 void __iomem *base; 364 struct clk *clk; 365 u32 num_lanes; 366 u32 mode; 367 int ret; 368 int irq; 369 370 data = of_device_get_match_data(dev); 371 if (!data) 372 return -EINVAL; 373 374 mode = (u32)data->mode; 375 376 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 377 if (!pcie) 378 return -ENOMEM; 379 380 switch (mode) { 381 case PCI_MODE_RC: 382 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) 383 return -ENODEV; 384 385 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 386 if (!bridge) 387 return -ENOMEM; 388 389 if (!data->byte_access_allowed) 390 bridge->ops = &cdns_ti_pcie_host_ops; 391 rc = pci_host_bridge_priv(bridge); 392 rc->quirk_retrain_flag = data->quirk_retrain_flag; 393 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 394 395 cdns_pcie = &rc->pcie; 396 cdns_pcie->dev = dev; 397 cdns_pcie->ops = &j721e_pcie_ops; 398 pcie->cdns_pcie = cdns_pcie; 399 break; 400 case PCI_MODE_EP: 401 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) 402 return -ENODEV; 403 404 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 405 if (!ep) 406 return -ENOMEM; 407 408 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 409 ep->quirk_disable_flr = data->quirk_disable_flr; 410 411 cdns_pcie = &ep->pcie; 412 cdns_pcie->dev = dev; 413 cdns_pcie->ops = &j721e_pcie_ops; 414 pcie->cdns_pcie = cdns_pcie; 415 break; 416 default: 417 dev_err(dev, "INVALID device type %d\n", mode); 418 return 0; 419 } 420 421 pcie->mode = mode; 422 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; 423 424 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 425 if (IS_ERR(base)) 426 return PTR_ERR(base); 427 pcie->intd_cfg_base = base; 428 429 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 430 if (IS_ERR(base)) 431 return PTR_ERR(base); 432 pcie->user_cfg_base = base; 433 434 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 435 if (ret || num_lanes > MAX_LANES) 436 num_lanes = 1; 437 pcie->num_lanes = num_lanes; 438 439 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 440 return -EINVAL; 441 442 irq = platform_get_irq_byname(pdev, "link_state"); 443 if (irq < 0) 444 return irq; 445 446 dev_set_drvdata(dev, pcie); 447 pm_runtime_enable(dev); 448 ret = pm_runtime_get_sync(dev); 449 if (ret < 0) { 450 dev_err(dev, "pm_runtime_get_sync failed\n"); 451 goto err_get_sync; 452 } 453 454 ret = j721e_pcie_ctrl_init(pcie); 455 if (ret < 0) { 456 dev_err(dev, "pm_runtime_get_sync failed\n"); 457 goto err_get_sync; 458 } 459 460 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 461 "j721e-pcie-link-down-irq", pcie); 462 if (ret < 0) { 463 dev_err(dev, "failed to request link state IRQ %d\n", irq); 464 goto err_get_sync; 465 } 466 467 j721e_pcie_config_link_irq(pcie); 468 469 switch (mode) { 470 case PCI_MODE_RC: 471 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 472 if (IS_ERR(gpiod)) { 473 ret = PTR_ERR(gpiod); 474 if (ret != -EPROBE_DEFER) 475 dev_err(dev, "Failed to get reset GPIO\n"); 476 goto err_get_sync; 477 } 478 479 ret = cdns_pcie_init_phy(dev, cdns_pcie); 480 if (ret) { 481 dev_err(dev, "Failed to init phy\n"); 482 goto err_get_sync; 483 } 484 485 clk = devm_clk_get_optional(dev, "pcie_refclk"); 486 if (IS_ERR(clk)) { 487 ret = PTR_ERR(clk); 488 dev_err(dev, "failed to get pcie_refclk\n"); 489 goto err_pcie_setup; 490 } 491 492 ret = clk_prepare_enable(clk); 493 if (ret) { 494 dev_err(dev, "failed to enable pcie_refclk\n"); 495 goto err_pcie_setup; 496 } 497 pcie->refclk = clk; 498 499 /* 500 * "Power Sequencing and Reset Signal Timings" table in 501 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 502 * indicates PERST# should be deasserted after minimum of 100us 503 * once REFCLK is stable. The REFCLK to the connector in RC 504 * mode is selected while enabling the PHY. So deassert PERST# 505 * after 100 us. 506 */ 507 if (gpiod) { 508 usleep_range(100, 200); 509 gpiod_set_value_cansleep(gpiod, 1); 510 } 511 512 ret = cdns_pcie_host_setup(rc); 513 if (ret < 0) { 514 clk_disable_unprepare(pcie->refclk); 515 goto err_pcie_setup; 516 } 517 518 break; 519 case PCI_MODE_EP: 520 ret = cdns_pcie_init_phy(dev, cdns_pcie); 521 if (ret) { 522 dev_err(dev, "Failed to init phy\n"); 523 goto err_get_sync; 524 } 525 526 ret = cdns_pcie_ep_setup(ep); 527 if (ret < 0) 528 goto err_pcie_setup; 529 530 break; 531 } 532 533 return 0; 534 535 err_pcie_setup: 536 cdns_pcie_disable_phy(cdns_pcie); 537 538 err_get_sync: 539 pm_runtime_put(dev); 540 pm_runtime_disable(dev); 541 542 return ret; 543 } 544 545 static int j721e_pcie_remove(struct platform_device *pdev) 546 { 547 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 548 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 549 struct device *dev = &pdev->dev; 550 551 clk_disable_unprepare(pcie->refclk); 552 cdns_pcie_disable_phy(cdns_pcie); 553 pm_runtime_put(dev); 554 pm_runtime_disable(dev); 555 556 return 0; 557 } 558 559 static struct platform_driver j721e_pcie_driver = { 560 .probe = j721e_pcie_probe, 561 .remove = j721e_pcie_remove, 562 .driver = { 563 .name = "j721e-pcie", 564 .of_match_table = of_j721e_pcie_match, 565 .suppress_bind_attrs = true, 566 }, 567 }; 568 builtin_platform_driver(j721e_pcie_driver); 569