1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/io.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_irq.h> 19 #include <linux/pci.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 23 #include "../../pci.h" 24 #include "pcie-cadence.h" 25 26 #define ENABLE_REG_SYS_2 0x108 27 #define STATUS_REG_SYS_2 0x508 28 #define STATUS_CLR_REG_SYS_2 0x708 29 #define LINK_DOWN BIT(1) 30 #define J7200_LINK_DOWN BIT(10) 31 32 #define J721E_PCIE_USER_CMD_STATUS 0x4 33 #define LINK_TRAINING_ENABLE BIT(0) 34 35 #define J721E_PCIE_USER_LINKSTATUS 0x14 36 #define LINK_STATUS GENMASK(1, 0) 37 38 enum link_status { 39 NO_RECEIVERS_DETECTED, 40 LINK_TRAINING_IN_PROGRESS, 41 LINK_UP_DL_IN_PROGRESS, 42 LINK_UP_DL_COMPLETED, 43 }; 44 45 #define J721E_MODE_RC BIT(7) 46 #define LANE_COUNT_MASK BIT(8) 47 #define LANE_COUNT(n) ((n) << 8) 48 49 #define GENERATION_SEL_MASK GENMASK(1, 0) 50 51 #define MAX_LANES 2 52 53 struct j721e_pcie { 54 struct cdns_pcie *cdns_pcie; 55 struct clk *refclk; 56 u32 mode; 57 u32 num_lanes; 58 void __iomem *user_cfg_base; 59 void __iomem *intd_cfg_base; 60 u32 linkdown_irq_regfield; 61 }; 62 63 enum j721e_pcie_mode { 64 PCI_MODE_RC, 65 PCI_MODE_EP, 66 }; 67 68 struct j721e_pcie_data { 69 enum j721e_pcie_mode mode; 70 unsigned int quirk_retrain_flag:1; 71 unsigned int quirk_detect_quiet_flag:1; 72 u32 linkdown_irq_regfield; 73 unsigned int byte_access_allowed:1; 74 }; 75 76 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 77 { 78 return readl(pcie->user_cfg_base + offset); 79 } 80 81 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 82 u32 value) 83 { 84 writel(value, pcie->user_cfg_base + offset); 85 } 86 87 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 88 { 89 return readl(pcie->intd_cfg_base + offset); 90 } 91 92 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 93 u32 value) 94 { 95 writel(value, pcie->intd_cfg_base + offset); 96 } 97 98 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 99 { 100 struct j721e_pcie *pcie = priv; 101 struct device *dev = pcie->cdns_pcie->dev; 102 u32 reg; 103 104 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 105 if (!(reg & pcie->linkdown_irq_regfield)) 106 return IRQ_NONE; 107 108 dev_err(dev, "LINK DOWN!\n"); 109 110 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); 111 return IRQ_HANDLED; 112 } 113 114 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 115 { 116 u32 reg; 117 118 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 119 reg |= pcie->linkdown_irq_regfield; 120 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 121 } 122 123 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 124 { 125 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 126 u32 reg; 127 128 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 129 reg |= LINK_TRAINING_ENABLE; 130 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 131 132 return 0; 133 } 134 135 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 136 { 137 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 138 u32 reg; 139 140 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 141 reg &= ~LINK_TRAINING_ENABLE; 142 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 143 } 144 145 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 146 { 147 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 148 u32 reg; 149 150 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 151 reg &= LINK_STATUS; 152 if (reg == LINK_UP_DL_COMPLETED) 153 return true; 154 155 return false; 156 } 157 158 static const struct cdns_pcie_ops j721e_pcie_ops = { 159 .start_link = j721e_pcie_start_link, 160 .stop_link = j721e_pcie_stop_link, 161 .link_up = j721e_pcie_link_up, 162 }; 163 164 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 165 unsigned int offset) 166 { 167 struct device *dev = pcie->cdns_pcie->dev; 168 u32 mask = J721E_MODE_RC; 169 u32 mode = pcie->mode; 170 u32 val = 0; 171 int ret = 0; 172 173 if (mode == PCI_MODE_RC) 174 val = J721E_MODE_RC; 175 176 ret = regmap_update_bits(syscon, offset, mask, val); 177 if (ret) 178 dev_err(dev, "failed to set pcie mode\n"); 179 180 return ret; 181 } 182 183 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 184 struct regmap *syscon, unsigned int offset) 185 { 186 struct device *dev = pcie->cdns_pcie->dev; 187 struct device_node *np = dev->of_node; 188 int link_speed; 189 u32 val = 0; 190 int ret; 191 192 link_speed = of_pci_get_max_link_speed(np); 193 if (link_speed < 2) 194 link_speed = 2; 195 196 val = link_speed - 1; 197 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 198 if (ret) 199 dev_err(dev, "failed to set link speed\n"); 200 201 return ret; 202 } 203 204 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 205 struct regmap *syscon, unsigned int offset) 206 { 207 struct device *dev = pcie->cdns_pcie->dev; 208 u32 lanes = pcie->num_lanes; 209 u32 val = 0; 210 int ret; 211 212 val = LANE_COUNT(lanes - 1); 213 ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); 214 if (ret) 215 dev_err(dev, "failed to set link count\n"); 216 217 return ret; 218 } 219 220 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 221 { 222 struct device *dev = pcie->cdns_pcie->dev; 223 struct device_node *node = dev->of_node; 224 struct of_phandle_args args; 225 unsigned int offset = 0; 226 struct regmap *syscon; 227 int ret; 228 229 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 230 if (IS_ERR(syscon)) { 231 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 232 return PTR_ERR(syscon); 233 } 234 235 /* Do not error out to maintain old DT compatibility */ 236 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 237 0, &args); 238 if (!ret) 239 offset = args.args[0]; 240 241 ret = j721e_pcie_set_mode(pcie, syscon, offset); 242 if (ret < 0) { 243 dev_err(dev, "Failed to set pci mode\n"); 244 return ret; 245 } 246 247 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 248 if (ret < 0) { 249 dev_err(dev, "Failed to set link speed\n"); 250 return ret; 251 } 252 253 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 254 if (ret < 0) { 255 dev_err(dev, "Failed to set num-lanes\n"); 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 263 int where, int size, u32 *value) 264 { 265 if (pci_is_root_bus(bus)) 266 return pci_generic_config_read32(bus, devfn, where, size, 267 value); 268 269 return pci_generic_config_read(bus, devfn, where, size, value); 270 } 271 272 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 273 int where, int size, u32 value) 274 { 275 if (pci_is_root_bus(bus)) 276 return pci_generic_config_write32(bus, devfn, where, size, 277 value); 278 279 return pci_generic_config_write(bus, devfn, where, size, value); 280 } 281 282 static struct pci_ops cdns_ti_pcie_host_ops = { 283 .map_bus = cdns_pci_map_bus, 284 .read = cdns_ti_pcie_config_read, 285 .write = cdns_ti_pcie_config_write, 286 }; 287 288 static const struct j721e_pcie_data j721e_pcie_rc_data = { 289 .mode = PCI_MODE_RC, 290 .quirk_retrain_flag = true, 291 .byte_access_allowed = false, 292 .linkdown_irq_regfield = LINK_DOWN, 293 }; 294 295 static const struct j721e_pcie_data j721e_pcie_ep_data = { 296 .mode = PCI_MODE_EP, 297 .linkdown_irq_regfield = LINK_DOWN, 298 }; 299 300 static const struct j721e_pcie_data j7200_pcie_rc_data = { 301 .mode = PCI_MODE_RC, 302 .quirk_detect_quiet_flag = true, 303 .linkdown_irq_regfield = J7200_LINK_DOWN, 304 .byte_access_allowed = true, 305 }; 306 307 static const struct j721e_pcie_data j7200_pcie_ep_data = { 308 .mode = PCI_MODE_EP, 309 .quirk_detect_quiet_flag = true, 310 }; 311 312 static const struct j721e_pcie_data am64_pcie_rc_data = { 313 .mode = PCI_MODE_RC, 314 .linkdown_irq_regfield = J7200_LINK_DOWN, 315 .byte_access_allowed = true, 316 }; 317 318 static const struct j721e_pcie_data am64_pcie_ep_data = { 319 .mode = PCI_MODE_EP, 320 .linkdown_irq_regfield = J7200_LINK_DOWN, 321 }; 322 323 static const struct of_device_id of_j721e_pcie_match[] = { 324 { 325 .compatible = "ti,j721e-pcie-host", 326 .data = &j721e_pcie_rc_data, 327 }, 328 { 329 .compatible = "ti,j721e-pcie-ep", 330 .data = &j721e_pcie_ep_data, 331 }, 332 { 333 .compatible = "ti,j7200-pcie-host", 334 .data = &j7200_pcie_rc_data, 335 }, 336 { 337 .compatible = "ti,j7200-pcie-ep", 338 .data = &j7200_pcie_ep_data, 339 }, 340 { 341 .compatible = "ti,am64-pcie-host", 342 .data = &am64_pcie_rc_data, 343 }, 344 { 345 .compatible = "ti,am64-pcie-ep", 346 .data = &am64_pcie_ep_data, 347 }, 348 {}, 349 }; 350 351 static int j721e_pcie_probe(struct platform_device *pdev) 352 { 353 struct device *dev = &pdev->dev; 354 struct device_node *node = dev->of_node; 355 struct pci_host_bridge *bridge; 356 const struct j721e_pcie_data *data; 357 struct cdns_pcie *cdns_pcie; 358 struct j721e_pcie *pcie; 359 struct cdns_pcie_rc *rc; 360 struct cdns_pcie_ep *ep; 361 struct gpio_desc *gpiod; 362 void __iomem *base; 363 struct clk *clk; 364 u32 num_lanes; 365 u32 mode; 366 int ret; 367 int irq; 368 369 data = of_device_get_match_data(dev); 370 if (!data) 371 return -EINVAL; 372 373 mode = (u32)data->mode; 374 375 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 376 if (!pcie) 377 return -ENOMEM; 378 379 pcie->mode = mode; 380 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; 381 382 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 383 if (IS_ERR(base)) 384 return PTR_ERR(base); 385 pcie->intd_cfg_base = base; 386 387 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 388 if (IS_ERR(base)) 389 return PTR_ERR(base); 390 pcie->user_cfg_base = base; 391 392 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 393 if (ret || num_lanes > MAX_LANES) 394 num_lanes = 1; 395 pcie->num_lanes = num_lanes; 396 397 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 398 return -EINVAL; 399 400 irq = platform_get_irq_byname(pdev, "link_state"); 401 if (irq < 0) 402 return irq; 403 404 dev_set_drvdata(dev, pcie); 405 pm_runtime_enable(dev); 406 ret = pm_runtime_get_sync(dev); 407 if (ret < 0) { 408 dev_err(dev, "pm_runtime_get_sync failed\n"); 409 goto err_get_sync; 410 } 411 412 ret = j721e_pcie_ctrl_init(pcie); 413 if (ret < 0) { 414 dev_err(dev, "pm_runtime_get_sync failed\n"); 415 goto err_get_sync; 416 } 417 418 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 419 "j721e-pcie-link-down-irq", pcie); 420 if (ret < 0) { 421 dev_err(dev, "failed to request link state IRQ %d\n", irq); 422 goto err_get_sync; 423 } 424 425 j721e_pcie_config_link_irq(pcie); 426 427 switch (mode) { 428 case PCI_MODE_RC: 429 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) { 430 ret = -ENODEV; 431 goto err_get_sync; 432 } 433 434 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 435 if (!bridge) { 436 ret = -ENOMEM; 437 goto err_get_sync; 438 } 439 440 if (!data->byte_access_allowed) 441 bridge->ops = &cdns_ti_pcie_host_ops; 442 rc = pci_host_bridge_priv(bridge); 443 rc->quirk_retrain_flag = data->quirk_retrain_flag; 444 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 445 446 cdns_pcie = &rc->pcie; 447 cdns_pcie->dev = dev; 448 cdns_pcie->ops = &j721e_pcie_ops; 449 pcie->cdns_pcie = cdns_pcie; 450 451 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 452 if (IS_ERR(gpiod)) { 453 ret = PTR_ERR(gpiod); 454 if (ret != -EPROBE_DEFER) 455 dev_err(dev, "Failed to get reset GPIO\n"); 456 goto err_get_sync; 457 } 458 459 ret = cdns_pcie_init_phy(dev, cdns_pcie); 460 if (ret) { 461 dev_err(dev, "Failed to init phy\n"); 462 goto err_get_sync; 463 } 464 465 clk = devm_clk_get_optional(dev, "pcie_refclk"); 466 if (IS_ERR(clk)) { 467 ret = PTR_ERR(clk); 468 dev_err(dev, "failed to get pcie_refclk\n"); 469 goto err_pcie_setup; 470 } 471 472 ret = clk_prepare_enable(clk); 473 if (ret) { 474 dev_err(dev, "failed to enable pcie_refclk\n"); 475 goto err_pcie_setup; 476 } 477 pcie->refclk = clk; 478 479 /* 480 * "Power Sequencing and Reset Signal Timings" table in 481 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 482 * indicates PERST# should be deasserted after minimum of 100us 483 * once REFCLK is stable. The REFCLK to the connector in RC 484 * mode is selected while enabling the PHY. So deassert PERST# 485 * after 100 us. 486 */ 487 if (gpiod) { 488 usleep_range(100, 200); 489 gpiod_set_value_cansleep(gpiod, 1); 490 } 491 492 ret = cdns_pcie_host_setup(rc); 493 if (ret < 0) { 494 clk_disable_unprepare(pcie->refclk); 495 goto err_pcie_setup; 496 } 497 498 break; 499 case PCI_MODE_EP: 500 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) { 501 ret = -ENODEV; 502 goto err_get_sync; 503 } 504 505 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 506 if (!ep) { 507 ret = -ENOMEM; 508 goto err_get_sync; 509 } 510 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 511 512 cdns_pcie = &ep->pcie; 513 cdns_pcie->dev = dev; 514 cdns_pcie->ops = &j721e_pcie_ops; 515 pcie->cdns_pcie = cdns_pcie; 516 517 ret = cdns_pcie_init_phy(dev, cdns_pcie); 518 if (ret) { 519 dev_err(dev, "Failed to init phy\n"); 520 goto err_get_sync; 521 } 522 523 ret = cdns_pcie_ep_setup(ep); 524 if (ret < 0) 525 goto err_pcie_setup; 526 527 break; 528 default: 529 dev_err(dev, "INVALID device type %d\n", mode); 530 } 531 532 return 0; 533 534 err_pcie_setup: 535 cdns_pcie_disable_phy(cdns_pcie); 536 537 err_get_sync: 538 pm_runtime_put(dev); 539 pm_runtime_disable(dev); 540 541 return ret; 542 } 543 544 static int j721e_pcie_remove(struct platform_device *pdev) 545 { 546 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 547 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 548 struct device *dev = &pdev->dev; 549 550 clk_disable_unprepare(pcie->refclk); 551 cdns_pcie_disable_phy(cdns_pcie); 552 pm_runtime_put(dev); 553 pm_runtime_disable(dev); 554 555 return 0; 556 } 557 558 static struct platform_driver j721e_pcie_driver = { 559 .probe = j721e_pcie_probe, 560 .remove = j721e_pcie_remove, 561 .driver = { 562 .name = "j721e-pcie", 563 .of_match_table = of_j721e_pcie_match, 564 .suppress_bind_attrs = true, 565 }, 566 }; 567 builtin_platform_driver(j721e_pcie_driver); 568