1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/container_of.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/pci.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 24 #include "../../pci.h" 25 #include "pcie-cadence.h" 26 27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) 28 29 #define ENABLE_REG_SYS_2 0x108 30 #define STATUS_REG_SYS_2 0x508 31 #define STATUS_CLR_REG_SYS_2 0x708 32 #define LINK_DOWN BIT(1) 33 #define J7200_LINK_DOWN BIT(10) 34 35 #define J721E_PCIE_USER_CMD_STATUS 0x4 36 #define LINK_TRAINING_ENABLE BIT(0) 37 38 #define J721E_PCIE_USER_LINKSTATUS 0x14 39 #define LINK_STATUS GENMASK(1, 0) 40 41 enum link_status { 42 NO_RECEIVERS_DETECTED, 43 LINK_TRAINING_IN_PROGRESS, 44 LINK_UP_DL_IN_PROGRESS, 45 LINK_UP_DL_COMPLETED, 46 }; 47 48 #define J721E_MODE_RC BIT(7) 49 #define LANE_COUNT(n) ((n) << 8) 50 51 #define GENERATION_SEL_MASK GENMASK(1, 0) 52 53 struct j721e_pcie { 54 struct cdns_pcie *cdns_pcie; 55 struct clk *refclk; 56 u32 mode; 57 u32 num_lanes; 58 u32 max_lanes; 59 struct gpio_desc *reset_gpio; 60 void __iomem *user_cfg_base; 61 void __iomem *intd_cfg_base; 62 u32 linkdown_irq_regfield; 63 }; 64 65 enum j721e_pcie_mode { 66 PCI_MODE_RC, 67 PCI_MODE_EP, 68 }; 69 70 struct j721e_pcie_data { 71 enum j721e_pcie_mode mode; 72 unsigned int quirk_retrain_flag:1; 73 unsigned int quirk_detect_quiet_flag:1; 74 unsigned int quirk_disable_flr:1; 75 u32 linkdown_irq_regfield; 76 unsigned int byte_access_allowed:1; 77 unsigned int max_lanes; 78 }; 79 80 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 81 { 82 return readl(pcie->user_cfg_base + offset); 83 } 84 85 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 86 u32 value) 87 { 88 writel(value, pcie->user_cfg_base + offset); 89 } 90 91 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 92 { 93 return readl(pcie->intd_cfg_base + offset); 94 } 95 96 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 97 u32 value) 98 { 99 writel(value, pcie->intd_cfg_base + offset); 100 } 101 102 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 103 { 104 struct j721e_pcie *pcie = priv; 105 struct device *dev = pcie->cdns_pcie->dev; 106 u32 reg; 107 108 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 109 if (!(reg & pcie->linkdown_irq_regfield)) 110 return IRQ_NONE; 111 112 dev_err(dev, "LINK DOWN!\n"); 113 114 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); 115 return IRQ_HANDLED; 116 } 117 118 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 119 { 120 u32 reg; 121 122 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 123 reg |= pcie->linkdown_irq_regfield; 124 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 125 } 126 127 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 128 { 129 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 130 u32 reg; 131 132 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 133 reg |= LINK_TRAINING_ENABLE; 134 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 135 136 return 0; 137 } 138 139 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 140 { 141 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 142 u32 reg; 143 144 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 145 reg &= ~LINK_TRAINING_ENABLE; 146 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 147 } 148 149 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 150 { 151 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 152 u32 reg; 153 154 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 155 reg &= LINK_STATUS; 156 if (reg == LINK_UP_DL_COMPLETED) 157 return true; 158 159 return false; 160 } 161 162 static const struct cdns_pcie_ops j721e_pcie_ops = { 163 .start_link = j721e_pcie_start_link, 164 .stop_link = j721e_pcie_stop_link, 165 .link_up = j721e_pcie_link_up, 166 }; 167 168 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 169 unsigned int offset) 170 { 171 struct device *dev = pcie->cdns_pcie->dev; 172 u32 mask = J721E_MODE_RC; 173 u32 mode = pcie->mode; 174 u32 val = 0; 175 int ret = 0; 176 177 if (mode == PCI_MODE_RC) 178 val = J721E_MODE_RC; 179 180 ret = regmap_update_bits(syscon, offset, mask, val); 181 if (ret) 182 dev_err(dev, "failed to set pcie mode\n"); 183 184 return ret; 185 } 186 187 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 188 struct regmap *syscon, unsigned int offset) 189 { 190 struct device *dev = pcie->cdns_pcie->dev; 191 struct device_node *np = dev->of_node; 192 int link_speed; 193 u32 val = 0; 194 int ret; 195 196 link_speed = of_pci_get_max_link_speed(np); 197 if (link_speed < 2) 198 link_speed = 2; 199 200 val = link_speed - 1; 201 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 202 if (ret) 203 dev_err(dev, "failed to set link speed\n"); 204 205 return ret; 206 } 207 208 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 209 struct regmap *syscon, unsigned int offset) 210 { 211 struct device *dev = pcie->cdns_pcie->dev; 212 u32 lanes = pcie->num_lanes; 213 u32 mask = BIT(8); 214 u32 val = 0; 215 int ret; 216 217 if (pcie->max_lanes == 4) 218 mask = GENMASK(9, 8); 219 220 val = LANE_COUNT(lanes - 1); 221 ret = regmap_update_bits(syscon, offset, mask, val); 222 if (ret) 223 dev_err(dev, "failed to set link count\n"); 224 225 return ret; 226 } 227 228 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 229 { 230 struct device *dev = pcie->cdns_pcie->dev; 231 struct device_node *node = dev->of_node; 232 struct of_phandle_args args; 233 unsigned int offset = 0; 234 struct regmap *syscon; 235 int ret; 236 237 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 238 if (IS_ERR(syscon)) { 239 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 240 return PTR_ERR(syscon); 241 } 242 243 /* Do not error out to maintain old DT compatibility */ 244 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 245 0, &args); 246 if (!ret) 247 offset = args.args[0]; 248 249 ret = j721e_pcie_set_mode(pcie, syscon, offset); 250 if (ret < 0) { 251 dev_err(dev, "Failed to set pci mode\n"); 252 return ret; 253 } 254 255 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 256 if (ret < 0) { 257 dev_err(dev, "Failed to set link speed\n"); 258 return ret; 259 } 260 261 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 262 if (ret < 0) { 263 dev_err(dev, "Failed to set num-lanes\n"); 264 return ret; 265 } 266 267 return 0; 268 } 269 270 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 271 int where, int size, u32 *value) 272 { 273 if (pci_is_root_bus(bus)) 274 return pci_generic_config_read32(bus, devfn, where, size, 275 value); 276 277 return pci_generic_config_read(bus, devfn, where, size, value); 278 } 279 280 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 281 int where, int size, u32 value) 282 { 283 if (pci_is_root_bus(bus)) 284 return pci_generic_config_write32(bus, devfn, where, size, 285 value); 286 287 return pci_generic_config_write(bus, devfn, where, size, value); 288 } 289 290 static struct pci_ops cdns_ti_pcie_host_ops = { 291 .map_bus = cdns_pci_map_bus, 292 .read = cdns_ti_pcie_config_read, 293 .write = cdns_ti_pcie_config_write, 294 }; 295 296 static const struct j721e_pcie_data j721e_pcie_rc_data = { 297 .mode = PCI_MODE_RC, 298 .quirk_retrain_flag = true, 299 .byte_access_allowed = false, 300 .linkdown_irq_regfield = LINK_DOWN, 301 .max_lanes = 2, 302 }; 303 304 static const struct j721e_pcie_data j721e_pcie_ep_data = { 305 .mode = PCI_MODE_EP, 306 .linkdown_irq_regfield = LINK_DOWN, 307 .max_lanes = 2, 308 }; 309 310 static const struct j721e_pcie_data j7200_pcie_rc_data = { 311 .mode = PCI_MODE_RC, 312 .quirk_detect_quiet_flag = true, 313 .linkdown_irq_regfield = J7200_LINK_DOWN, 314 .byte_access_allowed = true, 315 .max_lanes = 2, 316 }; 317 318 static const struct j721e_pcie_data j7200_pcie_ep_data = { 319 .mode = PCI_MODE_EP, 320 .quirk_detect_quiet_flag = true, 321 .quirk_disable_flr = true, 322 .max_lanes = 2, 323 }; 324 325 static const struct j721e_pcie_data am64_pcie_rc_data = { 326 .mode = PCI_MODE_RC, 327 .linkdown_irq_regfield = J7200_LINK_DOWN, 328 .byte_access_allowed = true, 329 .max_lanes = 1, 330 }; 331 332 static const struct j721e_pcie_data am64_pcie_ep_data = { 333 .mode = PCI_MODE_EP, 334 .linkdown_irq_regfield = J7200_LINK_DOWN, 335 .max_lanes = 1, 336 }; 337 338 static const struct of_device_id of_j721e_pcie_match[] = { 339 { 340 .compatible = "ti,j721e-pcie-host", 341 .data = &j721e_pcie_rc_data, 342 }, 343 { 344 .compatible = "ti,j721e-pcie-ep", 345 .data = &j721e_pcie_ep_data, 346 }, 347 { 348 .compatible = "ti,j7200-pcie-host", 349 .data = &j7200_pcie_rc_data, 350 }, 351 { 352 .compatible = "ti,j7200-pcie-ep", 353 .data = &j7200_pcie_ep_data, 354 }, 355 { 356 .compatible = "ti,am64-pcie-host", 357 .data = &am64_pcie_rc_data, 358 }, 359 { 360 .compatible = "ti,am64-pcie-ep", 361 .data = &am64_pcie_ep_data, 362 }, 363 {}, 364 }; 365 366 static int j721e_pcie_probe(struct platform_device *pdev) 367 { 368 struct device *dev = &pdev->dev; 369 struct device_node *node = dev->of_node; 370 struct pci_host_bridge *bridge; 371 const struct j721e_pcie_data *data; 372 struct cdns_pcie *cdns_pcie; 373 struct j721e_pcie *pcie; 374 struct cdns_pcie_rc *rc = NULL; 375 struct cdns_pcie_ep *ep = NULL; 376 struct gpio_desc *gpiod; 377 void __iomem *base; 378 struct clk *clk; 379 u32 num_lanes; 380 u32 mode; 381 int ret; 382 int irq; 383 384 data = of_device_get_match_data(dev); 385 if (!data) 386 return -EINVAL; 387 388 mode = (u32)data->mode; 389 390 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 391 if (!pcie) 392 return -ENOMEM; 393 394 switch (mode) { 395 case PCI_MODE_RC: 396 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) 397 return -ENODEV; 398 399 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 400 if (!bridge) 401 return -ENOMEM; 402 403 if (!data->byte_access_allowed) 404 bridge->ops = &cdns_ti_pcie_host_ops; 405 rc = pci_host_bridge_priv(bridge); 406 rc->quirk_retrain_flag = data->quirk_retrain_flag; 407 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 408 409 cdns_pcie = &rc->pcie; 410 cdns_pcie->dev = dev; 411 cdns_pcie->ops = &j721e_pcie_ops; 412 pcie->cdns_pcie = cdns_pcie; 413 break; 414 case PCI_MODE_EP: 415 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) 416 return -ENODEV; 417 418 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 419 if (!ep) 420 return -ENOMEM; 421 422 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 423 ep->quirk_disable_flr = data->quirk_disable_flr; 424 425 cdns_pcie = &ep->pcie; 426 cdns_pcie->dev = dev; 427 cdns_pcie->ops = &j721e_pcie_ops; 428 pcie->cdns_pcie = cdns_pcie; 429 break; 430 default: 431 dev_err(dev, "INVALID device type %d\n", mode); 432 return 0; 433 } 434 435 pcie->mode = mode; 436 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; 437 438 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 439 if (IS_ERR(base)) 440 return PTR_ERR(base); 441 pcie->intd_cfg_base = base; 442 443 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 444 if (IS_ERR(base)) 445 return PTR_ERR(base); 446 pcie->user_cfg_base = base; 447 448 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 449 if (ret || num_lanes > data->max_lanes) { 450 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); 451 num_lanes = 1; 452 } 453 454 pcie->num_lanes = num_lanes; 455 pcie->max_lanes = data->max_lanes; 456 457 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 458 return -EINVAL; 459 460 irq = platform_get_irq_byname(pdev, "link_state"); 461 if (irq < 0) 462 return irq; 463 464 dev_set_drvdata(dev, pcie); 465 pm_runtime_enable(dev); 466 ret = pm_runtime_get_sync(dev); 467 if (ret < 0) { 468 dev_err(dev, "pm_runtime_get_sync failed\n"); 469 goto err_get_sync; 470 } 471 472 ret = j721e_pcie_ctrl_init(pcie); 473 if (ret < 0) { 474 dev_err(dev, "pm_runtime_get_sync failed\n"); 475 goto err_get_sync; 476 } 477 478 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 479 "j721e-pcie-link-down-irq", pcie); 480 if (ret < 0) { 481 dev_err(dev, "failed to request link state IRQ %d\n", irq); 482 goto err_get_sync; 483 } 484 485 j721e_pcie_config_link_irq(pcie); 486 487 switch (mode) { 488 case PCI_MODE_RC: 489 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 490 if (IS_ERR(gpiod)) { 491 ret = PTR_ERR(gpiod); 492 if (ret != -EPROBE_DEFER) 493 dev_err(dev, "Failed to get reset GPIO\n"); 494 goto err_get_sync; 495 } 496 pcie->reset_gpio = gpiod; 497 498 ret = cdns_pcie_init_phy(dev, cdns_pcie); 499 if (ret) { 500 dev_err(dev, "Failed to init phy\n"); 501 goto err_get_sync; 502 } 503 504 clk = devm_clk_get_optional(dev, "pcie_refclk"); 505 if (IS_ERR(clk)) { 506 ret = PTR_ERR(clk); 507 dev_err(dev, "failed to get pcie_refclk\n"); 508 goto err_pcie_setup; 509 } 510 511 ret = clk_prepare_enable(clk); 512 if (ret) { 513 dev_err(dev, "failed to enable pcie_refclk\n"); 514 goto err_pcie_setup; 515 } 516 pcie->refclk = clk; 517 518 /* 519 * Section 2.2 of the PCI Express Card Electromechanical 520 * Specification (Revision 5.1) mandates that the deassertion 521 * of the PERST# signal should be delayed by 100 ms (TPVPERL). 522 * This shall ensure that the power and the reference clock 523 * are stable. 524 */ 525 if (gpiod) { 526 msleep(PCIE_T_PVPERL_MS); 527 gpiod_set_value_cansleep(gpiod, 1); 528 } 529 530 ret = cdns_pcie_host_setup(rc); 531 if (ret < 0) { 532 clk_disable_unprepare(pcie->refclk); 533 goto err_pcie_setup; 534 } 535 536 break; 537 case PCI_MODE_EP: 538 ret = cdns_pcie_init_phy(dev, cdns_pcie); 539 if (ret) { 540 dev_err(dev, "Failed to init phy\n"); 541 goto err_get_sync; 542 } 543 544 ret = cdns_pcie_ep_setup(ep); 545 if (ret < 0) 546 goto err_pcie_setup; 547 548 break; 549 } 550 551 return 0; 552 553 err_pcie_setup: 554 cdns_pcie_disable_phy(cdns_pcie); 555 556 err_get_sync: 557 pm_runtime_put(dev); 558 pm_runtime_disable(dev); 559 560 return ret; 561 } 562 563 static void j721e_pcie_remove(struct platform_device *pdev) 564 { 565 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 566 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 567 struct device *dev = &pdev->dev; 568 569 clk_disable_unprepare(pcie->refclk); 570 cdns_pcie_disable_phy(cdns_pcie); 571 pm_runtime_put(dev); 572 pm_runtime_disable(dev); 573 } 574 575 static int j721e_pcie_suspend_noirq(struct device *dev) 576 { 577 struct j721e_pcie *pcie = dev_get_drvdata(dev); 578 579 if (pcie->mode == PCI_MODE_RC) { 580 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 581 clk_disable_unprepare(pcie->refclk); 582 } 583 584 cdns_pcie_disable_phy(pcie->cdns_pcie); 585 586 return 0; 587 } 588 589 static int j721e_pcie_resume_noirq(struct device *dev) 590 { 591 struct j721e_pcie *pcie = dev_get_drvdata(dev); 592 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 593 int ret; 594 595 ret = j721e_pcie_ctrl_init(pcie); 596 if (ret < 0) 597 return ret; 598 599 j721e_pcie_config_link_irq(pcie); 600 601 /* 602 * This is not called explicitly in the probe, it is called by 603 * cdns_pcie_init_phy(). 604 */ 605 ret = cdns_pcie_enable_phy(pcie->cdns_pcie); 606 if (ret < 0) 607 return ret; 608 609 if (pcie->mode == PCI_MODE_RC) { 610 struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie); 611 612 ret = clk_prepare_enable(pcie->refclk); 613 if (ret < 0) 614 return ret; 615 616 /* 617 * Section 2.2 of the PCI Express Card Electromechanical 618 * Specification (Revision 5.1) mandates that the deassertion 619 * of the PERST# signal should be delayed by 100 ms (TPVPERL). 620 * This shall ensure that the power and the reference clock 621 * are stable. 622 */ 623 if (pcie->reset_gpio) { 624 msleep(PCIE_T_PVPERL_MS); 625 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 626 } 627 628 ret = cdns_pcie_host_link_setup(rc); 629 if (ret < 0) { 630 clk_disable_unprepare(pcie->refclk); 631 return ret; 632 } 633 634 /* 635 * Reset internal status of BARs to force reinitialization in 636 * cdns_pcie_host_init(). 637 */ 638 for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++) 639 rc->avail_ib_bar[bar] = true; 640 641 ret = cdns_pcie_host_init(rc); 642 if (ret) { 643 clk_disable_unprepare(pcie->refclk); 644 return ret; 645 } 646 } 647 648 return 0; 649 } 650 651 static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops, 652 j721e_pcie_suspend_noirq, 653 j721e_pcie_resume_noirq); 654 655 static struct platform_driver j721e_pcie_driver = { 656 .probe = j721e_pcie_probe, 657 .remove_new = j721e_pcie_remove, 658 .driver = { 659 .name = "j721e-pcie", 660 .of_match_table = of_j721e_pcie_match, 661 .suppress_bind_attrs = true, 662 .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), 663 }, 664 }; 665 builtin_platform_driver(j721e_pcie_driver); 666