1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI Express I/O Virtualization (IOV) support 4 * Address Translation Service 1.0 5 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com> 6 * PASID support added by Joerg Roedel <joerg.roedel@amd.com> 7 * 8 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> 9 * Copyright (C) 2011 Advanced Micro Devices, 10 */ 11 12 #include <linux/export.h> 13 #include <linux/pci-ats.h> 14 #include <linux/pci.h> 15 #include <linux/slab.h> 16 17 #include "pci.h" 18 19 void pci_ats_init(struct pci_dev *dev) 20 { 21 int pos; 22 23 if (pci_ats_disabled()) 24 return; 25 26 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS); 27 if (!pos) 28 return; 29 30 dev->ats_cap = pos; 31 } 32 33 /** 34 * pci_enable_ats - enable the ATS capability 35 * @dev: the PCI device 36 * @ps: the IOMMU page shift 37 * 38 * Returns 0 on success, or negative on failure. 39 */ 40 int pci_enable_ats(struct pci_dev *dev, int ps) 41 { 42 u16 ctrl; 43 struct pci_dev *pdev; 44 45 if (!dev->ats_cap) 46 return -EINVAL; 47 48 if (WARN_ON(dev->ats_enabled)) 49 return -EBUSY; 50 51 if (ps < PCI_ATS_MIN_STU) 52 return -EINVAL; 53 54 /* 55 * Note that enabling ATS on a VF fails unless it's already enabled 56 * with the same STU on the PF. 57 */ 58 ctrl = PCI_ATS_CTRL_ENABLE; 59 if (dev->is_virtfn) { 60 pdev = pci_physfn(dev); 61 if (pdev->ats_stu != ps) 62 return -EINVAL; 63 } else { 64 dev->ats_stu = ps; 65 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); 66 } 67 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); 68 69 dev->ats_enabled = 1; 70 return 0; 71 } 72 EXPORT_SYMBOL_GPL(pci_enable_ats); 73 74 /** 75 * pci_disable_ats - disable the ATS capability 76 * @dev: the PCI device 77 */ 78 void pci_disable_ats(struct pci_dev *dev) 79 { 80 u16 ctrl; 81 82 if (WARN_ON(!dev->ats_enabled)) 83 return; 84 85 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl); 86 ctrl &= ~PCI_ATS_CTRL_ENABLE; 87 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); 88 89 dev->ats_enabled = 0; 90 } 91 EXPORT_SYMBOL_GPL(pci_disable_ats); 92 93 void pci_restore_ats_state(struct pci_dev *dev) 94 { 95 u16 ctrl; 96 97 if (!dev->ats_enabled) 98 return; 99 100 ctrl = PCI_ATS_CTRL_ENABLE; 101 if (!dev->is_virtfn) 102 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU); 103 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); 104 } 105 106 /** 107 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth 108 * @dev: the PCI device 109 * 110 * Returns the queue depth on success, or negative on failure. 111 * 112 * The ATS spec uses 0 in the Invalidate Queue Depth field to 113 * indicate that the function can accept 32 Invalidate Request. 114 * But here we use the `real' values (i.e. 1~32) for the Queue 115 * Depth; and 0 indicates the function shares the Queue with 116 * other functions (doesn't exclusively own a Queue). 117 */ 118 int pci_ats_queue_depth(struct pci_dev *dev) 119 { 120 u16 cap; 121 122 if (!dev->ats_cap) 123 return -EINVAL; 124 125 if (dev->is_virtfn) 126 return 0; 127 128 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap); 129 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP; 130 } 131 132 /** 133 * pci_ats_page_aligned - Return Page Aligned Request bit status. 134 * @pdev: the PCI device 135 * 136 * Returns 1, if the Untranslated Addresses generated by the device 137 * are always aligned or 0 otherwise. 138 * 139 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit 140 * is set, it indicates the Untranslated Addresses generated by the 141 * device are always aligned to a 4096 byte boundary. 142 */ 143 int pci_ats_page_aligned(struct pci_dev *pdev) 144 { 145 u16 cap; 146 147 if (!pdev->ats_cap) 148 return 0; 149 150 pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap); 151 152 if (cap & PCI_ATS_CAP_PAGE_ALIGNED) 153 return 1; 154 155 return 0; 156 } 157 158 #ifdef CONFIG_PCI_PRI 159 void pci_pri_init(struct pci_dev *pdev) 160 { 161 u16 status; 162 163 pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); 164 165 if (!pdev->pri_cap) 166 return; 167 168 pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status); 169 if (status & PCI_PRI_STATUS_PASID) 170 pdev->pasid_required = 1; 171 } 172 173 /** 174 * pci_enable_pri - Enable PRI capability 175 * @ pdev: PCI device structure 176 * 177 * Returns 0 on success, negative value on error 178 */ 179 int pci_enable_pri(struct pci_dev *pdev, u32 reqs) 180 { 181 u16 control, status; 182 u32 max_requests; 183 int pri = pdev->pri_cap; 184 185 /* 186 * VFs must not implement the PRI Capability. If their PF 187 * implements PRI, it is shared by the VFs, so if the PF PRI is 188 * enabled, it is also enabled for the VF. 189 */ 190 if (pdev->is_virtfn) { 191 if (pci_physfn(pdev)->pri_enabled) 192 return 0; 193 return -EINVAL; 194 } 195 196 if (WARN_ON(pdev->pri_enabled)) 197 return -EBUSY; 198 199 if (!pri) 200 return -EINVAL; 201 202 pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status); 203 if (!(status & PCI_PRI_STATUS_STOPPED)) 204 return -EBUSY; 205 206 pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests); 207 reqs = min(max_requests, reqs); 208 pdev->pri_reqs_alloc = reqs; 209 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs); 210 211 control = PCI_PRI_CTRL_ENABLE; 212 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); 213 214 pdev->pri_enabled = 1; 215 216 return 0; 217 } 218 219 /** 220 * pci_disable_pri - Disable PRI capability 221 * @pdev: PCI device structure 222 * 223 * Only clears the enabled-bit, regardless of its former value 224 */ 225 void pci_disable_pri(struct pci_dev *pdev) 226 { 227 u16 control; 228 int pri = pdev->pri_cap; 229 230 /* VFs share the PF PRI */ 231 if (pdev->is_virtfn) 232 return; 233 234 if (WARN_ON(!pdev->pri_enabled)) 235 return; 236 237 if (!pri) 238 return; 239 240 pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control); 241 control &= ~PCI_PRI_CTRL_ENABLE; 242 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); 243 244 pdev->pri_enabled = 0; 245 } 246 EXPORT_SYMBOL_GPL(pci_disable_pri); 247 248 /** 249 * pci_restore_pri_state - Restore PRI 250 * @pdev: PCI device structure 251 */ 252 void pci_restore_pri_state(struct pci_dev *pdev) 253 { 254 u16 control = PCI_PRI_CTRL_ENABLE; 255 u32 reqs = pdev->pri_reqs_alloc; 256 int pri = pdev->pri_cap; 257 258 if (pdev->is_virtfn) 259 return; 260 261 if (!pdev->pri_enabled) 262 return; 263 264 if (!pri) 265 return; 266 267 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs); 268 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); 269 } 270 271 /** 272 * pci_reset_pri - Resets device's PRI state 273 * @pdev: PCI device structure 274 * 275 * The PRI capability must be disabled before this function is called. 276 * Returns 0 on success, negative value on error. 277 */ 278 int pci_reset_pri(struct pci_dev *pdev) 279 { 280 u16 control; 281 int pri = pdev->pri_cap; 282 283 if (pdev->is_virtfn) 284 return 0; 285 286 if (WARN_ON(pdev->pri_enabled)) 287 return -EBUSY; 288 289 if (!pri) 290 return -EINVAL; 291 292 control = PCI_PRI_CTRL_RESET; 293 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control); 294 295 return 0; 296 } 297 298 /** 299 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit 300 * status. 301 * @pdev: PCI device structure 302 * 303 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise. 304 */ 305 int pci_prg_resp_pasid_required(struct pci_dev *pdev) 306 { 307 if (pdev->is_virtfn) 308 pdev = pci_physfn(pdev); 309 310 return pdev->pasid_required; 311 } 312 #endif /* CONFIG_PCI_PRI */ 313 314 #ifdef CONFIG_PCI_PASID 315 void pci_pasid_init(struct pci_dev *pdev) 316 { 317 pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); 318 } 319 320 /** 321 * pci_enable_pasid - Enable the PASID capability 322 * @pdev: PCI device structure 323 * @features: Features to enable 324 * 325 * Returns 0 on success, negative value on error. This function checks 326 * whether the features are actually supported by the device and returns 327 * an error if not. 328 */ 329 int pci_enable_pasid(struct pci_dev *pdev, int features) 330 { 331 u16 control, supported; 332 int pasid = pdev->pasid_cap; 333 334 /* 335 * VFs must not implement the PASID Capability, but if a PF 336 * supports PASID, its VFs share the PF PASID configuration. 337 */ 338 if (pdev->is_virtfn) { 339 if (pci_physfn(pdev)->pasid_enabled) 340 return 0; 341 return -EINVAL; 342 } 343 344 if (WARN_ON(pdev->pasid_enabled)) 345 return -EBUSY; 346 347 if (!pdev->eetlp_prefix_path) 348 return -EINVAL; 349 350 if (!pasid) 351 return -EINVAL; 352 353 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported); 354 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV; 355 356 /* User wants to enable anything unsupported? */ 357 if ((supported & features) != features) 358 return -EINVAL; 359 360 control = PCI_PASID_CTRL_ENABLE | features; 361 pdev->pasid_features = features; 362 363 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control); 364 365 pdev->pasid_enabled = 1; 366 367 return 0; 368 } 369 370 /** 371 * pci_disable_pasid - Disable the PASID capability 372 * @pdev: PCI device structure 373 */ 374 void pci_disable_pasid(struct pci_dev *pdev) 375 { 376 u16 control = 0; 377 int pasid = pdev->pasid_cap; 378 379 /* VFs share the PF PASID configuration */ 380 if (pdev->is_virtfn) 381 return; 382 383 if (WARN_ON(!pdev->pasid_enabled)) 384 return; 385 386 if (!pasid) 387 return; 388 389 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control); 390 391 pdev->pasid_enabled = 0; 392 } 393 394 /** 395 * pci_restore_pasid_state - Restore PASID capabilities 396 * @pdev: PCI device structure 397 */ 398 void pci_restore_pasid_state(struct pci_dev *pdev) 399 { 400 u16 control; 401 int pasid = pdev->pasid_cap; 402 403 if (pdev->is_virtfn) 404 return; 405 406 if (!pdev->pasid_enabled) 407 return; 408 409 if (!pasid) 410 return; 411 412 control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features; 413 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control); 414 } 415 416 /** 417 * pci_pasid_features - Check which PASID features are supported 418 * @pdev: PCI device structure 419 * 420 * Returns a negative value when no PASI capability is present. 421 * Otherwise is returns a bitmask with supported features. Current 422 * features reported are: 423 * PCI_PASID_CAP_EXEC - Execute permission supported 424 * PCI_PASID_CAP_PRIV - Privileged mode supported 425 */ 426 int pci_pasid_features(struct pci_dev *pdev) 427 { 428 u16 supported; 429 int pasid; 430 431 if (pdev->is_virtfn) 432 pdev = pci_physfn(pdev); 433 434 pasid = pdev->pasid_cap; 435 if (!pasid) 436 return -EINVAL; 437 438 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported); 439 440 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV; 441 442 return supported; 443 } 444 445 #define PASID_NUMBER_SHIFT 8 446 #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) 447 /** 448 * pci_max_pasid - Get maximum number of PASIDs supported by device 449 * @pdev: PCI device structure 450 * 451 * Returns negative value when PASID capability is not present. 452 * Otherwise it returns the number of supported PASIDs. 453 */ 454 int pci_max_pasids(struct pci_dev *pdev) 455 { 456 u16 supported; 457 int pasid; 458 459 if (pdev->is_virtfn) 460 pdev = pci_physfn(pdev); 461 462 pasid = pdev->pasid_cap; 463 if (!pasid) 464 return -EINVAL; 465 466 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported); 467 468 supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT; 469 470 return (1 << supported); 471 } 472 #endif /* CONFIG_PCI_PASID */ 473