1 #include <linux/delay.h> 2 #include <linux/pci.h> 3 #include <linux/module.h> 4 #include <linux/sched.h> 5 #include <linux/slab.h> 6 #include <linux/ioport.h> 7 #include <linux/wait.h> 8 9 #include "pci.h" 10 11 /* 12 * This interrupt-safe spinlock protects all accesses to PCI 13 * configuration space. 14 */ 15 16 static DEFINE_RAW_SPINLOCK(pci_lock); 17 18 /* 19 * Wrappers for all PCI configuration access functions. They just check 20 * alignment, do locking and call the low-level functions pointed to 21 * by pci_dev->ops. 22 */ 23 24 #define PCI_byte_BAD 0 25 #define PCI_word_BAD (pos & 1) 26 #define PCI_dword_BAD (pos & 3) 27 28 #define PCI_OP_READ(size,type,len) \ 29 int pci_bus_read_config_##size \ 30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ 31 { \ 32 int res; \ 33 unsigned long flags; \ 34 u32 data = 0; \ 35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 36 raw_spin_lock_irqsave(&pci_lock, flags); \ 37 res = bus->ops->read(bus, devfn, pos, len, &data); \ 38 *value = (type)data; \ 39 raw_spin_unlock_irqrestore(&pci_lock, flags); \ 40 return res; \ 41 } 42 43 #define PCI_OP_WRITE(size,type,len) \ 44 int pci_bus_write_config_##size \ 45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ 46 { \ 47 int res; \ 48 unsigned long flags; \ 49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 50 raw_spin_lock_irqsave(&pci_lock, flags); \ 51 res = bus->ops->write(bus, devfn, pos, len, value); \ 52 raw_spin_unlock_irqrestore(&pci_lock, flags); \ 53 return res; \ 54 } 55 56 PCI_OP_READ(byte, u8, 1) 57 PCI_OP_READ(word, u16, 2) 58 PCI_OP_READ(dword, u32, 4) 59 PCI_OP_WRITE(byte, u8, 1) 60 PCI_OP_WRITE(word, u16, 2) 61 PCI_OP_WRITE(dword, u32, 4) 62 63 EXPORT_SYMBOL(pci_bus_read_config_byte); 64 EXPORT_SYMBOL(pci_bus_read_config_word); 65 EXPORT_SYMBOL(pci_bus_read_config_dword); 66 EXPORT_SYMBOL(pci_bus_write_config_byte); 67 EXPORT_SYMBOL(pci_bus_write_config_word); 68 EXPORT_SYMBOL(pci_bus_write_config_dword); 69 70 /** 71 * pci_bus_set_ops - Set raw operations of pci bus 72 * @bus: pci bus struct 73 * @ops: new raw operations 74 * 75 * Return previous raw operations 76 */ 77 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops) 78 { 79 struct pci_ops *old_ops; 80 unsigned long flags; 81 82 raw_spin_lock_irqsave(&pci_lock, flags); 83 old_ops = bus->ops; 84 bus->ops = ops; 85 raw_spin_unlock_irqrestore(&pci_lock, flags); 86 return old_ops; 87 } 88 EXPORT_SYMBOL(pci_bus_set_ops); 89 90 /** 91 * pci_read_vpd - Read one entry from Vital Product Data 92 * @dev: pci device struct 93 * @pos: offset in vpd space 94 * @count: number of bytes to read 95 * @buf: pointer to where to store result 96 * 97 */ 98 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf) 99 { 100 if (!dev->vpd || !dev->vpd->ops) 101 return -ENODEV; 102 return dev->vpd->ops->read(dev, pos, count, buf); 103 } 104 EXPORT_SYMBOL(pci_read_vpd); 105 106 /** 107 * pci_write_vpd - Write entry to Vital Product Data 108 * @dev: pci device struct 109 * @pos: offset in vpd space 110 * @count: number of bytes to write 111 * @buf: buffer containing write data 112 * 113 */ 114 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf) 115 { 116 if (!dev->vpd || !dev->vpd->ops) 117 return -ENODEV; 118 return dev->vpd->ops->write(dev, pos, count, buf); 119 } 120 EXPORT_SYMBOL(pci_write_vpd); 121 122 /* 123 * The following routines are to prevent the user from accessing PCI config 124 * space when it's unsafe to do so. Some devices require this during BIST and 125 * we're required to prevent it during D-state transitions. 126 * 127 * We have a bit per device to indicate it's blocked and a global wait queue 128 * for callers to sleep on until devices are unblocked. 129 */ 130 static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait); 131 132 static noinline void pci_wait_ucfg(struct pci_dev *dev) 133 { 134 DECLARE_WAITQUEUE(wait, current); 135 136 __add_wait_queue(&pci_ucfg_wait, &wait); 137 do { 138 set_current_state(TASK_UNINTERRUPTIBLE); 139 raw_spin_unlock_irq(&pci_lock); 140 schedule(); 141 raw_spin_lock_irq(&pci_lock); 142 } while (dev->block_ucfg_access); 143 __remove_wait_queue(&pci_ucfg_wait, &wait); 144 } 145 146 #define PCI_USER_READ_CONFIG(size,type) \ 147 int pci_user_read_config_##size \ 148 (struct pci_dev *dev, int pos, type *val) \ 149 { \ 150 int ret = 0; \ 151 u32 data = -1; \ 152 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 153 raw_spin_lock_irq(&pci_lock); \ 154 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ 155 ret = dev->bus->ops->read(dev->bus, dev->devfn, \ 156 pos, sizeof(type), &data); \ 157 raw_spin_unlock_irq(&pci_lock); \ 158 *val = (type)data; \ 159 return ret; \ 160 } 161 162 #define PCI_USER_WRITE_CONFIG(size,type) \ 163 int pci_user_write_config_##size \ 164 (struct pci_dev *dev, int pos, type val) \ 165 { \ 166 int ret = -EIO; \ 167 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ 168 raw_spin_lock_irq(&pci_lock); \ 169 if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \ 170 ret = dev->bus->ops->write(dev->bus, dev->devfn, \ 171 pos, sizeof(type), val); \ 172 raw_spin_unlock_irq(&pci_lock); \ 173 return ret; \ 174 } 175 176 PCI_USER_READ_CONFIG(byte, u8) 177 PCI_USER_READ_CONFIG(word, u16) 178 PCI_USER_READ_CONFIG(dword, u32) 179 PCI_USER_WRITE_CONFIG(byte, u8) 180 PCI_USER_WRITE_CONFIG(word, u16) 181 PCI_USER_WRITE_CONFIG(dword, u32) 182 183 /* VPD access through PCI 2.2+ VPD capability */ 184 185 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1) 186 187 struct pci_vpd_pci22 { 188 struct pci_vpd base; 189 struct mutex lock; 190 u16 flag; 191 bool busy; 192 u8 cap; 193 }; 194 195 /* 196 * Wait for last operation to complete. 197 * This code has to spin since there is no other notification from the PCI 198 * hardware. Since the VPD is often implemented by serial attachment to an 199 * EEPROM, it may take many milliseconds to complete. 200 */ 201 static int pci_vpd_pci22_wait(struct pci_dev *dev) 202 { 203 struct pci_vpd_pci22 *vpd = 204 container_of(dev->vpd, struct pci_vpd_pci22, base); 205 unsigned long timeout = jiffies + HZ/20 + 2; 206 u16 status; 207 int ret; 208 209 if (!vpd->busy) 210 return 0; 211 212 for (;;) { 213 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR, 214 &status); 215 if (ret) 216 return ret; 217 218 if ((status & PCI_VPD_ADDR_F) == vpd->flag) { 219 vpd->busy = false; 220 return 0; 221 } 222 223 if (time_after(jiffies, timeout)) { 224 dev_printk(KERN_DEBUG, &dev->dev, 225 "vpd r/w failed. This is likely a firmware " 226 "bug on this device. Contact the card " 227 "vendor for a firmware update."); 228 return -ETIMEDOUT; 229 } 230 if (fatal_signal_pending(current)) 231 return -EINTR; 232 if (!cond_resched()) 233 udelay(10); 234 } 235 } 236 237 static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count, 238 void *arg) 239 { 240 struct pci_vpd_pci22 *vpd = 241 container_of(dev->vpd, struct pci_vpd_pci22, base); 242 int ret; 243 loff_t end = pos + count; 244 u8 *buf = arg; 245 246 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len) 247 return -EINVAL; 248 249 if (mutex_lock_killable(&vpd->lock)) 250 return -EINTR; 251 252 ret = pci_vpd_pci22_wait(dev); 253 if (ret < 0) 254 goto out; 255 256 while (pos < end) { 257 u32 val; 258 unsigned int i, skip; 259 260 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, 261 pos & ~3); 262 if (ret < 0) 263 break; 264 vpd->busy = true; 265 vpd->flag = PCI_VPD_ADDR_F; 266 ret = pci_vpd_pci22_wait(dev); 267 if (ret < 0) 268 break; 269 270 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); 271 if (ret < 0) 272 break; 273 274 skip = pos & 3; 275 for (i = 0; i < sizeof(u32); i++) { 276 if (i >= skip) { 277 *buf++ = val; 278 if (++pos == end) 279 break; 280 } 281 val >>= 8; 282 } 283 } 284 out: 285 mutex_unlock(&vpd->lock); 286 return ret ? ret : count; 287 } 288 289 static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count, 290 const void *arg) 291 { 292 struct pci_vpd_pci22 *vpd = 293 container_of(dev->vpd, struct pci_vpd_pci22, base); 294 const u8 *buf = arg; 295 loff_t end = pos + count; 296 int ret = 0; 297 298 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len) 299 return -EINVAL; 300 301 if (mutex_lock_killable(&vpd->lock)) 302 return -EINTR; 303 304 ret = pci_vpd_pci22_wait(dev); 305 if (ret < 0) 306 goto out; 307 308 while (pos < end) { 309 u32 val; 310 311 val = *buf++; 312 val |= *buf++ << 8; 313 val |= *buf++ << 16; 314 val |= *buf++ << 24; 315 316 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val); 317 if (ret < 0) 318 break; 319 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, 320 pos | PCI_VPD_ADDR_F); 321 if (ret < 0) 322 break; 323 324 vpd->busy = true; 325 vpd->flag = 0; 326 ret = pci_vpd_pci22_wait(dev); 327 328 pos += sizeof(u32); 329 } 330 out: 331 mutex_unlock(&vpd->lock); 332 return ret ? ret : count; 333 } 334 335 static void pci_vpd_pci22_release(struct pci_dev *dev) 336 { 337 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); 338 } 339 340 static const struct pci_vpd_ops pci_vpd_pci22_ops = { 341 .read = pci_vpd_pci22_read, 342 .write = pci_vpd_pci22_write, 343 .release = pci_vpd_pci22_release, 344 }; 345 346 int pci_vpd_pci22_init(struct pci_dev *dev) 347 { 348 struct pci_vpd_pci22 *vpd; 349 u8 cap; 350 351 cap = pci_find_capability(dev, PCI_CAP_ID_VPD); 352 if (!cap) 353 return -ENODEV; 354 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC); 355 if (!vpd) 356 return -ENOMEM; 357 358 vpd->base.len = PCI_VPD_PCI22_SIZE; 359 vpd->base.ops = &pci_vpd_pci22_ops; 360 mutex_init(&vpd->lock); 361 vpd->cap = cap; 362 vpd->busy = false; 363 dev->vpd = &vpd->base; 364 return 0; 365 } 366 367 /** 368 * pci_vpd_truncate - Set available Vital Product Data size 369 * @dev: pci device struct 370 * @size: available memory in bytes 371 * 372 * Adjust size of available VPD area. 373 */ 374 int pci_vpd_truncate(struct pci_dev *dev, size_t size) 375 { 376 if (!dev->vpd) 377 return -EINVAL; 378 379 /* limited by the access method */ 380 if (size > dev->vpd->len) 381 return -EINVAL; 382 383 dev->vpd->len = size; 384 if (dev->vpd->attr) 385 dev->vpd->attr->size = size; 386 387 return 0; 388 } 389 EXPORT_SYMBOL(pci_vpd_truncate); 390 391 /** 392 * pci_block_user_cfg_access - Block userspace PCI config reads/writes 393 * @dev: pci device struct 394 * 395 * When user access is blocked, any reads or writes to config space will 396 * sleep until access is unblocked again. We don't allow nesting of 397 * block/unblock calls. 398 */ 399 void pci_block_user_cfg_access(struct pci_dev *dev) 400 { 401 unsigned long flags; 402 int was_blocked; 403 404 raw_spin_lock_irqsave(&pci_lock, flags); 405 was_blocked = dev->block_ucfg_access; 406 dev->block_ucfg_access = 1; 407 raw_spin_unlock_irqrestore(&pci_lock, flags); 408 409 /* If we BUG() inside the pci_lock, we're guaranteed to hose 410 * the machine */ 411 BUG_ON(was_blocked); 412 } 413 EXPORT_SYMBOL_GPL(pci_block_user_cfg_access); 414 415 /** 416 * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes 417 * @dev: pci device struct 418 * 419 * This function allows userspace PCI config accesses to resume. 420 */ 421 void pci_unblock_user_cfg_access(struct pci_dev *dev) 422 { 423 unsigned long flags; 424 425 raw_spin_lock_irqsave(&pci_lock, flags); 426 427 /* This indicates a problem in the caller, but we don't need 428 * to kill them, unlike a double-block above. */ 429 WARN_ON(!dev->block_ucfg_access); 430 431 dev->block_ucfg_access = 0; 432 wake_up_all(&pci_ucfg_wait); 433 raw_spin_unlock_irqrestore(&pci_lock, flags); 434 } 435 EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access); 436