1 /* Low-level parallel-port routines for 8255-based PC-style hardware. 2 * 3 * Authors: Phil Blundell <philb@gnu.org> 4 * Tim Waugh <tim@cyberelk.demon.co.uk> 5 * Jose Renau <renau@acm.org> 6 * David Campbell 7 * Andrea Arcangeli 8 * 9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. 10 * 11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org> 12 * DMA support - Bert De Jonghe <bert@sophis.be> 13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. 15 * Various hacks, Fred Barnes, 04/2001 16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com> 17 */ 18 19 /* This driver should work with any hardware that is broadly compatible 20 * with that in the IBM PC. This applies to the majority of integrated 21 * I/O chipsets that are commonly available. The expected register 22 * layout is: 23 * 24 * base+0 data 25 * base+1 status 26 * base+2 control 27 * 28 * In addition, there are some optional registers: 29 * 30 * base+3 EPP address 31 * base+4 EPP data 32 * base+0x400 ECP config A 33 * base+0x401 ECP config B 34 * base+0x402 ECP control 35 * 36 * All registers are 8 bits wide and read/write. If your hardware differs 37 * only in register addresses (eg because your registers are on 32-bit 38 * word boundaries) then you can alter the constants in parport_pc.h to 39 * accommodate this. 40 * 41 * Note that the ECP registers may not start at offset 0x400 for PCI cards, 42 * but rather will start at port->base_hi. 43 */ 44 45 #include <linux/module.h> 46 #include <linux/init.h> 47 #include <linux/sched.h> 48 #include <linux/delay.h> 49 #include <linux/errno.h> 50 #include <linux/interrupt.h> 51 #include <linux/ioport.h> 52 #include <linux/kernel.h> 53 #include <linux/slab.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/pci.h> 56 #include <linux/pnp.h> 57 #include <linux/platform_device.h> 58 #include <linux/sysctl.h> 59 60 #include <asm/io.h> 61 #include <asm/dma.h> 62 #include <asm/uaccess.h> 63 64 #include <linux/parport.h> 65 #include <linux/parport_pc.h> 66 #include <linux/via.h> 67 #include <asm/parport.h> 68 69 #define PARPORT_PC_MAX_PORTS PARPORT_MAX 70 71 #ifdef CONFIG_ISA_DMA_API 72 #define HAS_DMA 73 #endif 74 75 /* ECR modes */ 76 #define ECR_SPP 00 77 #define ECR_PS2 01 78 #define ECR_PPF 02 79 #define ECR_ECP 03 80 #define ECR_EPP 04 81 #define ECR_VND 05 82 #define ECR_TST 06 83 #define ECR_CNF 07 84 #define ECR_MODE_MASK 0xe0 85 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v)) 86 87 #undef DEBUG 88 89 #ifdef DEBUG 90 #define DPRINTK printk 91 #else 92 #define DPRINTK(stuff...) 93 #endif 94 95 96 #define NR_SUPERIOS 3 97 static struct superio_struct { /* For Super-IO chips autodetection */ 98 int io; 99 int irq; 100 int dma; 101 } superios[NR_SUPERIOS] = { {0,},}; 102 103 static int user_specified; 104 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 106 static int verbose_probing; 107 #endif 108 static int pci_registered_parport; 109 static int pnp_registered_parport; 110 111 /* frob_control, but for ECR */ 112 static void frob_econtrol (struct parport *pb, unsigned char m, 113 unsigned char v) 114 { 115 unsigned char ectr = 0; 116 117 if (m != 0xff) 118 ectr = inb (ECONTROL (pb)); 119 120 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", 121 m, v, ectr, (ectr & ~m) ^ v); 122 123 outb ((ectr & ~m) ^ v, ECONTROL (pb)); 124 } 125 126 static __inline__ void frob_set_mode (struct parport *p, int mode) 127 { 128 frob_econtrol (p, ECR_MODE_MASK, mode << 5); 129 } 130 131 #ifdef CONFIG_PARPORT_PC_FIFO 132 /* Safely change the mode bits in the ECR 133 Returns: 134 0 : Success 135 -EBUSY: Could not drain FIFO in some finite amount of time, 136 mode not changed! 137 */ 138 static int change_mode(struct parport *p, int m) 139 { 140 const struct parport_pc_private *priv = p->physport->private_data; 141 unsigned char oecr; 142 int mode; 143 144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m); 145 146 if (!priv->ecr) { 147 printk (KERN_DEBUG "change_mode: but there's no ECR!\n"); 148 return 0; 149 } 150 151 /* Bits <7:5> contain the mode. */ 152 oecr = inb (ECONTROL (p)); 153 mode = (oecr >> 5) & 0x7; 154 if (mode == m) return 0; 155 156 if (mode >= 2 && !(priv->ctr & 0x20)) { 157 /* This mode resets the FIFO, so we may 158 * have to wait for it to drain first. */ 159 unsigned long expire = jiffies + p->physport->cad->timeout; 160 int counter; 161 switch (mode) { 162 case ECR_PPF: /* Parallel Port FIFO mode */ 163 case ECR_ECP: /* ECP Parallel Port mode */ 164 /* Busy wait for 200us */ 165 for (counter = 0; counter < 40; counter++) { 166 if (inb (ECONTROL (p)) & 0x01) 167 break; 168 if (signal_pending (current)) break; 169 udelay (5); 170 } 171 172 /* Poll slowly. */ 173 while (!(inb (ECONTROL (p)) & 0x01)) { 174 if (time_after_eq (jiffies, expire)) 175 /* The FIFO is stuck. */ 176 return -EBUSY; 177 schedule_timeout_interruptible(msecs_to_jiffies(10)); 178 if (signal_pending (current)) 179 break; 180 } 181 } 182 } 183 184 if (mode >= 2 && m >= 2) { 185 /* We have to go through mode 001 */ 186 oecr &= ~(7 << 5); 187 oecr |= ECR_PS2 << 5; 188 ECR_WRITE (p, oecr); 189 } 190 191 /* Set the mode. */ 192 oecr &= ~(7 << 5); 193 oecr |= m << 5; 194 ECR_WRITE (p, oecr); 195 return 0; 196 } 197 198 #ifdef CONFIG_PARPORT_1284 199 /* Find FIFO lossage; FIFO is reset */ 200 #if 0 201 static int get_fifo_residue (struct parport *p) 202 { 203 int residue; 204 int cnfga; 205 const struct parport_pc_private *priv = p->physport->private_data; 206 207 /* Adjust for the contents of the FIFO. */ 208 for (residue = priv->fifo_depth; ; residue--) { 209 if (inb (ECONTROL (p)) & 0x2) 210 /* Full up. */ 211 break; 212 213 outb (0, FIFO (p)); 214 } 215 216 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name, 217 residue); 218 219 /* Reset the FIFO. */ 220 frob_set_mode (p, ECR_PS2); 221 222 /* Now change to config mode and clean up. FIXME */ 223 frob_set_mode (p, ECR_CNF); 224 cnfga = inb (CONFIGA (p)); 225 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga); 226 227 if (!(cnfga & (1<<2))) { 228 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name); 229 residue++; 230 } 231 232 /* Don't care about partial PWords until support is added for 233 * PWord != 1 byte. */ 234 235 /* Back to PS2 mode. */ 236 frob_set_mode (p, ECR_PS2); 237 238 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p))); 239 return residue; 240 } 241 #endif /* 0 */ 242 #endif /* IEEE 1284 support */ 243 #endif /* FIFO support */ 244 245 /* 246 * Clear TIMEOUT BIT in EPP MODE 247 * 248 * This is also used in SPP detection. 249 */ 250 static int clear_epp_timeout(struct parport *pb) 251 { 252 unsigned char r; 253 254 if (!(parport_pc_read_status(pb) & 0x01)) 255 return 1; 256 257 /* To clear timeout some chips require double read */ 258 parport_pc_read_status(pb); 259 r = parport_pc_read_status(pb); 260 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */ 261 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */ 262 r = parport_pc_read_status(pb); 263 264 return !(r & 0x01); 265 } 266 267 /* 268 * Access functions. 269 * 270 * Most of these aren't static because they may be used by the 271 * parport_xxx_yyy macros. extern __inline__ versions of several 272 * of these are in parport_pc.h. 273 */ 274 275 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s) 276 { 277 s->u.pc.ctr = 0xc; 278 if (dev->irq_func && 279 dev->port->irq != PARPORT_IRQ_NONE) 280 /* Set ackIntEn */ 281 s->u.pc.ctr |= 0x10; 282 283 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; 284 * D.Gruszka VScom */ 285 } 286 287 static void parport_pc_save_state(struct parport *p, struct parport_state *s) 288 { 289 const struct parport_pc_private *priv = p->physport->private_data; 290 s->u.pc.ctr = priv->ctr; 291 if (priv->ecr) 292 s->u.pc.ecr = inb (ECONTROL (p)); 293 } 294 295 static void parport_pc_restore_state(struct parport *p, struct parport_state *s) 296 { 297 struct parport_pc_private *priv = p->physport->private_data; 298 register unsigned char c = s->u.pc.ctr & priv->ctr_writable; 299 outb (c, CONTROL (p)); 300 priv->ctr = c; 301 if (priv->ecr) 302 ECR_WRITE (p, s->u.pc.ecr); 303 } 304 305 #ifdef CONFIG_PARPORT_1284 306 static size_t parport_pc_epp_read_data (struct parport *port, void *buf, 307 size_t length, int flags) 308 { 309 size_t got = 0; 310 311 if (flags & PARPORT_W91284PIC) { 312 unsigned char status; 313 size_t left = length; 314 315 /* use knowledge about data lines..: 316 * nFault is 0 if there is at least 1 byte in the Warp's FIFO 317 * pError is 1 if there are 16 bytes in the Warp's FIFO 318 */ 319 status = inb (STATUS (port)); 320 321 while (!(status & 0x08) && (got < length)) { 322 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) { 323 /* can grab 16 bytes from warp fifo */ 324 if (!((long)buf & 0x03)) { 325 insl (EPPDATA (port), buf, 4); 326 } else { 327 insb (EPPDATA (port), buf, 16); 328 } 329 buf += 16; 330 got += 16; 331 left -= 16; 332 } else { 333 /* grab single byte from the warp fifo */ 334 *((char *)buf) = inb (EPPDATA (port)); 335 buf++; 336 got++; 337 left--; 338 } 339 status = inb (STATUS (port)); 340 if (status & 0x01) { 341 /* EPP timeout should never occur... */ 342 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to " 343 "w91284pic (should not have done)\n", port->name); 344 clear_epp_timeout (port); 345 } 346 } 347 return got; 348 } 349 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 350 if (!(((long)buf | length) & 0x03)) { 351 insl (EPPDATA (port), buf, (length >> 2)); 352 } else { 353 insb (EPPDATA (port), buf, length); 354 } 355 if (inb (STATUS (port)) & 0x01) { 356 clear_epp_timeout (port); 357 return -EIO; 358 } 359 return length; 360 } 361 for (; got < length; got++) { 362 *((char*)buf) = inb (EPPDATA(port)); 363 buf++; 364 if (inb (STATUS (port)) & 0x01) { 365 /* EPP timeout */ 366 clear_epp_timeout (port); 367 break; 368 } 369 } 370 371 return got; 372 } 373 374 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf, 375 size_t length, int flags) 376 { 377 size_t written = 0; 378 379 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 380 if (!(((long)buf | length) & 0x03)) { 381 outsl (EPPDATA (port), buf, (length >> 2)); 382 } else { 383 outsb (EPPDATA (port), buf, length); 384 } 385 if (inb (STATUS (port)) & 0x01) { 386 clear_epp_timeout (port); 387 return -EIO; 388 } 389 return length; 390 } 391 for (; written < length; written++) { 392 outb (*((char*)buf), EPPDATA(port)); 393 buf++; 394 if (inb (STATUS(port)) & 0x01) { 395 clear_epp_timeout (port); 396 break; 397 } 398 } 399 400 return written; 401 } 402 403 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf, 404 size_t length, int flags) 405 { 406 size_t got = 0; 407 408 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 409 insb (EPPADDR (port), buf, length); 410 if (inb (STATUS (port)) & 0x01) { 411 clear_epp_timeout (port); 412 return -EIO; 413 } 414 return length; 415 } 416 for (; got < length; got++) { 417 *((char*)buf) = inb (EPPADDR (port)); 418 buf++; 419 if (inb (STATUS (port)) & 0x01) { 420 clear_epp_timeout (port); 421 break; 422 } 423 } 424 425 return got; 426 } 427 428 static size_t parport_pc_epp_write_addr (struct parport *port, 429 const void *buf, size_t length, 430 int flags) 431 { 432 size_t written = 0; 433 434 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 435 outsb (EPPADDR (port), buf, length); 436 if (inb (STATUS (port)) & 0x01) { 437 clear_epp_timeout (port); 438 return -EIO; 439 } 440 return length; 441 } 442 for (; written < length; written++) { 443 outb (*((char*)buf), EPPADDR (port)); 444 buf++; 445 if (inb (STATUS (port)) & 0x01) { 446 clear_epp_timeout (port); 447 break; 448 } 449 } 450 451 return written; 452 } 453 454 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf, 455 size_t length, int flags) 456 { 457 size_t got; 458 459 frob_set_mode (port, ECR_EPP); 460 parport_pc_data_reverse (port); 461 parport_pc_write_control (port, 0x4); 462 got = parport_pc_epp_read_data (port, buf, length, flags); 463 frob_set_mode (port, ECR_PS2); 464 465 return got; 466 } 467 468 static size_t parport_pc_ecpepp_write_data (struct parport *port, 469 const void *buf, size_t length, 470 int flags) 471 { 472 size_t written; 473 474 frob_set_mode (port, ECR_EPP); 475 parport_pc_write_control (port, 0x4); 476 parport_pc_data_forward (port); 477 written = parport_pc_epp_write_data (port, buf, length, flags); 478 frob_set_mode (port, ECR_PS2); 479 480 return written; 481 } 482 483 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf, 484 size_t length, int flags) 485 { 486 size_t got; 487 488 frob_set_mode (port, ECR_EPP); 489 parport_pc_data_reverse (port); 490 parport_pc_write_control (port, 0x4); 491 got = parport_pc_epp_read_addr (port, buf, length, flags); 492 frob_set_mode (port, ECR_PS2); 493 494 return got; 495 } 496 497 static size_t parport_pc_ecpepp_write_addr (struct parport *port, 498 const void *buf, size_t length, 499 int flags) 500 { 501 size_t written; 502 503 frob_set_mode (port, ECR_EPP); 504 parport_pc_write_control (port, 0x4); 505 parport_pc_data_forward (port); 506 written = parport_pc_epp_write_addr (port, buf, length, flags); 507 frob_set_mode (port, ECR_PS2); 508 509 return written; 510 } 511 #endif /* IEEE 1284 support */ 512 513 #ifdef CONFIG_PARPORT_PC_FIFO 514 static size_t parport_pc_fifo_write_block_pio (struct parport *port, 515 const void *buf, size_t length) 516 { 517 int ret = 0; 518 const unsigned char *bufp = buf; 519 size_t left = length; 520 unsigned long expire = jiffies + port->physport->cad->timeout; 521 const int fifo = FIFO (port); 522 int poll_for = 8; /* 80 usecs */ 523 const struct parport_pc_private *priv = port->physport->private_data; 524 const int fifo_depth = priv->fifo_depth; 525 526 port = port->physport; 527 528 /* We don't want to be interrupted every character. */ 529 parport_pc_disable_irq (port); 530 /* set nErrIntrEn and serviceIntr */ 531 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 532 533 /* Forward mode. */ 534 parport_pc_data_forward (port); /* Must be in PS2 mode */ 535 536 while (left) { 537 unsigned char byte; 538 unsigned char ecrval = inb (ECONTROL (port)); 539 int i = 0; 540 541 if (need_resched() && time_before (jiffies, expire)) 542 /* Can't yield the port. */ 543 schedule (); 544 545 /* Anyone else waiting for the port? */ 546 if (port->waithead) { 547 printk (KERN_DEBUG "Somebody wants the port\n"); 548 break; 549 } 550 551 if (ecrval & 0x02) { 552 /* FIFO is full. Wait for interrupt. */ 553 554 /* Clear serviceIntr */ 555 ECR_WRITE (port, ecrval & ~(1<<2)); 556 false_alarm: 557 ret = parport_wait_event (port, HZ); 558 if (ret < 0) break; 559 ret = 0; 560 if (!time_before (jiffies, expire)) { 561 /* Timed out. */ 562 printk (KERN_DEBUG "FIFO write timed out\n"); 563 break; 564 } 565 ecrval = inb (ECONTROL (port)); 566 if (!(ecrval & (1<<2))) { 567 if (need_resched() && 568 time_before (jiffies, expire)) 569 schedule (); 570 571 goto false_alarm; 572 } 573 574 continue; 575 } 576 577 /* Can't fail now. */ 578 expire = jiffies + port->cad->timeout; 579 580 poll: 581 if (signal_pending (current)) 582 break; 583 584 if (ecrval & 0x01) { 585 /* FIFO is empty. Blast it full. */ 586 const int n = left < fifo_depth ? left : fifo_depth; 587 outsb (fifo, bufp, n); 588 bufp += n; 589 left -= n; 590 591 /* Adjust the poll time. */ 592 if (i < (poll_for - 2)) poll_for--; 593 continue; 594 } else if (i++ < poll_for) { 595 udelay (10); 596 ecrval = inb (ECONTROL (port)); 597 goto poll; 598 } 599 600 /* Half-full (call me an optimist) */ 601 byte = *bufp++; 602 outb (byte, fifo); 603 left--; 604 } 605 606 dump_parport_state ("leave fifo_write_block_pio", port); 607 return length - left; 608 } 609 610 #ifdef HAS_DMA 611 static size_t parport_pc_fifo_write_block_dma (struct parport *port, 612 const void *buf, size_t length) 613 { 614 int ret = 0; 615 unsigned long dmaflag; 616 size_t left = length; 617 const struct parport_pc_private *priv = port->physport->private_data; 618 struct device *dev = port->physport->dev; 619 dma_addr_t dma_addr, dma_handle; 620 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ 621 unsigned long start = (unsigned long) buf; 622 unsigned long end = (unsigned long) buf + length - 1; 623 624 dump_parport_state ("enter fifo_write_block_dma", port); 625 if (end < MAX_DMA_ADDRESS) { 626 /* If it would cross a 64k boundary, cap it at the end. */ 627 if ((start ^ end) & ~0xffffUL) 628 maxlen = 0x10000 - (start & 0xffff); 629 630 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, 631 DMA_TO_DEVICE); 632 } else { 633 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */ 634 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ 635 dma_addr = priv->dma_handle; 636 dma_handle = 0; 637 } 638 639 port = port->physport; 640 641 /* We don't want to be interrupted every character. */ 642 parport_pc_disable_irq (port); 643 /* set nErrIntrEn and serviceIntr */ 644 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 645 646 /* Forward mode. */ 647 parport_pc_data_forward (port); /* Must be in PS2 mode */ 648 649 while (left) { 650 unsigned long expire = jiffies + port->physport->cad->timeout; 651 652 size_t count = left; 653 654 if (count > maxlen) 655 count = maxlen; 656 657 if (!dma_handle) /* bounce buffer ! */ 658 memcpy(priv->dma_buf, buf, count); 659 660 dmaflag = claim_dma_lock(); 661 disable_dma(port->dma); 662 clear_dma_ff(port->dma); 663 set_dma_mode(port->dma, DMA_MODE_WRITE); 664 set_dma_addr(port->dma, dma_addr); 665 set_dma_count(port->dma, count); 666 667 /* Set DMA mode */ 668 frob_econtrol (port, 1<<3, 1<<3); 669 670 /* Clear serviceIntr */ 671 frob_econtrol (port, 1<<2, 0); 672 673 enable_dma(port->dma); 674 release_dma_lock(dmaflag); 675 676 /* assume DMA will be successful */ 677 left -= count; 678 buf += count; 679 if (dma_handle) dma_addr += count; 680 681 /* Wait for interrupt. */ 682 false_alarm: 683 ret = parport_wait_event (port, HZ); 684 if (ret < 0) break; 685 ret = 0; 686 if (!time_before (jiffies, expire)) { 687 /* Timed out. */ 688 printk (KERN_DEBUG "DMA write timed out\n"); 689 break; 690 } 691 /* Is serviceIntr set? */ 692 if (!(inb (ECONTROL (port)) & (1<<2))) { 693 cond_resched(); 694 695 goto false_alarm; 696 } 697 698 dmaflag = claim_dma_lock(); 699 disable_dma(port->dma); 700 clear_dma_ff(port->dma); 701 count = get_dma_residue(port->dma); 702 release_dma_lock(dmaflag); 703 704 cond_resched(); /* Can't yield the port. */ 705 706 /* Anyone else waiting for the port? */ 707 if (port->waithead) { 708 printk (KERN_DEBUG "Somebody wants the port\n"); 709 break; 710 } 711 712 /* update for possible DMA residue ! */ 713 buf -= count; 714 left += count; 715 if (dma_handle) dma_addr -= count; 716 } 717 718 /* Maybe got here through break, so adjust for DMA residue! */ 719 dmaflag = claim_dma_lock(); 720 disable_dma(port->dma); 721 clear_dma_ff(port->dma); 722 left += get_dma_residue(port->dma); 723 release_dma_lock(dmaflag); 724 725 /* Turn off DMA mode */ 726 frob_econtrol (port, 1<<3, 0); 727 728 if (dma_handle) 729 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); 730 731 dump_parport_state ("leave fifo_write_block_dma", port); 732 return length - left; 733 } 734 #endif 735 736 static inline size_t parport_pc_fifo_write_block(struct parport *port, 737 const void *buf, size_t length) 738 { 739 #ifdef HAS_DMA 740 if (port->dma != PARPORT_DMA_NONE) 741 return parport_pc_fifo_write_block_dma (port, buf, length); 742 #endif 743 return parport_pc_fifo_write_block_pio (port, buf, length); 744 } 745 746 /* Parallel Port FIFO mode (ECP chipsets) */ 747 static size_t parport_pc_compat_write_block_pio (struct parport *port, 748 const void *buf, size_t length, 749 int flags) 750 { 751 size_t written; 752 int r; 753 unsigned long expire; 754 const struct parport_pc_private *priv = port->physport->private_data; 755 756 /* Special case: a timeout of zero means we cannot call schedule(). 757 * Also if O_NONBLOCK is set then use the default implementation. */ 758 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 759 return parport_ieee1284_write_compat (port, buf, 760 length, flags); 761 762 /* Set up parallel port FIFO mode.*/ 763 parport_pc_data_forward (port); /* Must be in PS2 mode */ 764 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0); 765 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */ 766 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name); 767 768 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 769 770 /* Write the data to the FIFO. */ 771 written = parport_pc_fifo_write_block(port, buf, length); 772 773 /* Finish up. */ 774 /* For some hardware we don't want to touch the mode until 775 * the FIFO is empty, so allow 4 seconds for each position 776 * in the fifo. 777 */ 778 expire = jiffies + (priv->fifo_depth * HZ * 4); 779 do { 780 /* Wait for the FIFO to empty */ 781 r = change_mode (port, ECR_PS2); 782 if (r != -EBUSY) { 783 break; 784 } 785 } while (time_before (jiffies, expire)); 786 if (r == -EBUSY) { 787 788 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 789 790 /* Prevent further data transfer. */ 791 frob_set_mode (port, ECR_TST); 792 793 /* Adjust for the contents of the FIFO. */ 794 for (written -= priv->fifo_depth; ; written++) { 795 if (inb (ECONTROL (port)) & 0x2) { 796 /* Full up. */ 797 break; 798 } 799 outb (0, FIFO (port)); 800 } 801 802 /* Reset the FIFO and return to PS2 mode. */ 803 frob_set_mode (port, ECR_PS2); 804 } 805 806 r = parport_wait_peripheral (port, 807 PARPORT_STATUS_BUSY, 808 PARPORT_STATUS_BUSY); 809 if (r) 810 printk (KERN_DEBUG 811 "%s: BUSY timeout (%d) in compat_write_block_pio\n", 812 port->name, r); 813 814 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 815 816 return written; 817 } 818 819 /* ECP */ 820 #ifdef CONFIG_PARPORT_1284 821 static size_t parport_pc_ecp_write_block_pio (struct parport *port, 822 const void *buf, size_t length, 823 int flags) 824 { 825 size_t written; 826 int r; 827 unsigned long expire; 828 const struct parport_pc_private *priv = port->physport->private_data; 829 830 /* Special case: a timeout of zero means we cannot call schedule(). 831 * Also if O_NONBLOCK is set then use the default implementation. */ 832 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 833 return parport_ieee1284_ecp_write_data (port, buf, 834 length, flags); 835 836 /* Switch to forward mode if necessary. */ 837 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 838 /* Event 47: Set nInit high. */ 839 parport_frob_control (port, 840 PARPORT_CONTROL_INIT 841 | PARPORT_CONTROL_AUTOFD, 842 PARPORT_CONTROL_INIT 843 | PARPORT_CONTROL_AUTOFD); 844 845 /* Event 49: PError goes high. */ 846 r = parport_wait_peripheral (port, 847 PARPORT_STATUS_PAPEROUT, 848 PARPORT_STATUS_PAPEROUT); 849 if (r) { 850 printk (KERN_DEBUG "%s: PError timeout (%d) " 851 "in ecp_write_block_pio\n", port->name, r); 852 } 853 } 854 855 /* Set up ECP parallel port mode.*/ 856 parport_pc_data_forward (port); /* Must be in PS2 mode */ 857 parport_pc_frob_control (port, 858 PARPORT_CONTROL_STROBE | 859 PARPORT_CONTROL_AUTOFD, 860 0); 861 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 862 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 863 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 864 865 /* Write the data to the FIFO. */ 866 written = parport_pc_fifo_write_block(port, buf, length); 867 868 /* Finish up. */ 869 /* For some hardware we don't want to touch the mode until 870 * the FIFO is empty, so allow 4 seconds for each position 871 * in the fifo. 872 */ 873 expire = jiffies + (priv->fifo_depth * (HZ * 4)); 874 do { 875 /* Wait for the FIFO to empty */ 876 r = change_mode (port, ECR_PS2); 877 if (r != -EBUSY) { 878 break; 879 } 880 } while (time_before (jiffies, expire)); 881 if (r == -EBUSY) { 882 883 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 884 885 /* Prevent further data transfer. */ 886 frob_set_mode (port, ECR_TST); 887 888 /* Adjust for the contents of the FIFO. */ 889 for (written -= priv->fifo_depth; ; written++) { 890 if (inb (ECONTROL (port)) & 0x2) { 891 /* Full up. */ 892 break; 893 } 894 outb (0, FIFO (port)); 895 } 896 897 /* Reset the FIFO and return to PS2 mode. */ 898 frob_set_mode (port, ECR_PS2); 899 900 /* Host transfer recovery. */ 901 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 902 udelay (5); 903 parport_frob_control (port, PARPORT_CONTROL_INIT, 0); 904 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 905 if (r) 906 printk (KERN_DEBUG "%s: PE,1 timeout (%d) " 907 "in ecp_write_block_pio\n", port->name, r); 908 909 parport_frob_control (port, 910 PARPORT_CONTROL_INIT, 911 PARPORT_CONTROL_INIT); 912 r = parport_wait_peripheral (port, 913 PARPORT_STATUS_PAPEROUT, 914 PARPORT_STATUS_PAPEROUT); 915 if (r) 916 printk (KERN_DEBUG "%s: PE,2 timeout (%d) " 917 "in ecp_write_block_pio\n", port->name, r); 918 } 919 920 r = parport_wait_peripheral (port, 921 PARPORT_STATUS_BUSY, 922 PARPORT_STATUS_BUSY); 923 if(r) 924 printk (KERN_DEBUG 925 "%s: BUSY timeout (%d) in ecp_write_block_pio\n", 926 port->name, r); 927 928 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 929 930 return written; 931 } 932 933 #if 0 934 static size_t parport_pc_ecp_read_block_pio (struct parport *port, 935 void *buf, size_t length, 936 int flags) 937 { 938 size_t left = length; 939 size_t fifofull; 940 int r; 941 const int fifo = FIFO(port); 942 const struct parport_pc_private *priv = port->physport->private_data; 943 const int fifo_depth = priv->fifo_depth; 944 char *bufp = buf; 945 946 port = port->physport; 947 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n"); 948 dump_parport_state ("enter fcn", port); 949 950 /* Special case: a timeout of zero means we cannot call schedule(). 951 * Also if O_NONBLOCK is set then use the default implementation. */ 952 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 953 return parport_ieee1284_ecp_read_data (port, buf, 954 length, flags); 955 956 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) { 957 /* If the peripheral is allowed to send RLE compressed 958 * data, it is possible for a byte to expand to 128 959 * bytes in the FIFO. */ 960 fifofull = 128; 961 } else { 962 fifofull = fifo_depth; 963 } 964 965 /* If the caller wants less than a full FIFO's worth of data, 966 * go through software emulation. Otherwise we may have to throw 967 * away data. */ 968 if (length < fifofull) 969 return parport_ieee1284_ecp_read_data (port, buf, 970 length, flags); 971 972 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) { 973 /* change to reverse-idle phase (must be in forward-idle) */ 974 975 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */ 976 parport_frob_control (port, 977 PARPORT_CONTROL_AUTOFD 978 | PARPORT_CONTROL_STROBE, 979 PARPORT_CONTROL_AUTOFD); 980 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 981 udelay (5); 982 /* Event 39: Set nInit low to initiate bus reversal */ 983 parport_frob_control (port, 984 PARPORT_CONTROL_INIT, 985 0); 986 /* Event 40: Wait for nAckReverse (PError) to go low */ 987 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 988 if (r) { 989 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) " 990 "in ecp_read_block_pio\n", port->name, r); 991 return 0; 992 } 993 } 994 995 /* Set up ECP FIFO mode.*/ 996 /* parport_pc_frob_control (port, 997 PARPORT_CONTROL_STROBE | 998 PARPORT_CONTROL_AUTOFD, 999 PARPORT_CONTROL_AUTOFD); */ 1000 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 1001 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 1002 1003 port->ieee1284.phase = IEEE1284_PH_REV_DATA; 1004 1005 /* the first byte must be collected manually */ 1006 dump_parport_state ("pre 43", port); 1007 /* Event 43: Wait for nAck to go low */ 1008 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); 1009 if (r) { 1010 /* timed out while reading -- no data */ 1011 printk (KERN_DEBUG "PIO read timed out (initial byte)\n"); 1012 goto out_no_data; 1013 } 1014 /* read byte */ 1015 *bufp++ = inb (DATA (port)); 1016 left--; 1017 dump_parport_state ("43-44", port); 1018 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */ 1019 parport_pc_frob_control (port, 1020 PARPORT_CONTROL_AUTOFD, 1021 0); 1022 dump_parport_state ("pre 45", port); 1023 /* Event 45: Wait for nAck to go high */ 1024 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */ 1025 dump_parport_state ("post 45", port); 1026 r = 0; 1027 if (r) { 1028 /* timed out while waiting for peripheral to respond to ack */ 1029 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n"); 1030 1031 /* keep hold of the byte we've got already */ 1032 goto out_no_data; 1033 } 1034 /* Event 46: nAutoFd (HostAck) goes low to accept more data */ 1035 parport_pc_frob_control (port, 1036 PARPORT_CONTROL_AUTOFD, 1037 PARPORT_CONTROL_AUTOFD); 1038 1039 1040 dump_parport_state ("rev idle", port); 1041 /* Do the transfer. */ 1042 while (left > fifofull) { 1043 int ret; 1044 unsigned long expire = jiffies + port->cad->timeout; 1045 unsigned char ecrval = inb (ECONTROL (port)); 1046 1047 if (need_resched() && time_before (jiffies, expire)) 1048 /* Can't yield the port. */ 1049 schedule (); 1050 1051 /* At this point, the FIFO may already be full. In 1052 * that case ECP is already holding back the 1053 * peripheral (assuming proper design) with a delayed 1054 * handshake. Work fast to avoid a peripheral 1055 * timeout. */ 1056 1057 if (ecrval & 0x01) { 1058 /* FIFO is empty. Wait for interrupt. */ 1059 dump_parport_state ("FIFO empty", port); 1060 1061 /* Anyone else waiting for the port? */ 1062 if (port->waithead) { 1063 printk (KERN_DEBUG "Somebody wants the port\n"); 1064 break; 1065 } 1066 1067 /* Clear serviceIntr */ 1068 ECR_WRITE (port, ecrval & ~(1<<2)); 1069 false_alarm: 1070 dump_parport_state ("waiting", port); 1071 ret = parport_wait_event (port, HZ); 1072 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret); 1073 if (ret < 0) 1074 break; 1075 ret = 0; 1076 if (!time_before (jiffies, expire)) { 1077 /* Timed out. */ 1078 dump_parport_state ("timeout", port); 1079 printk (KERN_DEBUG "PIO read timed out\n"); 1080 break; 1081 } 1082 ecrval = inb (ECONTROL (port)); 1083 if (!(ecrval & (1<<2))) { 1084 if (need_resched() && 1085 time_before (jiffies, expire)) { 1086 schedule (); 1087 } 1088 goto false_alarm; 1089 } 1090 1091 /* Depending on how the FIFO threshold was 1092 * set, how long interrupt service took, and 1093 * how fast the peripheral is, we might be 1094 * lucky and have a just filled FIFO. */ 1095 continue; 1096 } 1097 1098 if (ecrval & 0x02) { 1099 /* FIFO is full. */ 1100 dump_parport_state ("FIFO full", port); 1101 insb (fifo, bufp, fifo_depth); 1102 bufp += fifo_depth; 1103 left -= fifo_depth; 1104 continue; 1105 } 1106 1107 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n"); 1108 1109 /* FIFO not filled. We will cycle this loop for a while 1110 * and either the peripheral will fill it faster, 1111 * tripping a fast empty with insb, or we empty it. */ 1112 *bufp++ = inb (fifo); 1113 left--; 1114 } 1115 1116 /* scoop up anything left in the FIFO */ 1117 while (left && !(inb (ECONTROL (port) & 0x01))) { 1118 *bufp++ = inb (fifo); 1119 left--; 1120 } 1121 1122 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; 1123 dump_parport_state ("rev idle2", port); 1124 1125 out_no_data: 1126 1127 /* Go to forward idle mode to shut the peripheral up (event 47). */ 1128 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); 1129 1130 /* event 49: PError goes high */ 1131 r = parport_wait_peripheral (port, 1132 PARPORT_STATUS_PAPEROUT, 1133 PARPORT_STATUS_PAPEROUT); 1134 if (r) { 1135 printk (KERN_DEBUG 1136 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n", 1137 port->name, r); 1138 } 1139 1140 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1141 1142 /* Finish up. */ 1143 { 1144 int lost = get_fifo_residue (port); 1145 if (lost) 1146 /* Shouldn't happen with compliant peripherals. */ 1147 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n", 1148 port->name, lost); 1149 } 1150 1151 dump_parport_state ("fwd idle", port); 1152 return length - left; 1153 } 1154 #endif /* 0 */ 1155 #endif /* IEEE 1284 support */ 1156 #endif /* Allowed to use FIFO/DMA */ 1157 1158 1159 /* 1160 * ****************************************** 1161 * INITIALISATION AND MODULE STUFF BELOW HERE 1162 * ****************************************** 1163 */ 1164 1165 /* GCC is not inlining extern inline function later overwriten to non-inline, 1166 so we use outlined_ variants here. */ 1167 static const struct parport_operations parport_pc_ops = 1168 { 1169 .write_data = parport_pc_write_data, 1170 .read_data = parport_pc_read_data, 1171 1172 .write_control = parport_pc_write_control, 1173 .read_control = parport_pc_read_control, 1174 .frob_control = parport_pc_frob_control, 1175 1176 .read_status = parport_pc_read_status, 1177 1178 .enable_irq = parport_pc_enable_irq, 1179 .disable_irq = parport_pc_disable_irq, 1180 1181 .data_forward = parport_pc_data_forward, 1182 .data_reverse = parport_pc_data_reverse, 1183 1184 .init_state = parport_pc_init_state, 1185 .save_state = parport_pc_save_state, 1186 .restore_state = parport_pc_restore_state, 1187 1188 .epp_write_data = parport_ieee1284_epp_write_data, 1189 .epp_read_data = parport_ieee1284_epp_read_data, 1190 .epp_write_addr = parport_ieee1284_epp_write_addr, 1191 .epp_read_addr = parport_ieee1284_epp_read_addr, 1192 1193 .ecp_write_data = parport_ieee1284_ecp_write_data, 1194 .ecp_read_data = parport_ieee1284_ecp_read_data, 1195 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1196 1197 .compat_write_data = parport_ieee1284_write_compat, 1198 .nibble_read_data = parport_ieee1284_read_nibble, 1199 .byte_read_data = parport_ieee1284_read_byte, 1200 1201 .owner = THIS_MODULE, 1202 }; 1203 1204 #ifdef CONFIG_PARPORT_PC_SUPERIO 1205 /* Super-IO chipset detection, Winbond, SMSC */ 1206 static void __devinit show_parconfig_smsc37c669(int io, int key) 1207 { 1208 int cr1,cr4,cra,cr23,cr26,cr27,i=0; 1209 static const char *const modes[]={ 1210 "SPP and Bidirectional (PS/2)", 1211 "EPP and SPP", 1212 "ECP", 1213 "ECP and EPP" }; 1214 1215 outb(key,io); 1216 outb(key,io); 1217 outb(1,io); 1218 cr1=inb(io+1); 1219 outb(4,io); 1220 cr4=inb(io+1); 1221 outb(0x0a,io); 1222 cra=inb(io+1); 1223 outb(0x23,io); 1224 cr23=inb(io+1); 1225 outb(0x26,io); 1226 cr26=inb(io+1); 1227 outb(0x27,io); 1228 cr27=inb(io+1); 1229 outb(0xaa,io); 1230 1231 if (verbose_probing) { 1232 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " 1233 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", 1234 cr1,cr4,cra,cr23,cr26,cr27); 1235 1236 /* The documentation calls DMA and IRQ-Lines by letters, so 1237 the board maker can/will wire them 1238 appropriately/randomly... G=reserved H=IDE-irq, */ 1239 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, " 1240 "fifo threshold=%d\n", cr23*4, 1241 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-', 1242 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f); 1243 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", 1244 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no"); 1245 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n", 1246 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03], 1247 (cr4 & 0x40) ? "1.7" : "1.9"); 1248 } 1249 1250 /* Heuristics ! BIOS setup for this mainboard device limits 1251 the choices to standard settings, i.e. io-address and IRQ 1252 are related, however DMA can be 1 or 3, assume DMA_A=DMA1, 1253 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ 1254 if(cr23*4 >=0x100) { /* if active */ 1255 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1256 i++; 1257 if(i==NR_SUPERIOS) 1258 printk(KERN_INFO "Super-IO: too many chips!\n"); 1259 else { 1260 int d; 1261 switch (cr23*4) { 1262 case 0x3bc: 1263 superios[i].io = 0x3bc; 1264 superios[i].irq = 7; 1265 break; 1266 case 0x378: 1267 superios[i].io = 0x378; 1268 superios[i].irq = 7; 1269 break; 1270 case 0x278: 1271 superios[i].io = 0x278; 1272 superios[i].irq = 5; 1273 } 1274 d=(cr26 &0x0f); 1275 if((d==1) || (d==3)) 1276 superios[i].dma= d; 1277 else 1278 superios[i].dma= PARPORT_DMA_NONE; 1279 } 1280 } 1281 } 1282 1283 1284 static void __devinit show_parconfig_winbond(int io, int key) 1285 { 1286 int cr30,cr60,cr61,cr70,cr74,crf0,i=0; 1287 static const char *const modes[] = { 1288 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ 1289 "EPP-1.9 and SPP", 1290 "ECP", 1291 "ECP and EPP-1.9", 1292 "Standard (SPP)", 1293 "EPP-1.7 and SPP", /* 5 */ 1294 "undefined!", 1295 "ECP and EPP-1.7" }; 1296 static char *const irqtypes[] = { 1297 "pulsed low, high-Z", 1298 "follows nACK" }; 1299 1300 /* The registers are called compatible-PnP because the 1301 register layout is modelled after ISA-PnP, the access 1302 method is just another ... */ 1303 outb(key,io); 1304 outb(key,io); 1305 outb(0x07,io); /* Register 7: Select Logical Device */ 1306 outb(0x01,io+1); /* LD1 is Parallel Port */ 1307 outb(0x30,io); 1308 cr30=inb(io+1); 1309 outb(0x60,io); 1310 cr60=inb(io+1); 1311 outb(0x61,io); 1312 cr61=inb(io+1); 1313 outb(0x70,io); 1314 cr70=inb(io+1); 1315 outb(0x74,io); 1316 cr74=inb(io+1); 1317 outb(0xf0,io); 1318 crf0=inb(io+1); 1319 outb(0xaa,io); 1320 1321 if (verbose_probing) { 1322 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x " 1323 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0); 1324 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", 1325 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f ); 1326 if ((cr74 & 0x07) > 3) 1327 printk("dma=none\n"); 1328 else 1329 printk("dma=%d\n",cr74 & 0x07); 1330 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", 1331 irqtypes[crf0>>7], (crf0>>3)&0x0f); 1332 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]); 1333 } 1334 1335 if(cr30 & 0x01) { /* the settings can be interrogated later ... */ 1336 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1337 i++; 1338 if(i==NR_SUPERIOS) 1339 printk(KERN_INFO "Super-IO: too many chips!\n"); 1340 else { 1341 superios[i].io = (cr60<<8)|cr61; 1342 superios[i].irq = cr70&0x0f; 1343 superios[i].dma = (((cr74 & 0x07) > 3) ? 1344 PARPORT_DMA_NONE : (cr74 & 0x07)); 1345 } 1346 } 1347 } 1348 1349 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid) 1350 { 1351 const char *type = "unknown"; 1352 int id,progif=2; 1353 1354 if (devid == devrev) 1355 /* simple heuristics, we happened to read some 1356 non-winbond register */ 1357 return; 1358 1359 id=(devid<<8) | devrev; 1360 1361 /* Values are from public data sheets pdf files, I can just 1362 confirm 83977TF is correct :-) */ 1363 if (id == 0x9771) type="83977F/AF"; 1364 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x"; 1365 else if (id == 0x9774) type="83977ATF"; 1366 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x"; 1367 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x"; 1368 else if ((id & ~0x0f) == 0x5210) type="83627"; 1369 else if ((id & ~0x0f) == 0x6010) type="83697HF"; 1370 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;} 1371 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;} 1372 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;} 1373 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;} 1374 else progif=0; 1375 1376 if (verbose_probing) 1377 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " 1378 "devid=%02x devrev=%02x oldid=%02x type=%s\n", 1379 efer, key, devid, devrev, oldid, type); 1380 1381 if (progif == 2) 1382 show_parconfig_winbond(efer,key); 1383 } 1384 1385 static void __devinit decode_smsc(int efer, int key, int devid, int devrev) 1386 { 1387 const char *type = "unknown"; 1388 void (*func)(int io, int key); 1389 int id; 1390 1391 if (devid == devrev) 1392 /* simple heuristics, we happened to read some 1393 non-smsc register */ 1394 return; 1395 1396 func=NULL; 1397 id=(devid<<8) | devrev; 1398 1399 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;} 1400 else if (id==0x6582) type="37c665IR"; 1401 else if (devid==0x65) type="37c665GT"; 1402 else if (devid==0x66) type="37c666GT"; 1403 1404 if (verbose_probing) 1405 printk(KERN_INFO "SMSC chip at EFER=0x%x " 1406 "key=0x%02x devid=%02x devrev=%02x type=%s\n", 1407 efer, key, devid, devrev, type); 1408 1409 if (func) 1410 func(efer,key); 1411 } 1412 1413 1414 static void __devinit winbond_check(int io, int key) 1415 { 1416 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1417 1418 if (!request_region(io, 3, __func__)) 1419 return; 1420 1421 /* First probe without key */ 1422 outb(0x20,io); 1423 x_devid=inb(io+1); 1424 outb(0x21,io); 1425 x_devrev=inb(io+1); 1426 outb(0x09,io); 1427 x_oldid=inb(io+1); 1428 1429 outb(key,io); 1430 outb(key,io); /* Write Magic Sequence to EFER, extended 1431 funtion enable register */ 1432 outb(0x20,io); /* Write EFIR, extended function index register */ 1433 devid=inb(io+1); /* Read EFDR, extended function data register */ 1434 outb(0x21,io); 1435 devrev=inb(io+1); 1436 outb(0x09,io); 1437 oldid=inb(io+1); 1438 outb(0xaa,io); /* Magic Seal */ 1439 1440 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1441 goto out; /* protection against false positives */ 1442 1443 decode_winbond(io,key,devid,devrev,oldid); 1444 out: 1445 release_region(io, 3); 1446 } 1447 1448 static void __devinit winbond_check2(int io,int key) 1449 { 1450 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1451 1452 if (!request_region(io, 3, __func__)) 1453 return; 1454 1455 /* First probe without the key */ 1456 outb(0x20,io+2); 1457 x_devid=inb(io+2); 1458 outb(0x21,io+1); 1459 x_devrev=inb(io+2); 1460 outb(0x09,io+1); 1461 x_oldid=inb(io+2); 1462 1463 outb(key,io); /* Write Magic Byte to EFER, extended 1464 funtion enable register */ 1465 outb(0x20,io+2); /* Write EFIR, extended function index register */ 1466 devid=inb(io+2); /* Read EFDR, extended function data register */ 1467 outb(0x21,io+1); 1468 devrev=inb(io+2); 1469 outb(0x09,io+1); 1470 oldid=inb(io+2); 1471 outb(0xaa,io); /* Magic Seal */ 1472 1473 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1474 goto out; /* protection against false positives */ 1475 1476 decode_winbond(io,key,devid,devrev,oldid); 1477 out: 1478 release_region(io, 3); 1479 } 1480 1481 static void __devinit smsc_check(int io, int key) 1482 { 1483 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev; 1484 1485 if (!request_region(io, 3, __func__)) 1486 return; 1487 1488 /* First probe without the key */ 1489 outb(0x0d,io); 1490 x_oldid=inb(io+1); 1491 outb(0x0e,io); 1492 x_oldrev=inb(io+1); 1493 outb(0x20,io); 1494 x_id=inb(io+1); 1495 outb(0x21,io); 1496 x_rev=inb(io+1); 1497 1498 outb(key,io); 1499 outb(key,io); /* Write Magic Sequence to EFER, extended 1500 funtion enable register */ 1501 outb(0x0d,io); /* Write EFIR, extended function index register */ 1502 oldid=inb(io+1); /* Read EFDR, extended function data register */ 1503 outb(0x0e,io); 1504 oldrev=inb(io+1); 1505 outb(0x20,io); 1506 id=inb(io+1); 1507 outb(0x21,io); 1508 rev=inb(io+1); 1509 outb(0xaa,io); /* Magic Seal */ 1510 1511 if ((x_id == id) && (x_oldrev == oldrev) && 1512 (x_oldid == oldid) && (x_rev == rev)) 1513 goto out; /* protection against false positives */ 1514 1515 decode_smsc(io,key,oldid,oldrev); 1516 out: 1517 release_region(io, 3); 1518 } 1519 1520 1521 static void __devinit detect_and_report_winbond (void) 1522 { 1523 if (verbose_probing) 1524 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); 1525 winbond_check(0x3f0,0x87); 1526 winbond_check(0x370,0x87); 1527 winbond_check(0x2e ,0x87); 1528 winbond_check(0x4e ,0x87); 1529 winbond_check(0x3f0,0x86); 1530 winbond_check2(0x250,0x88); 1531 winbond_check2(0x250,0x89); 1532 } 1533 1534 static void __devinit detect_and_report_smsc (void) 1535 { 1536 if (verbose_probing) 1537 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); 1538 smsc_check(0x3f0,0x55); 1539 smsc_check(0x370,0x55); 1540 smsc_check(0x3f0,0x44); 1541 smsc_check(0x370,0x44); 1542 } 1543 1544 static void __devinit detect_and_report_it87(void) 1545 { 1546 u16 dev; 1547 u8 r; 1548 if (verbose_probing) 1549 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n"); 1550 if (!request_region(0x2e, 1, __func__)) 1551 return; 1552 outb(0x87, 0x2e); 1553 outb(0x01, 0x2e); 1554 outb(0x55, 0x2e); 1555 outb(0x55, 0x2e); 1556 outb(0x20, 0x2e); 1557 dev = inb(0x2f) << 8; 1558 outb(0x21, 0x2e); 1559 dev |= inb(0x2f); 1560 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || 1561 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { 1562 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev); 1563 outb(0x07, 0x2E); /* Parallel Port */ 1564 outb(0x03, 0x2F); 1565 outb(0xF0, 0x2E); /* BOOT 0x80 off */ 1566 r = inb(0x2f); 1567 outb(0xF0, 0x2E); 1568 outb(r | 8, 0x2F); 1569 outb(0x02, 0x2E); /* Lock */ 1570 outb(0x02, 0x2F); 1571 } 1572 release_region(0x2e, 1); 1573 } 1574 #endif /* CONFIG_PARPORT_PC_SUPERIO */ 1575 1576 static int get_superio_dma (struct parport *p) 1577 { 1578 int i=0; 1579 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1580 i++; 1581 if (i!=NR_SUPERIOS) 1582 return superios[i].dma; 1583 return PARPORT_DMA_NONE; 1584 } 1585 1586 static int get_superio_irq (struct parport *p) 1587 { 1588 int i=0; 1589 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1590 i++; 1591 if (i!=NR_SUPERIOS) 1592 return superios[i].irq; 1593 return PARPORT_IRQ_NONE; 1594 } 1595 1596 1597 /* --- Mode detection ------------------------------------- */ 1598 1599 /* 1600 * Checks for port existence, all ports support SPP MODE 1601 * Returns: 1602 * 0 : No parallel port at this address 1603 * PARPORT_MODE_PCSPP : SPP port detected 1604 * (if the user specified an ioport himself, 1605 * this shall always be the case!) 1606 * 1607 */ 1608 static int parport_SPP_supported(struct parport *pb) 1609 { 1610 unsigned char r, w; 1611 1612 /* 1613 * first clear an eventually pending EPP timeout 1614 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset 1615 * that does not even respond to SPP cycles if an EPP 1616 * timeout is pending 1617 */ 1618 clear_epp_timeout(pb); 1619 1620 /* Do a simple read-write test to make sure the port exists. */ 1621 w = 0xc; 1622 outb (w, CONTROL (pb)); 1623 1624 /* Is there a control register that we can read from? Some 1625 * ports don't allow reads, so read_control just returns a 1626 * software copy. Some ports _do_ allow reads, so bypass the 1627 * software copy here. In addition, some bits aren't 1628 * writable. */ 1629 r = inb (CONTROL (pb)); 1630 if ((r & 0xf) == w) { 1631 w = 0xe; 1632 outb (w, CONTROL (pb)); 1633 r = inb (CONTROL (pb)); 1634 outb (0xc, CONTROL (pb)); 1635 if ((r & 0xf) == w) 1636 return PARPORT_MODE_PCSPP; 1637 } 1638 1639 if (user_specified) 1640 /* That didn't work, but the user thinks there's a 1641 * port here. */ 1642 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: " 1643 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1644 1645 /* Try the data register. The data lines aren't tri-stated at 1646 * this stage, so we expect back what we wrote. */ 1647 w = 0xaa; 1648 parport_pc_write_data (pb, w); 1649 r = parport_pc_read_data (pb); 1650 if (r == w) { 1651 w = 0x55; 1652 parport_pc_write_data (pb, w); 1653 r = parport_pc_read_data (pb); 1654 if (r == w) 1655 return PARPORT_MODE_PCSPP; 1656 } 1657 1658 if (user_specified) { 1659 /* Didn't work, but the user is convinced this is the 1660 * place. */ 1661 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: " 1662 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1663 printk (KERN_INFO "parport 0x%lx: You gave this address, " 1664 "but there is probably no parallel port there!\n", 1665 pb->base); 1666 } 1667 1668 /* It's possible that we can't read the control register or 1669 * the data register. In that case just believe the user. */ 1670 if (user_specified) 1671 return PARPORT_MODE_PCSPP; 1672 1673 return 0; 1674 } 1675 1676 /* Check for ECR 1677 * 1678 * Old style XT ports alias io ports every 0x400, hence accessing ECR 1679 * on these cards actually accesses the CTR. 1680 * 1681 * Modern cards don't do this but reading from ECR will return 0xff 1682 * regardless of what is written here if the card does NOT support 1683 * ECP. 1684 * 1685 * We first check to see if ECR is the same as CTR. If not, the low 1686 * two bits of ECR aren't writable, so we check by writing ECR and 1687 * reading it back to see if it's what we expect. 1688 */ 1689 static int parport_ECR_present(struct parport *pb) 1690 { 1691 struct parport_pc_private *priv = pb->private_data; 1692 unsigned char r = 0xc; 1693 1694 outb (r, CONTROL (pb)); 1695 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) { 1696 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */ 1697 1698 r = inb (CONTROL (pb)); 1699 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2)) 1700 goto no_reg; /* Sure that no ECR register exists */ 1701 } 1702 1703 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1) 1704 goto no_reg; 1705 1706 ECR_WRITE (pb, 0x34); 1707 if (inb (ECONTROL (pb)) != 0x35) 1708 goto no_reg; 1709 1710 priv->ecr = 1; 1711 outb (0xc, CONTROL (pb)); 1712 1713 /* Go to mode 000 */ 1714 frob_set_mode (pb, ECR_SPP); 1715 1716 return 1; 1717 1718 no_reg: 1719 outb (0xc, CONTROL (pb)); 1720 return 0; 1721 } 1722 1723 #ifdef CONFIG_PARPORT_1284 1724 /* Detect PS/2 support. 1725 * 1726 * Bit 5 (0x20) sets the PS/2 data direction; setting this high 1727 * allows us to read data from the data lines. In theory we would get back 1728 * 0xff but any peripheral attached to the port may drag some or all of the 1729 * lines down to zero. So if we get back anything that isn't the contents 1730 * of the data register we deem PS/2 support to be present. 1731 * 1732 * Some SPP ports have "half PS/2" ability - you can't turn off the line 1733 * drivers, but an external peripheral with sufficiently beefy drivers of 1734 * its own can overpower them and assert its own levels onto the bus, from 1735 * where they can then be read back as normal. Ports with this property 1736 * and the right type of device attached are likely to fail the SPP test, 1737 * (as they will appear to have stuck bits) and so the fact that they might 1738 * be misdetected here is rather academic. 1739 */ 1740 1741 static int parport_PS2_supported(struct parport *pb) 1742 { 1743 int ok = 0; 1744 1745 clear_epp_timeout(pb); 1746 1747 /* try to tri-state the buffer */ 1748 parport_pc_data_reverse (pb); 1749 1750 parport_pc_write_data(pb, 0x55); 1751 if (parport_pc_read_data(pb) != 0x55) ok++; 1752 1753 parport_pc_write_data(pb, 0xaa); 1754 if (parport_pc_read_data(pb) != 0xaa) ok++; 1755 1756 /* cancel input mode */ 1757 parport_pc_data_forward (pb); 1758 1759 if (ok) { 1760 pb->modes |= PARPORT_MODE_TRISTATE; 1761 } else { 1762 struct parport_pc_private *priv = pb->private_data; 1763 priv->ctr_writable &= ~0x20; 1764 } 1765 1766 return ok; 1767 } 1768 1769 #ifdef CONFIG_PARPORT_PC_FIFO 1770 static int parport_ECP_supported(struct parport *pb) 1771 { 1772 int i; 1773 int config, configb; 1774 int pword; 1775 struct parport_pc_private *priv = pb->private_data; 1776 /* Translate ECP intrLine to ISA irq value */ 1777 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 }; 1778 1779 /* If there is no ECR, we have no hope of supporting ECP. */ 1780 if (!priv->ecr) 1781 return 0; 1782 1783 /* Find out FIFO depth */ 1784 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1785 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */ 1786 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++) 1787 outb (0xaa, FIFO (pb)); 1788 1789 /* 1790 * Using LGS chipset it uses ECR register, but 1791 * it doesn't support ECP or FIFO MODE 1792 */ 1793 if (i == 1024) { 1794 ECR_WRITE (pb, ECR_SPP << 5); 1795 return 0; 1796 } 1797 1798 priv->fifo_depth = i; 1799 if (verbose_probing) 1800 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); 1801 1802 /* Find out writeIntrThreshold */ 1803 frob_econtrol (pb, 1<<2, 1<<2); 1804 frob_econtrol (pb, 1<<2, 0); 1805 for (i = 1; i <= priv->fifo_depth; i++) { 1806 inb (FIFO (pb)); 1807 udelay (50); 1808 if (inb (ECONTROL (pb)) & (1<<2)) 1809 break; 1810 } 1811 1812 if (i <= priv->fifo_depth) { 1813 if (verbose_probing) 1814 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", 1815 pb->base, i); 1816 } else 1817 /* Number of bytes we know we can write if we get an 1818 interrupt. */ 1819 i = 0; 1820 1821 priv->writeIntrThreshold = i; 1822 1823 /* Find out readIntrThreshold */ 1824 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */ 1825 parport_pc_data_reverse (pb); /* Must be in PS2 mode */ 1826 frob_set_mode (pb, ECR_TST); /* Test FIFO */ 1827 frob_econtrol (pb, 1<<2, 1<<2); 1828 frob_econtrol (pb, 1<<2, 0); 1829 for (i = 1; i <= priv->fifo_depth; i++) { 1830 outb (0xaa, FIFO (pb)); 1831 if (inb (ECONTROL (pb)) & (1<<2)) 1832 break; 1833 } 1834 1835 if (i <= priv->fifo_depth) { 1836 if (verbose_probing) 1837 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n", 1838 pb->base, i); 1839 } else 1840 /* Number of bytes we can read if we get an interrupt. */ 1841 i = 0; 1842 1843 priv->readIntrThreshold = i; 1844 1845 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1846 ECR_WRITE (pb, 0xf4); /* Configuration mode */ 1847 config = inb (CONFIGA (pb)); 1848 pword = (config >> 4) & 0x7; 1849 switch (pword) { 1850 case 0: 1851 pword = 2; 1852 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1853 pb->base); 1854 break; 1855 case 2: 1856 pword = 4; 1857 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1858 pb->base); 1859 break; 1860 default: 1861 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n", 1862 pb->base); 1863 /* Assume 1 */ 1864 case 1: 1865 pword = 1; 1866 } 1867 priv->pword = pword; 1868 1869 if (verbose_probing) { 1870 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword); 1871 1872 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, 1873 config & 0x80 ? "Level" : "Pulses"); 1874 1875 configb = inb (CONFIGB (pb)); 1876 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", 1877 pb->base, config, configb); 1878 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); 1879 if ((configb >>3) & 0x07) 1880 printk("%d",intrline[(configb >>3) & 0x07]); 1881 else 1882 printk("<none or set by other means>"); 1883 printk (" dma="); 1884 if( (configb & 0x03 ) == 0x00) 1885 printk("<none or set by other means>\n"); 1886 else 1887 printk("%d\n",configb & 0x07); 1888 } 1889 1890 /* Go back to mode 000 */ 1891 frob_set_mode (pb, ECR_SPP); 1892 1893 return 1; 1894 } 1895 #endif 1896 1897 static int parport_ECPPS2_supported(struct parport *pb) 1898 { 1899 const struct parport_pc_private *priv = pb->private_data; 1900 int result; 1901 unsigned char oecr; 1902 1903 if (!priv->ecr) 1904 return 0; 1905 1906 oecr = inb (ECONTROL (pb)); 1907 ECR_WRITE (pb, ECR_PS2 << 5); 1908 result = parport_PS2_supported(pb); 1909 ECR_WRITE (pb, oecr); 1910 return result; 1911 } 1912 1913 /* EPP mode detection */ 1914 1915 static int parport_EPP_supported(struct parport *pb) 1916 { 1917 const struct parport_pc_private *priv = pb->private_data; 1918 1919 /* 1920 * Theory: 1921 * Bit 0 of STR is the EPP timeout bit, this bit is 0 1922 * when EPP is possible and is set high when an EPP timeout 1923 * occurs (EPP uses the HALT line to stop the CPU while it does 1924 * the byte transfer, an EPP timeout occurs if the attached 1925 * device fails to respond after 10 micro seconds). 1926 * 1927 * This bit is cleared by either reading it (National Semi) 1928 * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? 1929 * This bit is always high in non EPP modes. 1930 */ 1931 1932 /* If EPP timeout bit clear then EPP available */ 1933 if (!clear_epp_timeout(pb)) { 1934 return 0; /* No way to clear timeout */ 1935 } 1936 1937 /* Check for Intel bug. */ 1938 if (priv->ecr) { 1939 unsigned char i; 1940 for (i = 0x00; i < 0x80; i += 0x20) { 1941 ECR_WRITE (pb, i); 1942 if (clear_epp_timeout (pb)) { 1943 /* Phony EPP in ECP. */ 1944 return 0; 1945 } 1946 } 1947 } 1948 1949 pb->modes |= PARPORT_MODE_EPP; 1950 1951 /* Set up access functions to use EPP hardware. */ 1952 pb->ops->epp_read_data = parport_pc_epp_read_data; 1953 pb->ops->epp_write_data = parport_pc_epp_write_data; 1954 pb->ops->epp_read_addr = parport_pc_epp_read_addr; 1955 pb->ops->epp_write_addr = parport_pc_epp_write_addr; 1956 1957 return 1; 1958 } 1959 1960 static int parport_ECPEPP_supported(struct parport *pb) 1961 { 1962 struct parport_pc_private *priv = pb->private_data; 1963 int result; 1964 unsigned char oecr; 1965 1966 if (!priv->ecr) { 1967 return 0; 1968 } 1969 1970 oecr = inb (ECONTROL (pb)); 1971 /* Search for SMC style EPP+ECP mode */ 1972 ECR_WRITE (pb, 0x80); 1973 outb (0x04, CONTROL (pb)); 1974 result = parport_EPP_supported(pb); 1975 1976 ECR_WRITE (pb, oecr); 1977 1978 if (result) { 1979 /* Set up access functions to use ECP+EPP hardware. */ 1980 pb->ops->epp_read_data = parport_pc_ecpepp_read_data; 1981 pb->ops->epp_write_data = parport_pc_ecpepp_write_data; 1982 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; 1983 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; 1984 } 1985 1986 return result; 1987 } 1988 1989 #else /* No IEEE 1284 support */ 1990 1991 /* Don't bother probing for modes we know we won't use. */ 1992 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; } 1993 #ifdef CONFIG_PARPORT_PC_FIFO 1994 static int parport_ECP_supported(struct parport *pb) { return 0; } 1995 #endif 1996 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; } 1997 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;} 1998 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;} 1999 2000 #endif /* No IEEE 1284 support */ 2001 2002 /* --- IRQ detection -------------------------------------- */ 2003 2004 /* Only if supports ECP mode */ 2005 static int programmable_irq_support(struct parport *pb) 2006 { 2007 int irq, intrLine; 2008 unsigned char oecr = inb (ECONTROL (pb)); 2009 static const int lookup[8] = { 2010 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 2011 }; 2012 2013 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */ 2014 2015 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07; 2016 irq = lookup[intrLine]; 2017 2018 ECR_WRITE (pb, oecr); 2019 return irq; 2020 } 2021 2022 static int irq_probe_ECP(struct parport *pb) 2023 { 2024 int i; 2025 unsigned long irqs; 2026 2027 irqs = probe_irq_on(); 2028 2029 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 2030 ECR_WRITE (pb, (ECR_TST << 5) | 0x04); 2031 ECR_WRITE (pb, ECR_TST << 5); 2032 2033 /* If Full FIFO sure that writeIntrThreshold is generated */ 2034 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++) 2035 outb (0xaa, FIFO (pb)); 2036 2037 pb->irq = probe_irq_off(irqs); 2038 ECR_WRITE (pb, ECR_SPP << 5); 2039 2040 if (pb->irq <= 0) 2041 pb->irq = PARPORT_IRQ_NONE; 2042 2043 return pb->irq; 2044 } 2045 2046 /* 2047 * This detection seems that only works in National Semiconductors 2048 * This doesn't work in SMC, LGS, and Winbond 2049 */ 2050 static int irq_probe_EPP(struct parport *pb) 2051 { 2052 #ifndef ADVANCED_DETECT 2053 return PARPORT_IRQ_NONE; 2054 #else 2055 int irqs; 2056 unsigned char oecr; 2057 2058 if (pb->modes & PARPORT_MODE_PCECR) 2059 oecr = inb (ECONTROL (pb)); 2060 2061 irqs = probe_irq_on(); 2062 2063 if (pb->modes & PARPORT_MODE_PCECR) 2064 frob_econtrol (pb, 0x10, 0x10); 2065 2066 clear_epp_timeout(pb); 2067 parport_pc_frob_control (pb, 0x20, 0x20); 2068 parport_pc_frob_control (pb, 0x10, 0x10); 2069 clear_epp_timeout(pb); 2070 2071 /* Device isn't expecting an EPP read 2072 * and generates an IRQ. 2073 */ 2074 parport_pc_read_epp(pb); 2075 udelay(20); 2076 2077 pb->irq = probe_irq_off (irqs); 2078 if (pb->modes & PARPORT_MODE_PCECR) 2079 ECR_WRITE (pb, oecr); 2080 parport_pc_write_control(pb, 0xc); 2081 2082 if (pb->irq <= 0) 2083 pb->irq = PARPORT_IRQ_NONE; 2084 2085 return pb->irq; 2086 #endif /* Advanced detection */ 2087 } 2088 2089 static int irq_probe_SPP(struct parport *pb) 2090 { 2091 /* Don't even try to do this. */ 2092 return PARPORT_IRQ_NONE; 2093 } 2094 2095 /* We will attempt to share interrupt requests since other devices 2096 * such as sound cards and network cards seem to like using the 2097 * printer IRQs. 2098 * 2099 * When ECP is available we can autoprobe for IRQs. 2100 * NOTE: If we can autoprobe it, we can register the IRQ. 2101 */ 2102 static int parport_irq_probe(struct parport *pb) 2103 { 2104 struct parport_pc_private *priv = pb->private_data; 2105 2106 if (priv->ecr) { 2107 pb->irq = programmable_irq_support(pb); 2108 2109 if (pb->irq == PARPORT_IRQ_NONE) 2110 pb->irq = irq_probe_ECP(pb); 2111 } 2112 2113 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && 2114 (pb->modes & PARPORT_MODE_EPP)) 2115 pb->irq = irq_probe_EPP(pb); 2116 2117 clear_epp_timeout(pb); 2118 2119 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) 2120 pb->irq = irq_probe_EPP(pb); 2121 2122 clear_epp_timeout(pb); 2123 2124 if (pb->irq == PARPORT_IRQ_NONE) 2125 pb->irq = irq_probe_SPP(pb); 2126 2127 if (pb->irq == PARPORT_IRQ_NONE) 2128 pb->irq = get_superio_irq(pb); 2129 2130 return pb->irq; 2131 } 2132 2133 /* --- DMA detection -------------------------------------- */ 2134 2135 /* Only if chipset conforms to ECP ISA Interface Standard */ 2136 static int programmable_dma_support (struct parport *p) 2137 { 2138 unsigned char oecr = inb (ECONTROL (p)); 2139 int dma; 2140 2141 frob_set_mode (p, ECR_CNF); 2142 2143 dma = inb (CONFIGB(p)) & 0x07; 2144 /* 000: Indicates jumpered 8-bit DMA if read-only. 2145 100: Indicates jumpered 16-bit DMA if read-only. */ 2146 if ((dma & 0x03) == 0) 2147 dma = PARPORT_DMA_NONE; 2148 2149 ECR_WRITE (p, oecr); 2150 return dma; 2151 } 2152 2153 static int parport_dma_probe (struct parport *p) 2154 { 2155 const struct parport_pc_private *priv = p->private_data; 2156 if (priv->ecr) 2157 p->dma = programmable_dma_support(p); /* ask ECP chipset first */ 2158 if (p->dma == PARPORT_DMA_NONE) { 2159 /* ask known Super-IO chips proper, although these 2160 claim ECP compatible, some don't report their DMA 2161 conforming to ECP standards */ 2162 p->dma = get_superio_dma(p); 2163 } 2164 2165 return p->dma; 2166 } 2167 2168 /* --- Initialisation code -------------------------------- */ 2169 2170 static LIST_HEAD(ports_list); 2171 static DEFINE_SPINLOCK(ports_lock); 2172 2173 struct parport *parport_pc_probe_port(unsigned long int base, 2174 unsigned long int base_hi, 2175 int irq, int dma, 2176 struct device *dev, 2177 int irqflags) 2178 { 2179 struct parport_pc_private *priv; 2180 struct parport_operations *ops; 2181 struct parport *p; 2182 int probedirq = PARPORT_IRQ_NONE; 2183 struct resource *base_res; 2184 struct resource *ECR_res = NULL; 2185 struct resource *EPP_res = NULL; 2186 struct platform_device *pdev = NULL; 2187 2188 if (!dev) { 2189 /* We need a physical device to attach to, but none was 2190 * provided. Create our own. */ 2191 pdev = platform_device_register_simple("parport_pc", 2192 base, NULL, 0); 2193 if (IS_ERR(pdev)) 2194 return NULL; 2195 dev = &pdev->dev; 2196 } 2197 2198 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); 2199 if (!ops) 2200 goto out1; 2201 2202 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL); 2203 if (!priv) 2204 goto out2; 2205 2206 /* a misnomer, actually - it's allocate and reserve parport number */ 2207 p = parport_register_port(base, irq, dma, ops); 2208 if (!p) 2209 goto out3; 2210 2211 base_res = request_region(base, 3, p->name); 2212 if (!base_res) 2213 goto out4; 2214 2215 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations)); 2216 priv->ctr = 0xc; 2217 priv->ctr_writable = ~0x10; 2218 priv->ecr = 0; 2219 priv->fifo_depth = 0; 2220 priv->dma_buf = NULL; 2221 priv->dma_handle = 0; 2222 INIT_LIST_HEAD(&priv->list); 2223 priv->port = p; 2224 2225 p->dev = dev; 2226 p->base_hi = base_hi; 2227 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2228 p->private_data = priv; 2229 2230 if (base_hi) { 2231 ECR_res = request_region(base_hi, 3, p->name); 2232 if (ECR_res) 2233 parport_ECR_present(p); 2234 } 2235 2236 if (base != 0x3bc) { 2237 EPP_res = request_region(base+0x3, 5, p->name); 2238 if (EPP_res) 2239 if (!parport_EPP_supported(p)) 2240 parport_ECPEPP_supported(p); 2241 } 2242 if (!parport_SPP_supported (p)) 2243 /* No port. */ 2244 goto out5; 2245 if (priv->ecr) 2246 parport_ECPPS2_supported(p); 2247 else 2248 parport_PS2_supported(p); 2249 2250 p->size = (p->modes & PARPORT_MODE_EPP)?8:3; 2251 2252 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); 2253 if (p->base_hi && priv->ecr) 2254 printk(" (0x%lx)", p->base_hi); 2255 if (p->irq == PARPORT_IRQ_AUTO) { 2256 p->irq = PARPORT_IRQ_NONE; 2257 parport_irq_probe(p); 2258 } else if (p->irq == PARPORT_IRQ_PROBEONLY) { 2259 p->irq = PARPORT_IRQ_NONE; 2260 parport_irq_probe(p); 2261 probedirq = p->irq; 2262 p->irq = PARPORT_IRQ_NONE; 2263 } 2264 if (p->irq != PARPORT_IRQ_NONE) { 2265 printk(", irq %d", p->irq); 2266 priv->ctr_writable |= 0x10; 2267 2268 if (p->dma == PARPORT_DMA_AUTO) { 2269 p->dma = PARPORT_DMA_NONE; 2270 parport_dma_probe(p); 2271 } 2272 } 2273 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq 2274 is mandatory (see above) */ 2275 p->dma = PARPORT_DMA_NONE; 2276 2277 #ifdef CONFIG_PARPORT_PC_FIFO 2278 if (parport_ECP_supported(p) && 2279 p->dma != PARPORT_DMA_NOFIFO && 2280 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { 2281 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; 2282 p->ops->compat_write_data = parport_pc_compat_write_block_pio; 2283 #ifdef CONFIG_PARPORT_1284 2284 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; 2285 /* currently broken, but working on it.. (FB) */ 2286 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ 2287 #endif /* IEEE 1284 support */ 2288 if (p->dma != PARPORT_DMA_NONE) { 2289 printk(", dma %d", p->dma); 2290 p->modes |= PARPORT_MODE_DMA; 2291 } 2292 else printk(", using FIFO"); 2293 } 2294 else 2295 /* We can't use the DMA channel after all. */ 2296 p->dma = PARPORT_DMA_NONE; 2297 #endif /* Allowed to use FIFO/DMA */ 2298 2299 printk(" ["); 2300 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}} 2301 { 2302 int f = 0; 2303 printmode(PCSPP); 2304 printmode(TRISTATE); 2305 printmode(COMPAT) 2306 printmode(EPP); 2307 printmode(ECP); 2308 printmode(DMA); 2309 } 2310 #undef printmode 2311 #ifndef CONFIG_PARPORT_1284 2312 printk ("(,...)"); 2313 #endif /* CONFIG_PARPORT_1284 */ 2314 printk("]\n"); 2315 if (probedirq != PARPORT_IRQ_NONE) 2316 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); 2317 2318 /* If No ECP release the ports grabbed above. */ 2319 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { 2320 release_region(base_hi, 3); 2321 ECR_res = NULL; 2322 } 2323 /* Likewise for EEP ports */ 2324 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { 2325 release_region(base+3, 5); 2326 EPP_res = NULL; 2327 } 2328 if (p->irq != PARPORT_IRQ_NONE) { 2329 if (request_irq(p->irq, parport_irq_handler, 2330 irqflags, p->name, p)) { 2331 printk (KERN_WARNING "%s: irq %d in use, " 2332 "resorting to polled operation\n", 2333 p->name, p->irq); 2334 p->irq = PARPORT_IRQ_NONE; 2335 p->dma = PARPORT_DMA_NONE; 2336 } 2337 2338 #ifdef CONFIG_PARPORT_PC_FIFO 2339 #ifdef HAS_DMA 2340 if (p->dma != PARPORT_DMA_NONE) { 2341 if (request_dma (p->dma, p->name)) { 2342 printk (KERN_WARNING "%s: dma %d in use, " 2343 "resorting to PIO operation\n", 2344 p->name, p->dma); 2345 p->dma = PARPORT_DMA_NONE; 2346 } else { 2347 priv->dma_buf = 2348 dma_alloc_coherent(dev, 2349 PAGE_SIZE, 2350 &priv->dma_handle, 2351 GFP_KERNEL); 2352 if (! priv->dma_buf) { 2353 printk (KERN_WARNING "%s: " 2354 "cannot get buffer for DMA, " 2355 "resorting to PIO operation\n", 2356 p->name); 2357 free_dma(p->dma); 2358 p->dma = PARPORT_DMA_NONE; 2359 } 2360 } 2361 } 2362 #endif 2363 #endif 2364 } 2365 2366 /* Done probing. Now put the port into a sensible start-up state. */ 2367 if (priv->ecr) 2368 /* 2369 * Put the ECP detected port in PS2 mode. 2370 * Do this also for ports that have ECR but don't do ECP. 2371 */ 2372 ECR_WRITE (p, 0x34); 2373 2374 parport_pc_write_data(p, 0); 2375 parport_pc_data_forward (p); 2376 2377 /* Now that we've told the sharing engine about the port, and 2378 found out its characteristics, let the high-level drivers 2379 know about it. */ 2380 spin_lock(&ports_lock); 2381 list_add(&priv->list, &ports_list); 2382 spin_unlock(&ports_lock); 2383 parport_announce_port (p); 2384 2385 return p; 2386 2387 out5: 2388 if (ECR_res) 2389 release_region(base_hi, 3); 2390 if (EPP_res) 2391 release_region(base+0x3, 5); 2392 release_region(base, 3); 2393 out4: 2394 parport_put_port(p); 2395 out3: 2396 kfree (priv); 2397 out2: 2398 kfree (ops); 2399 out1: 2400 if (pdev) 2401 platform_device_unregister(pdev); 2402 return NULL; 2403 } 2404 2405 EXPORT_SYMBOL (parport_pc_probe_port); 2406 2407 void parport_pc_unregister_port (struct parport *p) 2408 { 2409 struct parport_pc_private *priv = p->private_data; 2410 struct parport_operations *ops = p->ops; 2411 2412 parport_remove_port(p); 2413 spin_lock(&ports_lock); 2414 list_del_init(&priv->list); 2415 spin_unlock(&ports_lock); 2416 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2417 if (p->dma != PARPORT_DMA_NONE) 2418 free_dma(p->dma); 2419 #endif 2420 if (p->irq != PARPORT_IRQ_NONE) 2421 free_irq(p->irq, p); 2422 release_region(p->base, 3); 2423 if (p->size > 3) 2424 release_region(p->base + 3, p->size - 3); 2425 if (p->modes & PARPORT_MODE_ECP) 2426 release_region(p->base_hi, 3); 2427 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2428 if (priv->dma_buf) 2429 dma_free_coherent(p->physport->dev, PAGE_SIZE, 2430 priv->dma_buf, 2431 priv->dma_handle); 2432 #endif 2433 kfree (p->private_data); 2434 parport_put_port(p); 2435 kfree (ops); /* hope no-one cached it */ 2436 } 2437 2438 EXPORT_SYMBOL (parport_pc_unregister_port); 2439 2440 #ifdef CONFIG_PCI 2441 2442 /* ITE support maintained by Rich Liu <richliu@poorman.org> */ 2443 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq, 2444 int autodma, 2445 const struct parport_pc_via_data *via) 2446 { 2447 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; 2448 struct resource *base_res; 2449 u32 ite8872set; 2450 u32 ite8872_lpt, ite8872_lpthi; 2451 u8 ite8872_irq, type; 2452 int irq; 2453 int i; 2454 2455 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n"); 2456 2457 // make sure which one chip 2458 for(i = 0; i < 5; i++) { 2459 base_res = request_region(inta_addr[i], 32, "it887x"); 2460 if (base_res) { 2461 int test; 2462 pci_write_config_dword (pdev, 0x60, 2463 0xe5000000 | inta_addr[i]); 2464 pci_write_config_dword (pdev, 0x78, 2465 0x00000000 | inta_addr[i]); 2466 test = inb (inta_addr[i]); 2467 if (test != 0xff) break; 2468 release_region(inta_addr[i], 0x8); 2469 } 2470 } 2471 if(i >= 5) { 2472 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); 2473 return 0; 2474 } 2475 2476 type = inb (inta_addr[i] + 0x18); 2477 type &= 0x0f; 2478 2479 switch (type) { 2480 case 0x2: 2481 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n"); 2482 ite8872set = 0x64200000; 2483 break; 2484 case 0xa: 2485 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n"); 2486 ite8872set = 0x64200000; 2487 break; 2488 case 0xe: 2489 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); 2490 ite8872set = 0x64e00000; 2491 break; 2492 case 0x6: 2493 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n"); 2494 return 0; 2495 case 0x8: 2496 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n"); 2497 return 0; 2498 default: 2499 printk (KERN_INFO "parport_pc: unknown ITE887x\n"); 2500 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' " 2501 "output to Rich.Liu@ite.com.tw\n"); 2502 return 0; 2503 } 2504 2505 pci_read_config_byte (pdev, 0x3c, &ite8872_irq); 2506 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt); 2507 ite8872_lpt &= 0x0000ff00; 2508 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi); 2509 ite8872_lpthi &= 0x0000ff00; 2510 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt); 2511 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi); 2512 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); 2513 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function 2514 // SET Parallel IRQ 2515 pci_write_config_dword (pdev, 0x9c, 2516 ite8872set | (ite8872_irq * 0x11111)); 2517 2518 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); 2519 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", 2520 ite8872_lpt); 2521 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", 2522 ite8872_lpthi); 2523 2524 /* Let the user (or defaults) steer us away from interrupts */ 2525 irq = ite8872_irq; 2526 if (autoirq != PARPORT_IRQ_AUTO) 2527 irq = PARPORT_IRQ_NONE; 2528 2529 /* 2530 * Release the resource so that parport_pc_probe_port can get it. 2531 */ 2532 release_resource(base_res); 2533 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi, 2534 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { 2535 printk (KERN_INFO 2536 "parport_pc: ITE 8872 parallel port: io=0x%X", 2537 ite8872_lpt); 2538 if (irq != PARPORT_IRQ_NONE) 2539 printk (", irq=%d", irq); 2540 printk ("\n"); 2541 return 1; 2542 } 2543 2544 return 0; 2545 } 2546 2547 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> 2548 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ 2549 static int __devinitdata parport_init_mode = 0; 2550 2551 /* Data for two known VIA chips */ 2552 static struct parport_pc_via_data via_686a_data __devinitdata = { 2553 0x51, 2554 0x50, 2555 0x85, 2556 0x02, 2557 0xE2, 2558 0xF0, 2559 0xE6 2560 }; 2561 static struct parport_pc_via_data via_8231_data __devinitdata = { 2562 0x45, 2563 0x44, 2564 0x50, 2565 0x04, 2566 0xF2, 2567 0xFA, 2568 0xF6 2569 }; 2570 2571 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq, 2572 int autodma, 2573 const struct parport_pc_via_data *via) 2574 { 2575 u8 tmp, tmp2, siofunc; 2576 u8 ppcontrol = 0; 2577 int dma, irq; 2578 unsigned port1, port2; 2579 unsigned have_epp = 0; 2580 2581 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); 2582 2583 switch(parport_init_mode) 2584 { 2585 case 1: 2586 printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); 2587 siofunc = VIA_FUNCTION_PARPORT_SPP; 2588 break; 2589 case 2: 2590 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); 2591 siofunc = VIA_FUNCTION_PARPORT_SPP; 2592 ppcontrol = VIA_PARPORT_BIDIR; 2593 break; 2594 case 3: 2595 printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); 2596 siofunc = VIA_FUNCTION_PARPORT_EPP; 2597 ppcontrol = VIA_PARPORT_BIDIR; 2598 have_epp = 1; 2599 break; 2600 case 4: 2601 printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); 2602 siofunc = VIA_FUNCTION_PARPORT_ECP; 2603 ppcontrol = VIA_PARPORT_BIDIR; 2604 break; 2605 case 5: 2606 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); 2607 siofunc = VIA_FUNCTION_PARPORT_ECP; 2608 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; 2609 have_epp = 1; 2610 break; 2611 default: 2612 printk(KERN_DEBUG "parport_pc: probing current configuration\n"); 2613 siofunc = VIA_FUNCTION_PROBE; 2614 break; 2615 } 2616 /* 2617 * unlock super i/o configuration 2618 */ 2619 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2620 tmp |= via->via_pci_superio_config_data; 2621 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2622 2623 /* Bits 1-0: Parallel Port Mode / Enable */ 2624 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2625 tmp = inb (VIA_CONFIG_DATA); 2626 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ 2627 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2628 tmp2 = inb (VIA_CONFIG_DATA); 2629 if (siofunc == VIA_FUNCTION_PROBE) 2630 { 2631 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; 2632 ppcontrol = tmp2; 2633 } 2634 else 2635 { 2636 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; 2637 tmp |= siofunc; 2638 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2639 outb(tmp, VIA_CONFIG_DATA); 2640 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); 2641 tmp2 |= ppcontrol; 2642 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2643 outb(tmp2, VIA_CONFIG_DATA); 2644 } 2645 2646 /* Parallel Port I/O Base Address, bits 9-2 */ 2647 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2648 port1 = inb(VIA_CONFIG_DATA) << 2; 2649 2650 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1); 2651 if ((port1 == 0x3BC) && have_epp) 2652 { 2653 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2654 outb((0x378 >> 2), VIA_CONFIG_DATA); 2655 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); 2656 port1 = 0x378; 2657 } 2658 2659 /* 2660 * lock super i/o configuration 2661 */ 2662 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2663 tmp &= ~via->via_pci_superio_config_data; 2664 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2665 2666 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { 2667 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); 2668 return 0; 2669 } 2670 2671 /* Bits 7-4: PnP Routing for Parallel Port IRQ */ 2672 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); 2673 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); 2674 2675 if (siofunc == VIA_FUNCTION_PARPORT_ECP) 2676 { 2677 /* Bits 3-2: PnP Routing for Parallel Port DMA */ 2678 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); 2679 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); 2680 } 2681 else 2682 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */ 2683 dma = PARPORT_DMA_NONE; 2684 2685 /* Let the user (or defaults) steer us away from interrupts and DMA */ 2686 if (autoirq == PARPORT_IRQ_NONE) { 2687 irq = PARPORT_IRQ_NONE; 2688 dma = PARPORT_DMA_NONE; 2689 } 2690 if (autodma == PARPORT_DMA_NONE) 2691 dma = PARPORT_DMA_NONE; 2692 2693 switch (port1) { 2694 case 0x3bc: port2 = 0x7bc; break; 2695 case 0x378: port2 = 0x778; break; 2696 case 0x278: port2 = 0x678; break; 2697 default: 2698 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n", 2699 port1); 2700 return 0; 2701 } 2702 2703 /* filter bogus IRQs */ 2704 switch (irq) { 2705 case 0: 2706 case 2: 2707 case 8: 2708 case 13: 2709 irq = PARPORT_IRQ_NONE; 2710 break; 2711 2712 default: /* do nothing */ 2713 break; 2714 } 2715 2716 /* finally, do the probe with values obtained */ 2717 if (parport_pc_probe_port (port1, port2, irq, dma, &pdev->dev, 0)) { 2718 printk (KERN_INFO 2719 "parport_pc: VIA parallel port: io=0x%X", port1); 2720 if (irq != PARPORT_IRQ_NONE) 2721 printk (", irq=%d", irq); 2722 if (dma != PARPORT_DMA_NONE) 2723 printk (", dma=%d", dma); 2724 printk ("\n"); 2725 return 1; 2726 } 2727 2728 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", 2729 port1, irq, dma); 2730 return 0; 2731 } 2732 2733 2734 enum parport_pc_sio_types { 2735 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ 2736 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ 2737 sio_ite_8872, 2738 last_sio 2739 }; 2740 2741 /* each element directly indexed from enum list, above */ 2742 static struct parport_pc_superio { 2743 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, 2744 const struct parport_pc_via_data *via); 2745 const struct parport_pc_via_data *via; 2746 } parport_pc_superio_info[] __devinitdata = { 2747 { sio_via_probe, &via_686a_data, }, 2748 { sio_via_probe, &via_8231_data, }, 2749 { sio_ite_8872_probe, NULL, }, 2750 }; 2751 2752 enum parport_pc_pci_cards { 2753 siig_1p_10x = last_sio, 2754 siig_2p_10x, 2755 siig_1p_20x, 2756 siig_2p_20x, 2757 lava_parallel, 2758 lava_parallel_dual_a, 2759 lava_parallel_dual_b, 2760 boca_ioppar, 2761 plx_9050, 2762 timedia_4078a, 2763 timedia_4079h, 2764 timedia_4085h, 2765 timedia_4088a, 2766 timedia_4089a, 2767 timedia_4095a, 2768 timedia_4096a, 2769 timedia_4078u, 2770 timedia_4079a, 2771 timedia_4085u, 2772 timedia_4079r, 2773 timedia_4079s, 2774 timedia_4079d, 2775 timedia_4079e, 2776 timedia_4079f, 2777 timedia_9079a, 2778 timedia_9079b, 2779 timedia_9079c, 2780 timedia_4006a, 2781 timedia_4014, 2782 timedia_4008a, 2783 timedia_4018, 2784 timedia_9018a, 2785 syba_2p_epp, 2786 syba_1p_ecp, 2787 titan_010l, 2788 titan_1284p1, 2789 titan_1284p2, 2790 avlab_1p, 2791 avlab_2p, 2792 oxsemi_952, 2793 oxsemi_954, 2794 oxsemi_840, 2795 oxsemi_pcie_pport, 2796 aks_0100, 2797 mobility_pp, 2798 netmos_9705, 2799 netmos_9715, 2800 netmos_9755, 2801 netmos_9805, 2802 netmos_9815, 2803 quatech_sppxp100, 2804 }; 2805 2806 2807 /* each element directly indexed from enum list, above 2808 * (but offset by last_sio) */ 2809 static struct parport_pc_pci { 2810 int numports; 2811 struct { /* BAR (base address registers) numbers in the config 2812 space header */ 2813 int lo; 2814 int hi; /* -1 if not there, >6 for offset-method (max 2815 BAR is 6) */ 2816 } addr[4]; 2817 2818 /* If set, this is called immediately after pci_enable_device. 2819 * If it returns non-zero, no probing will take place and the 2820 * ports will not be used. */ 2821 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); 2822 2823 /* If set, this is called after probing for ports. If 'failed' 2824 * is non-zero we couldn't use any of the ports. */ 2825 void (*postinit_hook) (struct pci_dev *pdev, int failed); 2826 } cards[] = { 2827 /* siig_1p_10x */ { 1, { { 2, 3 }, } }, 2828 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2829 /* siig_1p_20x */ { 1, { { 0, 1 }, } }, 2830 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2831 /* lava_parallel */ { 1, { { 0, -1 }, } }, 2832 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, 2833 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, 2834 /* boca_ioppar */ { 1, { { 0, -1 }, } }, 2835 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, 2836 /* timedia_4078a */ { 1, { { 2, -1 }, } }, 2837 /* timedia_4079h */ { 1, { { 2, 3 }, } }, 2838 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2839 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2840 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2841 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2842 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2843 /* timedia_4078u */ { 1, { { 2, -1 }, } }, 2844 /* timedia_4079a */ { 1, { { 2, 3 }, } }, 2845 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2846 /* timedia_4079r */ { 1, { { 2, 3 }, } }, 2847 /* timedia_4079s */ { 1, { { 2, 3 }, } }, 2848 /* timedia_4079d */ { 1, { { 2, 3 }, } }, 2849 /* timedia_4079e */ { 1, { { 2, 3 }, } }, 2850 /* timedia_4079f */ { 1, { { 2, 3 }, } }, 2851 /* timedia_9079a */ { 1, { { 2, 3 }, } }, 2852 /* timedia_9079b */ { 1, { { 2, 3 }, } }, 2853 /* timedia_9079c */ { 1, { { 2, 3 }, } }, 2854 /* timedia_4006a */ { 1, { { 0, -1 }, } }, 2855 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, 2856 /* timedia_4008a */ { 1, { { 0, 1 }, } }, 2857 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2858 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2859 /* SYBA uses fixed offsets in 2860 a 1K io window */ 2861 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, 2862 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, 2863 /* titan_010l */ { 1, { { 3, -1 }, } }, 2864 /* titan_1284p1 */ { 1, { { 0, 1 }, } }, 2865 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2866 /* avlab_1p */ { 1, { { 0, 1}, } }, 2867 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, 2868 /* The Oxford Semi cards are unusual: 954 doesn't support ECP, 2869 * and 840 locks up if you write 1 to bit 2! */ 2870 /* oxsemi_952 */ { 1, { { 0, 1 }, } }, 2871 /* oxsemi_954 */ { 1, { { 0, -1 }, } }, 2872 /* oxsemi_840 */ { 1, { { 0, 1 }, } }, 2873 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } }, 2874 /* aks_0100 */ { 1, { { 0, -1 }, } }, 2875 /* mobility_pp */ { 1, { { 0, 1 }, } }, 2876 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */ 2877 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2878 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2879 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */ 2880 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */ 2881 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } }, 2882 }; 2883 2884 static const struct pci_device_id parport_pc_pci_tbl[] = { 2885 /* Super-IO onboard chips */ 2886 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, 2887 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, 2888 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 2889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, 2890 2891 /* PCI cards */ 2892 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, 2893 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, 2894 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, 2895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, 2896 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, 2897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, 2898 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, 2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, 2900 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, 2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, 2902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, 2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, 2904 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, 2905 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, 2906 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, 2907 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, 2908 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2909 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 }, 2910 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ 2911 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a }, 2912 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h }, 2913 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h }, 2914 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a }, 2915 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a }, 2916 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a }, 2917 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a }, 2918 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u }, 2919 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a }, 2920 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u }, 2921 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r }, 2922 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s }, 2923 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d }, 2924 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e }, 2925 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f }, 2926 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a }, 2927 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b }, 2928 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, 2929 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, 2930 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, 2931 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, 2932 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, 2933 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, 2934 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, 2935 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, 2936 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, 2937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, 2938 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, 2939 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, 2940 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, 2941 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, 2942 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ 2943 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */ 2944 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, 2945 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, 2946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, 2947 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, 2948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, 2949 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, 2950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, 2951 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840, 2952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2953 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G, 2954 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2955 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0, 2956 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2957 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G, 2958 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2959 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1, 2960 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2961 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G, 2962 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2963 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U, 2964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2965 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU, 2966 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport }, 2967 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, 2968 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, 2969 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, 2970 /* NetMos communication controllers */ 2971 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, 2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, 2973 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, 2974 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, 2975 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, 2976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, 2977 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, 2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, 2979 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, 2980 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, 2981 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */ 2982 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100, 2983 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 }, 2984 { 0, } /* terminate list */ 2985 }; 2986 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl); 2987 2988 struct pci_parport_data { 2989 int num; 2990 struct parport *ports[2]; 2991 }; 2992 2993 static int parport_pc_pci_probe (struct pci_dev *dev, 2994 const struct pci_device_id *id) 2995 { 2996 int err, count, n, i = id->driver_data; 2997 struct pci_parport_data *data; 2998 2999 if (i < last_sio) 3000 /* This is an onboard Super-IO and has already been probed */ 3001 return 0; 3002 3003 /* This is a PCI card */ 3004 i -= last_sio; 3005 count = 0; 3006 if ((err = pci_enable_device (dev)) != 0) 3007 return err; 3008 3009 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); 3010 if (!data) 3011 return -ENOMEM; 3012 3013 if (cards[i].preinit_hook && 3014 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { 3015 kfree(data); 3016 return -ENODEV; 3017 } 3018 3019 for (n = 0; n < cards[i].numports; n++) { 3020 int lo = cards[i].addr[n].lo; 3021 int hi = cards[i].addr[n].hi; 3022 int irq; 3023 unsigned long io_lo, io_hi; 3024 io_lo = pci_resource_start (dev, lo); 3025 io_hi = 0; 3026 if ((hi >= 0) && (hi <= 6)) 3027 io_hi = pci_resource_start (dev, hi); 3028 else if (hi > 6) 3029 io_lo += hi; /* Reinterpret the meaning of 3030 "hi" as an offset (see SYBA 3031 def.) */ 3032 /* TODO: test if sharing interrupts works */ 3033 irq = dev->irq; 3034 if (irq == IRQ_NONE) { 3035 printk (KERN_DEBUG 3036 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", 3037 parport_pc_pci_tbl[i + last_sio].vendor, 3038 parport_pc_pci_tbl[i + last_sio].device, 3039 io_lo, io_hi); 3040 irq = PARPORT_IRQ_NONE; 3041 } else { 3042 printk (KERN_DEBUG 3043 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", 3044 parport_pc_pci_tbl[i + last_sio].vendor, 3045 parport_pc_pci_tbl[i + last_sio].device, 3046 io_lo, io_hi, irq); 3047 } 3048 data->ports[count] = 3049 parport_pc_probe_port(io_lo, io_hi, irq, 3050 PARPORT_DMA_NONE, &dev->dev, 3051 IRQF_SHARED); 3052 if (data->ports[count]) 3053 count++; 3054 } 3055 3056 data->num = count; 3057 3058 if (cards[i].postinit_hook) 3059 cards[i].postinit_hook (dev, count == 0); 3060 3061 if (count) { 3062 pci_set_drvdata(dev, data); 3063 return 0; 3064 } 3065 3066 kfree(data); 3067 3068 return -ENODEV; 3069 } 3070 3071 static void __devexit parport_pc_pci_remove(struct pci_dev *dev) 3072 { 3073 struct pci_parport_data *data = pci_get_drvdata(dev); 3074 int i; 3075 3076 pci_set_drvdata(dev, NULL); 3077 3078 if (data) { 3079 for (i = data->num - 1; i >= 0; i--) 3080 parport_pc_unregister_port(data->ports[i]); 3081 3082 kfree(data); 3083 } 3084 } 3085 3086 static struct pci_driver parport_pc_pci_driver = { 3087 .name = "parport_pc", 3088 .id_table = parport_pc_pci_tbl, 3089 .probe = parport_pc_pci_probe, 3090 .remove = __devexit_p(parport_pc_pci_remove), 3091 }; 3092 3093 static int __init parport_pc_init_superio (int autoirq, int autodma) 3094 { 3095 const struct pci_device_id *id; 3096 struct pci_dev *pdev = NULL; 3097 int ret = 0; 3098 3099 for_each_pci_dev(pdev) { 3100 id = pci_match_id(parport_pc_pci_tbl, pdev); 3101 if (id == NULL || id->driver_data >= last_sio) 3102 continue; 3103 3104 if (parport_pc_superio_info[id->driver_data].probe 3105 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) { 3106 ret++; 3107 } 3108 } 3109 3110 return ret; /* number of devices found */ 3111 } 3112 #else 3113 static struct pci_driver parport_pc_pci_driver; 3114 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;} 3115 #endif /* CONFIG_PCI */ 3116 3117 #ifdef CONFIG_PNP 3118 3119 static const struct pnp_device_id parport_pc_pnp_tbl[] = { 3120 /* Standard LPT Printer Port */ 3121 {.id = "PNP0400", .driver_data = 0}, 3122 /* ECP Printer Port */ 3123 {.id = "PNP0401", .driver_data = 0}, 3124 { } 3125 }; 3126 3127 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl); 3128 3129 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) 3130 { 3131 struct parport *pdata; 3132 unsigned long io_lo, io_hi; 3133 int dma, irq; 3134 3135 if (pnp_port_valid(dev,0) && 3136 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) { 3137 io_lo = pnp_port_start(dev,0); 3138 } else 3139 return -EINVAL; 3140 3141 if (pnp_port_valid(dev,1) && 3142 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) { 3143 io_hi = pnp_port_start(dev,1); 3144 } else 3145 io_hi = 0; 3146 3147 if (pnp_irq_valid(dev,0) && 3148 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) { 3149 irq = pnp_irq(dev,0); 3150 } else 3151 irq = PARPORT_IRQ_NONE; 3152 3153 if (pnp_dma_valid(dev,0) && 3154 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) { 3155 dma = pnp_dma(dev,0); 3156 } else 3157 dma = PARPORT_DMA_NONE; 3158 3159 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); 3160 if (!(pdata = parport_pc_probe_port(io_lo, io_hi, 3161 irq, dma, &dev->dev, 0))) 3162 return -ENODEV; 3163 3164 pnp_set_drvdata(dev,pdata); 3165 return 0; 3166 } 3167 3168 static void parport_pc_pnp_remove(struct pnp_dev *dev) 3169 { 3170 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); 3171 if (!pdata) 3172 return; 3173 3174 parport_pc_unregister_port(pdata); 3175 } 3176 3177 /* we only need the pnp layer to activate the device, at least for now */ 3178 static struct pnp_driver parport_pc_pnp_driver = { 3179 .name = "parport_pc", 3180 .id_table = parport_pc_pnp_tbl, 3181 .probe = parport_pc_pnp_probe, 3182 .remove = parport_pc_pnp_remove, 3183 }; 3184 3185 #else 3186 static struct pnp_driver parport_pc_pnp_driver; 3187 #endif /* CONFIG_PNP */ 3188 3189 static int __devinit parport_pc_platform_probe(struct platform_device *pdev) 3190 { 3191 /* Always succeed, the actual probing is done in 3192 * parport_pc_probe_port(). */ 3193 return 0; 3194 } 3195 3196 static struct platform_driver parport_pc_platform_driver = { 3197 .driver = { 3198 .owner = THIS_MODULE, 3199 .name = "parport_pc", 3200 }, 3201 .probe = parport_pc_platform_probe, 3202 }; 3203 3204 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ 3205 static int __devinit __attribute__((unused)) 3206 parport_pc_find_isa_ports (int autoirq, int autodma) 3207 { 3208 int count = 0; 3209 3210 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) 3211 count++; 3212 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) 3213 count++; 3214 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) 3215 count++; 3216 3217 return count; 3218 } 3219 3220 /* This function is called by parport_pc_init if the user didn't 3221 * specify any ports to probe. Its job is to find some ports. Order 3222 * is important here -- we want ISA ports to be registered first, 3223 * followed by PCI cards (for least surprise), but before that we want 3224 * to do chipset-specific tests for some onboard ports that we know 3225 * about. 3226 * 3227 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY 3228 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO 3229 */ 3230 static void __init parport_pc_find_ports (int autoirq, int autodma) 3231 { 3232 int count = 0, err; 3233 3234 #ifdef CONFIG_PARPORT_PC_SUPERIO 3235 detect_and_report_it87(); 3236 detect_and_report_winbond(); 3237 detect_and_report_smsc(); 3238 #endif 3239 3240 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ 3241 count += parport_pc_init_superio(autoirq, autodma); 3242 3243 /* PnP ports, skip detection if SuperIO already found them */ 3244 if (!count) { 3245 err = pnp_register_driver(&parport_pc_pnp_driver); 3246 if (!err) 3247 pnp_registered_parport = 1; 3248 } 3249 3250 /* ISA ports and whatever (see asm/parport.h). */ 3251 parport_pc_find_nonpci_ports(autoirq, autodma); 3252 3253 err = pci_register_driver(&parport_pc_pci_driver); 3254 if (!err) 3255 pci_registered_parport = 1; 3256 } 3257 3258 /* 3259 * Piles of crap below pretend to be a parser for module and kernel 3260 * parameters. Say "thank you" to whoever had come up with that 3261 * syntax and keep in mind that code below is a cleaned up version. 3262 */ 3263 3264 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 }; 3265 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = 3266 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO }; 3267 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE }; 3268 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY }; 3269 3270 static int __init parport_parse_param(const char *s, int *val, 3271 int automatic, int none, int nofifo) 3272 { 3273 if (!s) 3274 return 0; 3275 if (!strncmp(s, "auto", 4)) 3276 *val = automatic; 3277 else if (!strncmp(s, "none", 4)) 3278 *val = none; 3279 else if (nofifo && !strncmp(s, "nofifo", 4)) 3280 *val = nofifo; 3281 else { 3282 char *ep; 3283 unsigned long r = simple_strtoul(s, &ep, 0); 3284 if (ep != s) 3285 *val = r; 3286 else { 3287 printk(KERN_ERR "parport: bad specifier `%s'\n", s); 3288 return -1; 3289 } 3290 } 3291 return 0; 3292 } 3293 3294 static int __init parport_parse_irq(const char *irqstr, int *val) 3295 { 3296 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, 3297 PARPORT_IRQ_NONE, 0); 3298 } 3299 3300 static int __init parport_parse_dma(const char *dmastr, int *val) 3301 { 3302 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, 3303 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); 3304 } 3305 3306 #ifdef CONFIG_PCI 3307 static int __init parport_init_mode_setup(char *str) 3308 { 3309 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); 3310 3311 if (!strcmp (str, "spp")) 3312 parport_init_mode=1; 3313 if (!strcmp (str, "ps2")) 3314 parport_init_mode=2; 3315 if (!strcmp (str, "epp")) 3316 parport_init_mode=3; 3317 if (!strcmp (str, "ecp")) 3318 parport_init_mode=4; 3319 if (!strcmp (str, "ecpepp")) 3320 parport_init_mode=5; 3321 return 1; 3322 } 3323 #endif 3324 3325 #ifdef MODULE 3326 static const char *irq[PARPORT_PC_MAX_PORTS]; 3327 static const char *dma[PARPORT_PC_MAX_PORTS]; 3328 3329 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); 3330 module_param_array(io, int, NULL, 0); 3331 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); 3332 module_param_array(io_hi, int, NULL, 0); 3333 MODULE_PARM_DESC(irq, "IRQ line"); 3334 module_param_array(irq, charp, NULL, 0); 3335 MODULE_PARM_DESC(dma, "DMA channel"); 3336 module_param_array(dma, charp, NULL, 0); 3337 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 3338 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 3339 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); 3340 module_param(verbose_probing, int, 0644); 3341 #endif 3342 #ifdef CONFIG_PCI 3343 static char *init_mode; 3344 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); 3345 module_param(init_mode, charp, 0); 3346 #endif 3347 3348 static int __init parse_parport_params(void) 3349 { 3350 unsigned int i; 3351 int val; 3352 3353 #ifdef CONFIG_PCI 3354 if (init_mode) 3355 parport_init_mode_setup(init_mode); 3356 #endif 3357 3358 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { 3359 if (parport_parse_irq(irq[i], &val)) 3360 return 1; 3361 irqval[i] = val; 3362 if (parport_parse_dma(dma[i], &val)) 3363 return 1; 3364 dmaval[i] = val; 3365 } 3366 if (!io[0]) { 3367 /* The user can make us use any IRQs or DMAs we find. */ 3368 if (irq[0] && !parport_parse_irq(irq[0], &val)) 3369 switch (val) { 3370 case PARPORT_IRQ_NONE: 3371 case PARPORT_IRQ_AUTO: 3372 irqval[0] = val; 3373 break; 3374 default: 3375 printk (KERN_WARNING 3376 "parport_pc: irq specified " 3377 "without base address. Use 'io=' " 3378 "to specify one\n"); 3379 } 3380 3381 if (dma[0] && !parport_parse_dma(dma[0], &val)) 3382 switch (val) { 3383 case PARPORT_DMA_NONE: 3384 case PARPORT_DMA_AUTO: 3385 dmaval[0] = val; 3386 break; 3387 default: 3388 printk (KERN_WARNING 3389 "parport_pc: dma specified " 3390 "without base address. Use 'io=' " 3391 "to specify one\n"); 3392 } 3393 } 3394 return 0; 3395 } 3396 3397 #else 3398 3399 static int parport_setup_ptr __initdata = 0; 3400 3401 /* 3402 * Acceptable parameters: 3403 * 3404 * parport=0 3405 * parport=auto 3406 * parport=0xBASE[,IRQ[,DMA]] 3407 * 3408 * IRQ/DMA may be numeric or 'auto' or 'none' 3409 */ 3410 static int __init parport_setup (char *str) 3411 { 3412 char *endptr; 3413 char *sep; 3414 int val; 3415 3416 if (!str || !*str || (*str == '0' && !*(str+1))) { 3417 /* Disable parport if "parport=0" in cmdline */ 3418 io[0] = PARPORT_DISABLE; 3419 return 1; 3420 } 3421 3422 if (!strncmp (str, "auto", 4)) { 3423 irqval[0] = PARPORT_IRQ_AUTO; 3424 dmaval[0] = PARPORT_DMA_AUTO; 3425 return 1; 3426 } 3427 3428 val = simple_strtoul (str, &endptr, 0); 3429 if (endptr == str) { 3430 printk (KERN_WARNING "parport=%s not understood\n", str); 3431 return 1; 3432 } 3433 3434 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { 3435 printk(KERN_ERR "parport=%s ignored, too many ports\n", str); 3436 return 1; 3437 } 3438 3439 io[parport_setup_ptr] = val; 3440 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; 3441 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; 3442 3443 sep = strchr(str, ','); 3444 if (sep++) { 3445 if (parport_parse_irq(sep, &val)) 3446 return 1; 3447 irqval[parport_setup_ptr] = val; 3448 sep = strchr(sep, ','); 3449 if (sep++) { 3450 if (parport_parse_dma(sep, &val)) 3451 return 1; 3452 dmaval[parport_setup_ptr] = val; 3453 } 3454 } 3455 parport_setup_ptr++; 3456 return 1; 3457 } 3458 3459 static int __init parse_parport_params(void) 3460 { 3461 return io[0] == PARPORT_DISABLE; 3462 } 3463 3464 __setup ("parport=", parport_setup); 3465 3466 /* 3467 * Acceptable parameters: 3468 * 3469 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] 3470 */ 3471 #ifdef CONFIG_PCI 3472 __setup("parport_init_mode=",parport_init_mode_setup); 3473 #endif 3474 #endif 3475 3476 /* "Parser" ends here */ 3477 3478 static int __init parport_pc_init(void) 3479 { 3480 int err; 3481 3482 if (parse_parport_params()) 3483 return -EINVAL; 3484 3485 err = platform_driver_register(&parport_pc_platform_driver); 3486 if (err) 3487 return err; 3488 3489 if (io[0]) { 3490 int i; 3491 /* Only probe the ports we were given. */ 3492 user_specified = 1; 3493 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { 3494 if (!io[i]) 3495 break; 3496 if ((io_hi[i]) == PARPORT_IOHI_AUTO) 3497 io_hi[i] = 0x400 + io[i]; 3498 parport_pc_probe_port(io[i], io_hi[i], 3499 irqval[i], dmaval[i], NULL, 0); 3500 } 3501 } else 3502 parport_pc_find_ports (irqval[0], dmaval[0]); 3503 3504 return 0; 3505 } 3506 3507 static void __exit parport_pc_exit(void) 3508 { 3509 if (pci_registered_parport) 3510 pci_unregister_driver (&parport_pc_pci_driver); 3511 if (pnp_registered_parport) 3512 pnp_unregister_driver (&parport_pc_pnp_driver); 3513 platform_driver_unregister(&parport_pc_platform_driver); 3514 3515 while (!list_empty(&ports_list)) { 3516 struct parport_pc_private *priv; 3517 struct parport *port; 3518 priv = list_entry(ports_list.next, 3519 struct parport_pc_private, list); 3520 port = priv->port; 3521 if (port->dev && port->dev->bus == &platform_bus_type) 3522 platform_device_unregister( 3523 to_platform_device(port->dev)); 3524 parport_pc_unregister_port(port); 3525 } 3526 } 3527 3528 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); 3529 MODULE_DESCRIPTION("PC-style parallel port driver"); 3530 MODULE_LICENSE("GPL"); 3531 module_init(parport_pc_init) 3532 module_exit(parport_pc_exit) 3533