1 /* Low-level parallel-port routines for 8255-based PC-style hardware. 2 * 3 * Authors: Phil Blundell <philb@gnu.org> 4 * Tim Waugh <tim@cyberelk.demon.co.uk> 5 * Jose Renau <renau@acm.org> 6 * David Campbell 7 * Andrea Arcangeli 8 * 9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell. 10 * 11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org> 12 * DMA support - Bert De Jonghe <bert@sophis.be> 13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999 14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G. 15 * Various hacks, Fred Barnes, 04/2001 16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com> 17 */ 18 19 /* This driver should work with any hardware that is broadly compatible 20 * with that in the IBM PC. This applies to the majority of integrated 21 * I/O chipsets that are commonly available. The expected register 22 * layout is: 23 * 24 * base+0 data 25 * base+1 status 26 * base+2 control 27 * 28 * In addition, there are some optional registers: 29 * 30 * base+3 EPP address 31 * base+4 EPP data 32 * base+0x400 ECP config A 33 * base+0x401 ECP config B 34 * base+0x402 ECP control 35 * 36 * All registers are 8 bits wide and read/write. If your hardware differs 37 * only in register addresses (eg because your registers are on 32-bit 38 * word boundaries) then you can alter the constants in parport_pc.h to 39 * accommodate this. 40 * 41 * Note that the ECP registers may not start at offset 0x400 for PCI cards, 42 * but rather will start at port->base_hi. 43 */ 44 45 #include <linux/module.h> 46 #include <linux/init.h> 47 #include <linux/sched.h> 48 #include <linux/delay.h> 49 #include <linux/errno.h> 50 #include <linux/interrupt.h> 51 #include <linux/ioport.h> 52 #include <linux/kernel.h> 53 #include <linux/slab.h> 54 #include <linux/dma-mapping.h> 55 #include <linux/pci.h> 56 #include <linux/pnp.h> 57 #include <linux/platform_device.h> 58 #include <linux/sysctl.h> 59 60 #include <asm/io.h> 61 #include <asm/dma.h> 62 #include <asm/uaccess.h> 63 64 #include <linux/parport.h> 65 #include <linux/parport_pc.h> 66 #include <linux/via.h> 67 #include <asm/parport.h> 68 69 #define PARPORT_PC_MAX_PORTS PARPORT_MAX 70 71 #ifdef CONFIG_ISA_DMA_API 72 #define HAS_DMA 73 #endif 74 75 /* ECR modes */ 76 #define ECR_SPP 00 77 #define ECR_PS2 01 78 #define ECR_PPF 02 79 #define ECR_ECP 03 80 #define ECR_EPP 04 81 #define ECR_VND 05 82 #define ECR_TST 06 83 #define ECR_CNF 07 84 #define ECR_MODE_MASK 0xe0 85 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v)) 86 87 #undef DEBUG 88 89 #ifdef DEBUG 90 #define DPRINTK printk 91 #else 92 #define DPRINTK(stuff...) 93 #endif 94 95 96 #define NR_SUPERIOS 3 97 static struct superio_struct { /* For Super-IO chips autodetection */ 98 int io; 99 int irq; 100 int dma; 101 } superios[NR_SUPERIOS] = { {0,},}; 102 103 static int user_specified; 104 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 106 static int verbose_probing; 107 #endif 108 static int pci_registered_parport; 109 static int pnp_registered_parport; 110 111 /* frob_control, but for ECR */ 112 static void frob_econtrol (struct parport *pb, unsigned char m, 113 unsigned char v) 114 { 115 unsigned char ectr = 0; 116 117 if (m != 0xff) 118 ectr = inb (ECONTROL (pb)); 119 120 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", 121 m, v, ectr, (ectr & ~m) ^ v); 122 123 outb ((ectr & ~m) ^ v, ECONTROL (pb)); 124 } 125 126 static __inline__ void frob_set_mode (struct parport *p, int mode) 127 { 128 frob_econtrol (p, ECR_MODE_MASK, mode << 5); 129 } 130 131 #ifdef CONFIG_PARPORT_PC_FIFO 132 /* Safely change the mode bits in the ECR 133 Returns: 134 0 : Success 135 -EBUSY: Could not drain FIFO in some finite amount of time, 136 mode not changed! 137 */ 138 static int change_mode(struct parport *p, int m) 139 { 140 const struct parport_pc_private *priv = p->physport->private_data; 141 unsigned char oecr; 142 int mode; 143 144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m); 145 146 if (!priv->ecr) { 147 printk (KERN_DEBUG "change_mode: but there's no ECR!\n"); 148 return 0; 149 } 150 151 /* Bits <7:5> contain the mode. */ 152 oecr = inb (ECONTROL (p)); 153 mode = (oecr >> 5) & 0x7; 154 if (mode == m) return 0; 155 156 if (mode >= 2 && !(priv->ctr & 0x20)) { 157 /* This mode resets the FIFO, so we may 158 * have to wait for it to drain first. */ 159 unsigned long expire = jiffies + p->physport->cad->timeout; 160 int counter; 161 switch (mode) { 162 case ECR_PPF: /* Parallel Port FIFO mode */ 163 case ECR_ECP: /* ECP Parallel Port mode */ 164 /* Busy wait for 200us */ 165 for (counter = 0; counter < 40; counter++) { 166 if (inb (ECONTROL (p)) & 0x01) 167 break; 168 if (signal_pending (current)) break; 169 udelay (5); 170 } 171 172 /* Poll slowly. */ 173 while (!(inb (ECONTROL (p)) & 0x01)) { 174 if (time_after_eq (jiffies, expire)) 175 /* The FIFO is stuck. */ 176 return -EBUSY; 177 schedule_timeout_interruptible(msecs_to_jiffies(10)); 178 if (signal_pending (current)) 179 break; 180 } 181 } 182 } 183 184 if (mode >= 2 && m >= 2) { 185 /* We have to go through mode 001 */ 186 oecr &= ~(7 << 5); 187 oecr |= ECR_PS2 << 5; 188 ECR_WRITE (p, oecr); 189 } 190 191 /* Set the mode. */ 192 oecr &= ~(7 << 5); 193 oecr |= m << 5; 194 ECR_WRITE (p, oecr); 195 return 0; 196 } 197 198 #ifdef CONFIG_PARPORT_1284 199 /* Find FIFO lossage; FIFO is reset */ 200 #if 0 201 static int get_fifo_residue (struct parport *p) 202 { 203 int residue; 204 int cnfga; 205 const struct parport_pc_private *priv = p->physport->private_data; 206 207 /* Adjust for the contents of the FIFO. */ 208 for (residue = priv->fifo_depth; ; residue--) { 209 if (inb (ECONTROL (p)) & 0x2) 210 /* Full up. */ 211 break; 212 213 outb (0, FIFO (p)); 214 } 215 216 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name, 217 residue); 218 219 /* Reset the FIFO. */ 220 frob_set_mode (p, ECR_PS2); 221 222 /* Now change to config mode and clean up. FIXME */ 223 frob_set_mode (p, ECR_CNF); 224 cnfga = inb (CONFIGA (p)); 225 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga); 226 227 if (!(cnfga & (1<<2))) { 228 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name); 229 residue++; 230 } 231 232 /* Don't care about partial PWords until support is added for 233 * PWord != 1 byte. */ 234 235 /* Back to PS2 mode. */ 236 frob_set_mode (p, ECR_PS2); 237 238 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p))); 239 return residue; 240 } 241 #endif /* 0 */ 242 #endif /* IEEE 1284 support */ 243 #endif /* FIFO support */ 244 245 /* 246 * Clear TIMEOUT BIT in EPP MODE 247 * 248 * This is also used in SPP detection. 249 */ 250 static int clear_epp_timeout(struct parport *pb) 251 { 252 unsigned char r; 253 254 if (!(parport_pc_read_status(pb) & 0x01)) 255 return 1; 256 257 /* To clear timeout some chips require double read */ 258 parport_pc_read_status(pb); 259 r = parport_pc_read_status(pb); 260 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */ 261 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */ 262 r = parport_pc_read_status(pb); 263 264 return !(r & 0x01); 265 } 266 267 /* 268 * Access functions. 269 * 270 * Most of these aren't static because they may be used by the 271 * parport_xxx_yyy macros. extern __inline__ versions of several 272 * of these are in parport_pc.h. 273 */ 274 275 static void parport_pc_init_state(struct pardevice *dev, struct parport_state *s) 276 { 277 s->u.pc.ctr = 0xc; 278 if (dev->irq_func && 279 dev->port->irq != PARPORT_IRQ_NONE) 280 /* Set ackIntEn */ 281 s->u.pc.ctr |= 0x10; 282 283 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; 284 * D.Gruszka VScom */ 285 } 286 287 static void parport_pc_save_state(struct parport *p, struct parport_state *s) 288 { 289 const struct parport_pc_private *priv = p->physport->private_data; 290 s->u.pc.ctr = priv->ctr; 291 if (priv->ecr) 292 s->u.pc.ecr = inb (ECONTROL (p)); 293 } 294 295 static void parport_pc_restore_state(struct parport *p, struct parport_state *s) 296 { 297 struct parport_pc_private *priv = p->physport->private_data; 298 register unsigned char c = s->u.pc.ctr & priv->ctr_writable; 299 outb (c, CONTROL (p)); 300 priv->ctr = c; 301 if (priv->ecr) 302 ECR_WRITE (p, s->u.pc.ecr); 303 } 304 305 #ifdef CONFIG_PARPORT_1284 306 static size_t parport_pc_epp_read_data (struct parport *port, void *buf, 307 size_t length, int flags) 308 { 309 size_t got = 0; 310 311 if (flags & PARPORT_W91284PIC) { 312 unsigned char status; 313 size_t left = length; 314 315 /* use knowledge about data lines..: 316 * nFault is 0 if there is at least 1 byte in the Warp's FIFO 317 * pError is 1 if there are 16 bytes in the Warp's FIFO 318 */ 319 status = inb (STATUS (port)); 320 321 while (!(status & 0x08) && (got < length)) { 322 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) { 323 /* can grab 16 bytes from warp fifo */ 324 if (!((long)buf & 0x03)) { 325 insl (EPPDATA (port), buf, 4); 326 } else { 327 insb (EPPDATA (port), buf, 16); 328 } 329 buf += 16; 330 got += 16; 331 left -= 16; 332 } else { 333 /* grab single byte from the warp fifo */ 334 *((char *)buf) = inb (EPPDATA (port)); 335 buf++; 336 got++; 337 left--; 338 } 339 status = inb (STATUS (port)); 340 if (status & 0x01) { 341 /* EPP timeout should never occur... */ 342 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to " 343 "w91284pic (should not have done)\n", port->name); 344 clear_epp_timeout (port); 345 } 346 } 347 return got; 348 } 349 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 350 if (!(((long)buf | length) & 0x03)) { 351 insl (EPPDATA (port), buf, (length >> 2)); 352 } else { 353 insb (EPPDATA (port), buf, length); 354 } 355 if (inb (STATUS (port)) & 0x01) { 356 clear_epp_timeout (port); 357 return -EIO; 358 } 359 return length; 360 } 361 for (; got < length; got++) { 362 *((char*)buf) = inb (EPPDATA(port)); 363 buf++; 364 if (inb (STATUS (port)) & 0x01) { 365 /* EPP timeout */ 366 clear_epp_timeout (port); 367 break; 368 } 369 } 370 371 return got; 372 } 373 374 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf, 375 size_t length, int flags) 376 { 377 size_t written = 0; 378 379 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 380 if (!(((long)buf | length) & 0x03)) { 381 outsl (EPPDATA (port), buf, (length >> 2)); 382 } else { 383 outsb (EPPDATA (port), buf, length); 384 } 385 if (inb (STATUS (port)) & 0x01) { 386 clear_epp_timeout (port); 387 return -EIO; 388 } 389 return length; 390 } 391 for (; written < length; written++) { 392 outb (*((char*)buf), EPPDATA(port)); 393 buf++; 394 if (inb (STATUS(port)) & 0x01) { 395 clear_epp_timeout (port); 396 break; 397 } 398 } 399 400 return written; 401 } 402 403 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf, 404 size_t length, int flags) 405 { 406 size_t got = 0; 407 408 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 409 insb (EPPADDR (port), buf, length); 410 if (inb (STATUS (port)) & 0x01) { 411 clear_epp_timeout (port); 412 return -EIO; 413 } 414 return length; 415 } 416 for (; got < length; got++) { 417 *((char*)buf) = inb (EPPADDR (port)); 418 buf++; 419 if (inb (STATUS (port)) & 0x01) { 420 clear_epp_timeout (port); 421 break; 422 } 423 } 424 425 return got; 426 } 427 428 static size_t parport_pc_epp_write_addr (struct parport *port, 429 const void *buf, size_t length, 430 int flags) 431 { 432 size_t written = 0; 433 434 if ((flags & PARPORT_EPP_FAST) && (length > 1)) { 435 outsb (EPPADDR (port), buf, length); 436 if (inb (STATUS (port)) & 0x01) { 437 clear_epp_timeout (port); 438 return -EIO; 439 } 440 return length; 441 } 442 for (; written < length; written++) { 443 outb (*((char*)buf), EPPADDR (port)); 444 buf++; 445 if (inb (STATUS (port)) & 0x01) { 446 clear_epp_timeout (port); 447 break; 448 } 449 } 450 451 return written; 452 } 453 454 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf, 455 size_t length, int flags) 456 { 457 size_t got; 458 459 frob_set_mode (port, ECR_EPP); 460 parport_pc_data_reverse (port); 461 parport_pc_write_control (port, 0x4); 462 got = parport_pc_epp_read_data (port, buf, length, flags); 463 frob_set_mode (port, ECR_PS2); 464 465 return got; 466 } 467 468 static size_t parport_pc_ecpepp_write_data (struct parport *port, 469 const void *buf, size_t length, 470 int flags) 471 { 472 size_t written; 473 474 frob_set_mode (port, ECR_EPP); 475 parport_pc_write_control (port, 0x4); 476 parport_pc_data_forward (port); 477 written = parport_pc_epp_write_data (port, buf, length, flags); 478 frob_set_mode (port, ECR_PS2); 479 480 return written; 481 } 482 483 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf, 484 size_t length, int flags) 485 { 486 size_t got; 487 488 frob_set_mode (port, ECR_EPP); 489 parport_pc_data_reverse (port); 490 parport_pc_write_control (port, 0x4); 491 got = parport_pc_epp_read_addr (port, buf, length, flags); 492 frob_set_mode (port, ECR_PS2); 493 494 return got; 495 } 496 497 static size_t parport_pc_ecpepp_write_addr (struct parport *port, 498 const void *buf, size_t length, 499 int flags) 500 { 501 size_t written; 502 503 frob_set_mode (port, ECR_EPP); 504 parport_pc_write_control (port, 0x4); 505 parport_pc_data_forward (port); 506 written = parport_pc_epp_write_addr (port, buf, length, flags); 507 frob_set_mode (port, ECR_PS2); 508 509 return written; 510 } 511 #endif /* IEEE 1284 support */ 512 513 #ifdef CONFIG_PARPORT_PC_FIFO 514 static size_t parport_pc_fifo_write_block_pio (struct parport *port, 515 const void *buf, size_t length) 516 { 517 int ret = 0; 518 const unsigned char *bufp = buf; 519 size_t left = length; 520 unsigned long expire = jiffies + port->physport->cad->timeout; 521 const int fifo = FIFO (port); 522 int poll_for = 8; /* 80 usecs */ 523 const struct parport_pc_private *priv = port->physport->private_data; 524 const int fifo_depth = priv->fifo_depth; 525 526 port = port->physport; 527 528 /* We don't want to be interrupted every character. */ 529 parport_pc_disable_irq (port); 530 /* set nErrIntrEn and serviceIntr */ 531 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 532 533 /* Forward mode. */ 534 parport_pc_data_forward (port); /* Must be in PS2 mode */ 535 536 while (left) { 537 unsigned char byte; 538 unsigned char ecrval = inb (ECONTROL (port)); 539 int i = 0; 540 541 if (need_resched() && time_before (jiffies, expire)) 542 /* Can't yield the port. */ 543 schedule (); 544 545 /* Anyone else waiting for the port? */ 546 if (port->waithead) { 547 printk (KERN_DEBUG "Somebody wants the port\n"); 548 break; 549 } 550 551 if (ecrval & 0x02) { 552 /* FIFO is full. Wait for interrupt. */ 553 554 /* Clear serviceIntr */ 555 ECR_WRITE (port, ecrval & ~(1<<2)); 556 false_alarm: 557 ret = parport_wait_event (port, HZ); 558 if (ret < 0) break; 559 ret = 0; 560 if (!time_before (jiffies, expire)) { 561 /* Timed out. */ 562 printk (KERN_DEBUG "FIFO write timed out\n"); 563 break; 564 } 565 ecrval = inb (ECONTROL (port)); 566 if (!(ecrval & (1<<2))) { 567 if (need_resched() && 568 time_before (jiffies, expire)) 569 schedule (); 570 571 goto false_alarm; 572 } 573 574 continue; 575 } 576 577 /* Can't fail now. */ 578 expire = jiffies + port->cad->timeout; 579 580 poll: 581 if (signal_pending (current)) 582 break; 583 584 if (ecrval & 0x01) { 585 /* FIFO is empty. Blast it full. */ 586 const int n = left < fifo_depth ? left : fifo_depth; 587 outsb (fifo, bufp, n); 588 bufp += n; 589 left -= n; 590 591 /* Adjust the poll time. */ 592 if (i < (poll_for - 2)) poll_for--; 593 continue; 594 } else if (i++ < poll_for) { 595 udelay (10); 596 ecrval = inb (ECONTROL (port)); 597 goto poll; 598 } 599 600 /* Half-full (call me an optimist) */ 601 byte = *bufp++; 602 outb (byte, fifo); 603 left--; 604 } 605 606 dump_parport_state ("leave fifo_write_block_pio", port); 607 return length - left; 608 } 609 610 #ifdef HAS_DMA 611 static size_t parport_pc_fifo_write_block_dma (struct parport *port, 612 const void *buf, size_t length) 613 { 614 int ret = 0; 615 unsigned long dmaflag; 616 size_t left = length; 617 const struct parport_pc_private *priv = port->physport->private_data; 618 struct device *dev = port->physport->dev; 619 dma_addr_t dma_addr, dma_handle; 620 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ 621 unsigned long start = (unsigned long) buf; 622 unsigned long end = (unsigned long) buf + length - 1; 623 624 dump_parport_state ("enter fifo_write_block_dma", port); 625 if (end < MAX_DMA_ADDRESS) { 626 /* If it would cross a 64k boundary, cap it at the end. */ 627 if ((start ^ end) & ~0xffffUL) 628 maxlen = 0x10000 - (start & 0xffff); 629 630 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length, 631 DMA_TO_DEVICE); 632 } else { 633 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */ 634 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */ 635 dma_addr = priv->dma_handle; 636 dma_handle = 0; 637 } 638 639 port = port->physport; 640 641 /* We don't want to be interrupted every character. */ 642 parport_pc_disable_irq (port); 643 /* set nErrIntrEn and serviceIntr */ 644 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2)); 645 646 /* Forward mode. */ 647 parport_pc_data_forward (port); /* Must be in PS2 mode */ 648 649 while (left) { 650 unsigned long expire = jiffies + port->physport->cad->timeout; 651 652 size_t count = left; 653 654 if (count > maxlen) 655 count = maxlen; 656 657 if (!dma_handle) /* bounce buffer ! */ 658 memcpy(priv->dma_buf, buf, count); 659 660 dmaflag = claim_dma_lock(); 661 disable_dma(port->dma); 662 clear_dma_ff(port->dma); 663 set_dma_mode(port->dma, DMA_MODE_WRITE); 664 set_dma_addr(port->dma, dma_addr); 665 set_dma_count(port->dma, count); 666 667 /* Set DMA mode */ 668 frob_econtrol (port, 1<<3, 1<<3); 669 670 /* Clear serviceIntr */ 671 frob_econtrol (port, 1<<2, 0); 672 673 enable_dma(port->dma); 674 release_dma_lock(dmaflag); 675 676 /* assume DMA will be successful */ 677 left -= count; 678 buf += count; 679 if (dma_handle) dma_addr += count; 680 681 /* Wait for interrupt. */ 682 false_alarm: 683 ret = parport_wait_event (port, HZ); 684 if (ret < 0) break; 685 ret = 0; 686 if (!time_before (jiffies, expire)) { 687 /* Timed out. */ 688 printk (KERN_DEBUG "DMA write timed out\n"); 689 break; 690 } 691 /* Is serviceIntr set? */ 692 if (!(inb (ECONTROL (port)) & (1<<2))) { 693 cond_resched(); 694 695 goto false_alarm; 696 } 697 698 dmaflag = claim_dma_lock(); 699 disable_dma(port->dma); 700 clear_dma_ff(port->dma); 701 count = get_dma_residue(port->dma); 702 release_dma_lock(dmaflag); 703 704 cond_resched(); /* Can't yield the port. */ 705 706 /* Anyone else waiting for the port? */ 707 if (port->waithead) { 708 printk (KERN_DEBUG "Somebody wants the port\n"); 709 break; 710 } 711 712 /* update for possible DMA residue ! */ 713 buf -= count; 714 left += count; 715 if (dma_handle) dma_addr -= count; 716 } 717 718 /* Maybe got here through break, so adjust for DMA residue! */ 719 dmaflag = claim_dma_lock(); 720 disable_dma(port->dma); 721 clear_dma_ff(port->dma); 722 left += get_dma_residue(port->dma); 723 release_dma_lock(dmaflag); 724 725 /* Turn off DMA mode */ 726 frob_econtrol (port, 1<<3, 0); 727 728 if (dma_handle) 729 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE); 730 731 dump_parport_state ("leave fifo_write_block_dma", port); 732 return length - left; 733 } 734 #endif 735 736 static inline size_t parport_pc_fifo_write_block(struct parport *port, 737 const void *buf, size_t length) 738 { 739 #ifdef HAS_DMA 740 if (port->dma != PARPORT_DMA_NONE) 741 return parport_pc_fifo_write_block_dma (port, buf, length); 742 #endif 743 return parport_pc_fifo_write_block_pio (port, buf, length); 744 } 745 746 /* Parallel Port FIFO mode (ECP chipsets) */ 747 static size_t parport_pc_compat_write_block_pio (struct parport *port, 748 const void *buf, size_t length, 749 int flags) 750 { 751 size_t written; 752 int r; 753 unsigned long expire; 754 const struct parport_pc_private *priv = port->physport->private_data; 755 756 /* Special case: a timeout of zero means we cannot call schedule(). 757 * Also if O_NONBLOCK is set then use the default implementation. */ 758 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 759 return parport_ieee1284_write_compat (port, buf, 760 length, flags); 761 762 /* Set up parallel port FIFO mode.*/ 763 parport_pc_data_forward (port); /* Must be in PS2 mode */ 764 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0); 765 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */ 766 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name); 767 768 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 769 770 /* Write the data to the FIFO. */ 771 written = parport_pc_fifo_write_block(port, buf, length); 772 773 /* Finish up. */ 774 /* For some hardware we don't want to touch the mode until 775 * the FIFO is empty, so allow 4 seconds for each position 776 * in the fifo. 777 */ 778 expire = jiffies + (priv->fifo_depth * HZ * 4); 779 do { 780 /* Wait for the FIFO to empty */ 781 r = change_mode (port, ECR_PS2); 782 if (r != -EBUSY) { 783 break; 784 } 785 } while (time_before (jiffies, expire)); 786 if (r == -EBUSY) { 787 788 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 789 790 /* Prevent further data transfer. */ 791 frob_set_mode (port, ECR_TST); 792 793 /* Adjust for the contents of the FIFO. */ 794 for (written -= priv->fifo_depth; ; written++) { 795 if (inb (ECONTROL (port)) & 0x2) { 796 /* Full up. */ 797 break; 798 } 799 outb (0, FIFO (port)); 800 } 801 802 /* Reset the FIFO and return to PS2 mode. */ 803 frob_set_mode (port, ECR_PS2); 804 } 805 806 r = parport_wait_peripheral (port, 807 PARPORT_STATUS_BUSY, 808 PARPORT_STATUS_BUSY); 809 if (r) 810 printk (KERN_DEBUG 811 "%s: BUSY timeout (%d) in compat_write_block_pio\n", 812 port->name, r); 813 814 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 815 816 return written; 817 } 818 819 /* ECP */ 820 #ifdef CONFIG_PARPORT_1284 821 static size_t parport_pc_ecp_write_block_pio (struct parport *port, 822 const void *buf, size_t length, 823 int flags) 824 { 825 size_t written; 826 int r; 827 unsigned long expire; 828 const struct parport_pc_private *priv = port->physport->private_data; 829 830 /* Special case: a timeout of zero means we cannot call schedule(). 831 * Also if O_NONBLOCK is set then use the default implementation. */ 832 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 833 return parport_ieee1284_ecp_write_data (port, buf, 834 length, flags); 835 836 /* Switch to forward mode if necessary. */ 837 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 838 /* Event 47: Set nInit high. */ 839 parport_frob_control (port, 840 PARPORT_CONTROL_INIT 841 | PARPORT_CONTROL_AUTOFD, 842 PARPORT_CONTROL_INIT 843 | PARPORT_CONTROL_AUTOFD); 844 845 /* Event 49: PError goes high. */ 846 r = parport_wait_peripheral (port, 847 PARPORT_STATUS_PAPEROUT, 848 PARPORT_STATUS_PAPEROUT); 849 if (r) { 850 printk (KERN_DEBUG "%s: PError timeout (%d) " 851 "in ecp_write_block_pio\n", port->name, r); 852 } 853 } 854 855 /* Set up ECP parallel port mode.*/ 856 parport_pc_data_forward (port); /* Must be in PS2 mode */ 857 parport_pc_frob_control (port, 858 PARPORT_CONTROL_STROBE | 859 PARPORT_CONTROL_AUTOFD, 860 0); 861 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 862 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 863 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 864 865 /* Write the data to the FIFO. */ 866 written = parport_pc_fifo_write_block(port, buf, length); 867 868 /* Finish up. */ 869 /* For some hardware we don't want to touch the mode until 870 * the FIFO is empty, so allow 4 seconds for each position 871 * in the fifo. 872 */ 873 expire = jiffies + (priv->fifo_depth * (HZ * 4)); 874 do { 875 /* Wait for the FIFO to empty */ 876 r = change_mode (port, ECR_PS2); 877 if (r != -EBUSY) { 878 break; 879 } 880 } while (time_before (jiffies, expire)); 881 if (r == -EBUSY) { 882 883 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name); 884 885 /* Prevent further data transfer. */ 886 frob_set_mode (port, ECR_TST); 887 888 /* Adjust for the contents of the FIFO. */ 889 for (written -= priv->fifo_depth; ; written++) { 890 if (inb (ECONTROL (port)) & 0x2) { 891 /* Full up. */ 892 break; 893 } 894 outb (0, FIFO (port)); 895 } 896 897 /* Reset the FIFO and return to PS2 mode. */ 898 frob_set_mode (port, ECR_PS2); 899 900 /* Host transfer recovery. */ 901 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 902 udelay (5); 903 parport_frob_control (port, PARPORT_CONTROL_INIT, 0); 904 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 905 if (r) 906 printk (KERN_DEBUG "%s: PE,1 timeout (%d) " 907 "in ecp_write_block_pio\n", port->name, r); 908 909 parport_frob_control (port, 910 PARPORT_CONTROL_INIT, 911 PARPORT_CONTROL_INIT); 912 r = parport_wait_peripheral (port, 913 PARPORT_STATUS_PAPEROUT, 914 PARPORT_STATUS_PAPEROUT); 915 if (r) 916 printk (KERN_DEBUG "%s: PE,2 timeout (%d) " 917 "in ecp_write_block_pio\n", port->name, r); 918 } 919 920 r = parport_wait_peripheral (port, 921 PARPORT_STATUS_BUSY, 922 PARPORT_STATUS_BUSY); 923 if(r) 924 printk (KERN_DEBUG 925 "%s: BUSY timeout (%d) in ecp_write_block_pio\n", 926 port->name, r); 927 928 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 929 930 return written; 931 } 932 933 #if 0 934 static size_t parport_pc_ecp_read_block_pio (struct parport *port, 935 void *buf, size_t length, 936 int flags) 937 { 938 size_t left = length; 939 size_t fifofull; 940 int r; 941 const int fifo = FIFO(port); 942 const struct parport_pc_private *priv = port->physport->private_data; 943 const int fifo_depth = priv->fifo_depth; 944 char *bufp = buf; 945 946 port = port->physport; 947 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n"); 948 dump_parport_state ("enter fcn", port); 949 950 /* Special case: a timeout of zero means we cannot call schedule(). 951 * Also if O_NONBLOCK is set then use the default implementation. */ 952 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 953 return parport_ieee1284_ecp_read_data (port, buf, 954 length, flags); 955 956 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) { 957 /* If the peripheral is allowed to send RLE compressed 958 * data, it is possible for a byte to expand to 128 959 * bytes in the FIFO. */ 960 fifofull = 128; 961 } else { 962 fifofull = fifo_depth; 963 } 964 965 /* If the caller wants less than a full FIFO's worth of data, 966 * go through software emulation. Otherwise we may have to throw 967 * away data. */ 968 if (length < fifofull) 969 return parport_ieee1284_ecp_read_data (port, buf, 970 length, flags); 971 972 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) { 973 /* change to reverse-idle phase (must be in forward-idle) */ 974 975 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */ 976 parport_frob_control (port, 977 PARPORT_CONTROL_AUTOFD 978 | PARPORT_CONTROL_STROBE, 979 PARPORT_CONTROL_AUTOFD); 980 parport_pc_data_reverse (port); /* Must be in PS2 mode */ 981 udelay (5); 982 /* Event 39: Set nInit low to initiate bus reversal */ 983 parport_frob_control (port, 984 PARPORT_CONTROL_INIT, 985 0); 986 /* Event 40: Wait for nAckReverse (PError) to go low */ 987 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0); 988 if (r) { 989 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) " 990 "in ecp_read_block_pio\n", port->name, r); 991 return 0; 992 } 993 } 994 995 /* Set up ECP FIFO mode.*/ 996 /* parport_pc_frob_control (port, 997 PARPORT_CONTROL_STROBE | 998 PARPORT_CONTROL_AUTOFD, 999 PARPORT_CONTROL_AUTOFD); */ 1000 r = change_mode (port, ECR_ECP); /* ECP FIFO */ 1001 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name); 1002 1003 port->ieee1284.phase = IEEE1284_PH_REV_DATA; 1004 1005 /* the first byte must be collected manually */ 1006 dump_parport_state ("pre 43", port); 1007 /* Event 43: Wait for nAck to go low */ 1008 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); 1009 if (r) { 1010 /* timed out while reading -- no data */ 1011 printk (KERN_DEBUG "PIO read timed out (initial byte)\n"); 1012 goto out_no_data; 1013 } 1014 /* read byte */ 1015 *bufp++ = inb (DATA (port)); 1016 left--; 1017 dump_parport_state ("43-44", port); 1018 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */ 1019 parport_pc_frob_control (port, 1020 PARPORT_CONTROL_AUTOFD, 1021 0); 1022 dump_parport_state ("pre 45", port); 1023 /* Event 45: Wait for nAck to go high */ 1024 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */ 1025 dump_parport_state ("post 45", port); 1026 r = 0; 1027 if (r) { 1028 /* timed out while waiting for peripheral to respond to ack */ 1029 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n"); 1030 1031 /* keep hold of the byte we've got already */ 1032 goto out_no_data; 1033 } 1034 /* Event 46: nAutoFd (HostAck) goes low to accept more data */ 1035 parport_pc_frob_control (port, 1036 PARPORT_CONTROL_AUTOFD, 1037 PARPORT_CONTROL_AUTOFD); 1038 1039 1040 dump_parport_state ("rev idle", port); 1041 /* Do the transfer. */ 1042 while (left > fifofull) { 1043 int ret; 1044 unsigned long expire = jiffies + port->cad->timeout; 1045 unsigned char ecrval = inb (ECONTROL (port)); 1046 1047 if (need_resched() && time_before (jiffies, expire)) 1048 /* Can't yield the port. */ 1049 schedule (); 1050 1051 /* At this point, the FIFO may already be full. In 1052 * that case ECP is already holding back the 1053 * peripheral (assuming proper design) with a delayed 1054 * handshake. Work fast to avoid a peripheral 1055 * timeout. */ 1056 1057 if (ecrval & 0x01) { 1058 /* FIFO is empty. Wait for interrupt. */ 1059 dump_parport_state ("FIFO empty", port); 1060 1061 /* Anyone else waiting for the port? */ 1062 if (port->waithead) { 1063 printk (KERN_DEBUG "Somebody wants the port\n"); 1064 break; 1065 } 1066 1067 /* Clear serviceIntr */ 1068 ECR_WRITE (port, ecrval & ~(1<<2)); 1069 false_alarm: 1070 dump_parport_state ("waiting", port); 1071 ret = parport_wait_event (port, HZ); 1072 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret); 1073 if (ret < 0) 1074 break; 1075 ret = 0; 1076 if (!time_before (jiffies, expire)) { 1077 /* Timed out. */ 1078 dump_parport_state ("timeout", port); 1079 printk (KERN_DEBUG "PIO read timed out\n"); 1080 break; 1081 } 1082 ecrval = inb (ECONTROL (port)); 1083 if (!(ecrval & (1<<2))) { 1084 if (need_resched() && 1085 time_before (jiffies, expire)) { 1086 schedule (); 1087 } 1088 goto false_alarm; 1089 } 1090 1091 /* Depending on how the FIFO threshold was 1092 * set, how long interrupt service took, and 1093 * how fast the peripheral is, we might be 1094 * lucky and have a just filled FIFO. */ 1095 continue; 1096 } 1097 1098 if (ecrval & 0x02) { 1099 /* FIFO is full. */ 1100 dump_parport_state ("FIFO full", port); 1101 insb (fifo, bufp, fifo_depth); 1102 bufp += fifo_depth; 1103 left -= fifo_depth; 1104 continue; 1105 } 1106 1107 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n"); 1108 1109 /* FIFO not filled. We will cycle this loop for a while 1110 * and either the peripheral will fill it faster, 1111 * tripping a fast empty with insb, or we empty it. */ 1112 *bufp++ = inb (fifo); 1113 left--; 1114 } 1115 1116 /* scoop up anything left in the FIFO */ 1117 while (left && !(inb (ECONTROL (port) & 0x01))) { 1118 *bufp++ = inb (fifo); 1119 left--; 1120 } 1121 1122 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; 1123 dump_parport_state ("rev idle2", port); 1124 1125 out_no_data: 1126 1127 /* Go to forward idle mode to shut the peripheral up (event 47). */ 1128 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); 1129 1130 /* event 49: PError goes high */ 1131 r = parport_wait_peripheral (port, 1132 PARPORT_STATUS_PAPEROUT, 1133 PARPORT_STATUS_PAPEROUT); 1134 if (r) { 1135 printk (KERN_DEBUG 1136 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n", 1137 port->name, r); 1138 } 1139 1140 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1141 1142 /* Finish up. */ 1143 { 1144 int lost = get_fifo_residue (port); 1145 if (lost) 1146 /* Shouldn't happen with compliant peripherals. */ 1147 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n", 1148 port->name, lost); 1149 } 1150 1151 dump_parport_state ("fwd idle", port); 1152 return length - left; 1153 } 1154 #endif /* 0 */ 1155 #endif /* IEEE 1284 support */ 1156 #endif /* Allowed to use FIFO/DMA */ 1157 1158 1159 /* 1160 * ****************************************** 1161 * INITIALISATION AND MODULE STUFF BELOW HERE 1162 * ****************************************** 1163 */ 1164 1165 /* GCC is not inlining extern inline function later overwriten to non-inline, 1166 so we use outlined_ variants here. */ 1167 static const struct parport_operations parport_pc_ops = 1168 { 1169 .write_data = parport_pc_write_data, 1170 .read_data = parport_pc_read_data, 1171 1172 .write_control = parport_pc_write_control, 1173 .read_control = parport_pc_read_control, 1174 .frob_control = parport_pc_frob_control, 1175 1176 .read_status = parport_pc_read_status, 1177 1178 .enable_irq = parport_pc_enable_irq, 1179 .disable_irq = parport_pc_disable_irq, 1180 1181 .data_forward = parport_pc_data_forward, 1182 .data_reverse = parport_pc_data_reverse, 1183 1184 .init_state = parport_pc_init_state, 1185 .save_state = parport_pc_save_state, 1186 .restore_state = parport_pc_restore_state, 1187 1188 .epp_write_data = parport_ieee1284_epp_write_data, 1189 .epp_read_data = parport_ieee1284_epp_read_data, 1190 .epp_write_addr = parport_ieee1284_epp_write_addr, 1191 .epp_read_addr = parport_ieee1284_epp_read_addr, 1192 1193 .ecp_write_data = parport_ieee1284_ecp_write_data, 1194 .ecp_read_data = parport_ieee1284_ecp_read_data, 1195 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1196 1197 .compat_write_data = parport_ieee1284_write_compat, 1198 .nibble_read_data = parport_ieee1284_read_nibble, 1199 .byte_read_data = parport_ieee1284_read_byte, 1200 1201 .owner = THIS_MODULE, 1202 }; 1203 1204 #ifdef CONFIG_PARPORT_PC_SUPERIO 1205 /* Super-IO chipset detection, Winbond, SMSC */ 1206 static void __devinit show_parconfig_smsc37c669(int io, int key) 1207 { 1208 int cr1,cr4,cra,cr23,cr26,cr27,i=0; 1209 static const char *const modes[]={ 1210 "SPP and Bidirectional (PS/2)", 1211 "EPP and SPP", 1212 "ECP", 1213 "ECP and EPP" }; 1214 1215 outb(key,io); 1216 outb(key,io); 1217 outb(1,io); 1218 cr1=inb(io+1); 1219 outb(4,io); 1220 cr4=inb(io+1); 1221 outb(0x0a,io); 1222 cra=inb(io+1); 1223 outb(0x23,io); 1224 cr23=inb(io+1); 1225 outb(0x26,io); 1226 cr26=inb(io+1); 1227 outb(0x27,io); 1228 cr27=inb(io+1); 1229 outb(0xaa,io); 1230 1231 if (verbose_probing) { 1232 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " 1233 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", 1234 cr1,cr4,cra,cr23,cr26,cr27); 1235 1236 /* The documentation calls DMA and IRQ-Lines by letters, so 1237 the board maker can/will wire them 1238 appropriately/randomly... G=reserved H=IDE-irq, */ 1239 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, " 1240 "fifo threshold=%d\n", cr23*4, 1241 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-', 1242 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f); 1243 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", 1244 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no"); 1245 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n", 1246 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03], 1247 (cr4 & 0x40) ? "1.7" : "1.9"); 1248 } 1249 1250 /* Heuristics ! BIOS setup for this mainboard device limits 1251 the choices to standard settings, i.e. io-address and IRQ 1252 are related, however DMA can be 1 or 3, assume DMA_A=DMA1, 1253 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */ 1254 if(cr23*4 >=0x100) { /* if active */ 1255 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1256 i++; 1257 if(i==NR_SUPERIOS) 1258 printk(KERN_INFO "Super-IO: too many chips!\n"); 1259 else { 1260 int d; 1261 switch (cr23*4) { 1262 case 0x3bc: 1263 superios[i].io = 0x3bc; 1264 superios[i].irq = 7; 1265 break; 1266 case 0x378: 1267 superios[i].io = 0x378; 1268 superios[i].irq = 7; 1269 break; 1270 case 0x278: 1271 superios[i].io = 0x278; 1272 superios[i].irq = 5; 1273 } 1274 d=(cr26 &0x0f); 1275 if((d==1) || (d==3)) 1276 superios[i].dma= d; 1277 else 1278 superios[i].dma= PARPORT_DMA_NONE; 1279 } 1280 } 1281 } 1282 1283 1284 static void __devinit show_parconfig_winbond(int io, int key) 1285 { 1286 int cr30,cr60,cr61,cr70,cr74,crf0,i=0; 1287 static const char *const modes[] = { 1288 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ 1289 "EPP-1.9 and SPP", 1290 "ECP", 1291 "ECP and EPP-1.9", 1292 "Standard (SPP)", 1293 "EPP-1.7 and SPP", /* 5 */ 1294 "undefined!", 1295 "ECP and EPP-1.7" }; 1296 static char *const irqtypes[] = { 1297 "pulsed low, high-Z", 1298 "follows nACK" }; 1299 1300 /* The registers are called compatible-PnP because the 1301 register layout is modelled after ISA-PnP, the access 1302 method is just another ... */ 1303 outb(key,io); 1304 outb(key,io); 1305 outb(0x07,io); /* Register 7: Select Logical Device */ 1306 outb(0x01,io+1); /* LD1 is Parallel Port */ 1307 outb(0x30,io); 1308 cr30=inb(io+1); 1309 outb(0x60,io); 1310 cr60=inb(io+1); 1311 outb(0x61,io); 1312 cr61=inb(io+1); 1313 outb(0x70,io); 1314 cr70=inb(io+1); 1315 outb(0x74,io); 1316 cr74=inb(io+1); 1317 outb(0xf0,io); 1318 crf0=inb(io+1); 1319 outb(0xaa,io); 1320 1321 if (verbose_probing) { 1322 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x " 1323 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0); 1324 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", 1325 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f ); 1326 if ((cr74 & 0x07) > 3) 1327 printk("dma=none\n"); 1328 else 1329 printk("dma=%d\n",cr74 & 0x07); 1330 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", 1331 irqtypes[crf0>>7], (crf0>>3)&0x0f); 1332 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]); 1333 } 1334 1335 if(cr30 & 0x01) { /* the settings can be interrogated later ... */ 1336 while((superios[i].io!= 0) && (i<NR_SUPERIOS)) 1337 i++; 1338 if(i==NR_SUPERIOS) 1339 printk(KERN_INFO "Super-IO: too many chips!\n"); 1340 else { 1341 superios[i].io = (cr60<<8)|cr61; 1342 superios[i].irq = cr70&0x0f; 1343 superios[i].dma = (((cr74 & 0x07) > 3) ? 1344 PARPORT_DMA_NONE : (cr74 & 0x07)); 1345 } 1346 } 1347 } 1348 1349 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid) 1350 { 1351 const char *type = "unknown"; 1352 int id,progif=2; 1353 1354 if (devid == devrev) 1355 /* simple heuristics, we happened to read some 1356 non-winbond register */ 1357 return; 1358 1359 id=(devid<<8) | devrev; 1360 1361 /* Values are from public data sheets pdf files, I can just 1362 confirm 83977TF is correct :-) */ 1363 if (id == 0x9771) type="83977F/AF"; 1364 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x"; 1365 else if (id == 0x9774) type="83977ATF"; 1366 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x"; 1367 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x"; 1368 else if ((id & ~0x0f) == 0x5210) type="83627"; 1369 else if ((id & ~0x0f) == 0x6010) type="83697HF"; 1370 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;} 1371 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;} 1372 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;} 1373 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;} 1374 else progif=0; 1375 1376 if (verbose_probing) 1377 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " 1378 "devid=%02x devrev=%02x oldid=%02x type=%s\n", 1379 efer, key, devid, devrev, oldid, type); 1380 1381 if (progif == 2) 1382 show_parconfig_winbond(efer,key); 1383 } 1384 1385 static void __devinit decode_smsc(int efer, int key, int devid, int devrev) 1386 { 1387 const char *type = "unknown"; 1388 void (*func)(int io, int key); 1389 int id; 1390 1391 if (devid == devrev) 1392 /* simple heuristics, we happened to read some 1393 non-smsc register */ 1394 return; 1395 1396 func=NULL; 1397 id=(devid<<8) | devrev; 1398 1399 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;} 1400 else if (id==0x6582) type="37c665IR"; 1401 else if (devid==0x65) type="37c665GT"; 1402 else if (devid==0x66) type="37c666GT"; 1403 1404 if (verbose_probing) 1405 printk(KERN_INFO "SMSC chip at EFER=0x%x " 1406 "key=0x%02x devid=%02x devrev=%02x type=%s\n", 1407 efer, key, devid, devrev, type); 1408 1409 if (func) 1410 func(efer,key); 1411 } 1412 1413 1414 static void __devinit winbond_check(int io, int key) 1415 { 1416 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1417 1418 if (!request_region(io, 3, __FUNCTION__)) 1419 return; 1420 1421 /* First probe without key */ 1422 outb(0x20,io); 1423 x_devid=inb(io+1); 1424 outb(0x21,io); 1425 x_devrev=inb(io+1); 1426 outb(0x09,io); 1427 x_oldid=inb(io+1); 1428 1429 outb(key,io); 1430 outb(key,io); /* Write Magic Sequence to EFER, extended 1431 funtion enable register */ 1432 outb(0x20,io); /* Write EFIR, extended function index register */ 1433 devid=inb(io+1); /* Read EFDR, extended function data register */ 1434 outb(0x21,io); 1435 devrev=inb(io+1); 1436 outb(0x09,io); 1437 oldid=inb(io+1); 1438 outb(0xaa,io); /* Magic Seal */ 1439 1440 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1441 goto out; /* protection against false positives */ 1442 1443 decode_winbond(io,key,devid,devrev,oldid); 1444 out: 1445 release_region(io, 3); 1446 } 1447 1448 static void __devinit winbond_check2(int io,int key) 1449 { 1450 int devid,devrev,oldid,x_devid,x_devrev,x_oldid; 1451 1452 if (!request_region(io, 3, __FUNCTION__)) 1453 return; 1454 1455 /* First probe without the key */ 1456 outb(0x20,io+2); 1457 x_devid=inb(io+2); 1458 outb(0x21,io+1); 1459 x_devrev=inb(io+2); 1460 outb(0x09,io+1); 1461 x_oldid=inb(io+2); 1462 1463 outb(key,io); /* Write Magic Byte to EFER, extended 1464 funtion enable register */ 1465 outb(0x20,io+2); /* Write EFIR, extended function index register */ 1466 devid=inb(io+2); /* Read EFDR, extended function data register */ 1467 outb(0x21,io+1); 1468 devrev=inb(io+2); 1469 outb(0x09,io+1); 1470 oldid=inb(io+2); 1471 outb(0xaa,io); /* Magic Seal */ 1472 1473 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid)) 1474 goto out; /* protection against false positives */ 1475 1476 decode_winbond(io,key,devid,devrev,oldid); 1477 out: 1478 release_region(io, 3); 1479 } 1480 1481 static void __devinit smsc_check(int io, int key) 1482 { 1483 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev; 1484 1485 if (!request_region(io, 3, __FUNCTION__)) 1486 return; 1487 1488 /* First probe without the key */ 1489 outb(0x0d,io); 1490 x_oldid=inb(io+1); 1491 outb(0x0e,io); 1492 x_oldrev=inb(io+1); 1493 outb(0x20,io); 1494 x_id=inb(io+1); 1495 outb(0x21,io); 1496 x_rev=inb(io+1); 1497 1498 outb(key,io); 1499 outb(key,io); /* Write Magic Sequence to EFER, extended 1500 funtion enable register */ 1501 outb(0x0d,io); /* Write EFIR, extended function index register */ 1502 oldid=inb(io+1); /* Read EFDR, extended function data register */ 1503 outb(0x0e,io); 1504 oldrev=inb(io+1); 1505 outb(0x20,io); 1506 id=inb(io+1); 1507 outb(0x21,io); 1508 rev=inb(io+1); 1509 outb(0xaa,io); /* Magic Seal */ 1510 1511 if ((x_id == id) && (x_oldrev == oldrev) && 1512 (x_oldid == oldid) && (x_rev == rev)) 1513 goto out; /* protection against false positives */ 1514 1515 decode_smsc(io,key,oldid,oldrev); 1516 out: 1517 release_region(io, 3); 1518 } 1519 1520 1521 static void __devinit detect_and_report_winbond (void) 1522 { 1523 if (verbose_probing) 1524 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n"); 1525 winbond_check(0x3f0,0x87); 1526 winbond_check(0x370,0x87); 1527 winbond_check(0x2e ,0x87); 1528 winbond_check(0x4e ,0x87); 1529 winbond_check(0x3f0,0x86); 1530 winbond_check2(0x250,0x88); 1531 winbond_check2(0x250,0x89); 1532 } 1533 1534 static void __devinit detect_and_report_smsc (void) 1535 { 1536 if (verbose_probing) 1537 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n"); 1538 smsc_check(0x3f0,0x55); 1539 smsc_check(0x370,0x55); 1540 smsc_check(0x3f0,0x44); 1541 smsc_check(0x370,0x44); 1542 } 1543 #endif /* CONFIG_PARPORT_PC_SUPERIO */ 1544 1545 static int get_superio_dma (struct parport *p) 1546 { 1547 int i=0; 1548 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1549 i++; 1550 if (i!=NR_SUPERIOS) 1551 return superios[i].dma; 1552 return PARPORT_DMA_NONE; 1553 } 1554 1555 static int get_superio_irq (struct parport *p) 1556 { 1557 int i=0; 1558 while( (superios[i].io != p->base) && (i<NR_SUPERIOS)) 1559 i++; 1560 if (i!=NR_SUPERIOS) 1561 return superios[i].irq; 1562 return PARPORT_IRQ_NONE; 1563 } 1564 1565 1566 /* --- Mode detection ------------------------------------- */ 1567 1568 /* 1569 * Checks for port existence, all ports support SPP MODE 1570 * Returns: 1571 * 0 : No parallel port at this address 1572 * PARPORT_MODE_PCSPP : SPP port detected 1573 * (if the user specified an ioport himself, 1574 * this shall always be the case!) 1575 * 1576 */ 1577 static int parport_SPP_supported(struct parport *pb) 1578 { 1579 unsigned char r, w; 1580 1581 /* 1582 * first clear an eventually pending EPP timeout 1583 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset 1584 * that does not even respond to SPP cycles if an EPP 1585 * timeout is pending 1586 */ 1587 clear_epp_timeout(pb); 1588 1589 /* Do a simple read-write test to make sure the port exists. */ 1590 w = 0xc; 1591 outb (w, CONTROL (pb)); 1592 1593 /* Is there a control register that we can read from? Some 1594 * ports don't allow reads, so read_control just returns a 1595 * software copy. Some ports _do_ allow reads, so bypass the 1596 * software copy here. In addition, some bits aren't 1597 * writable. */ 1598 r = inb (CONTROL (pb)); 1599 if ((r & 0xf) == w) { 1600 w = 0xe; 1601 outb (w, CONTROL (pb)); 1602 r = inb (CONTROL (pb)); 1603 outb (0xc, CONTROL (pb)); 1604 if ((r & 0xf) == w) 1605 return PARPORT_MODE_PCSPP; 1606 } 1607 1608 if (user_specified) 1609 /* That didn't work, but the user thinks there's a 1610 * port here. */ 1611 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: " 1612 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1613 1614 /* Try the data register. The data lines aren't tri-stated at 1615 * this stage, so we expect back what we wrote. */ 1616 w = 0xaa; 1617 parport_pc_write_data (pb, w); 1618 r = parport_pc_read_data (pb); 1619 if (r == w) { 1620 w = 0x55; 1621 parport_pc_write_data (pb, w); 1622 r = parport_pc_read_data (pb); 1623 if (r == w) 1624 return PARPORT_MODE_PCSPP; 1625 } 1626 1627 if (user_specified) { 1628 /* Didn't work, but the user is convinced this is the 1629 * place. */ 1630 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: " 1631 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); 1632 printk (KERN_INFO "parport 0x%lx: You gave this address, " 1633 "but there is probably no parallel port there!\n", 1634 pb->base); 1635 } 1636 1637 /* It's possible that we can't read the control register or 1638 * the data register. In that case just believe the user. */ 1639 if (user_specified) 1640 return PARPORT_MODE_PCSPP; 1641 1642 return 0; 1643 } 1644 1645 /* Check for ECR 1646 * 1647 * Old style XT ports alias io ports every 0x400, hence accessing ECR 1648 * on these cards actually accesses the CTR. 1649 * 1650 * Modern cards don't do this but reading from ECR will return 0xff 1651 * regardless of what is written here if the card does NOT support 1652 * ECP. 1653 * 1654 * We first check to see if ECR is the same as CTR. If not, the low 1655 * two bits of ECR aren't writable, so we check by writing ECR and 1656 * reading it back to see if it's what we expect. 1657 */ 1658 static int parport_ECR_present(struct parport *pb) 1659 { 1660 struct parport_pc_private *priv = pb->private_data; 1661 unsigned char r = 0xc; 1662 1663 outb (r, CONTROL (pb)); 1664 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) { 1665 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */ 1666 1667 r = inb (CONTROL (pb)); 1668 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2)) 1669 goto no_reg; /* Sure that no ECR register exists */ 1670 } 1671 1672 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1) 1673 goto no_reg; 1674 1675 ECR_WRITE (pb, 0x34); 1676 if (inb (ECONTROL (pb)) != 0x35) 1677 goto no_reg; 1678 1679 priv->ecr = 1; 1680 outb (0xc, CONTROL (pb)); 1681 1682 /* Go to mode 000 */ 1683 frob_set_mode (pb, ECR_SPP); 1684 1685 return 1; 1686 1687 no_reg: 1688 outb (0xc, CONTROL (pb)); 1689 return 0; 1690 } 1691 1692 #ifdef CONFIG_PARPORT_1284 1693 /* Detect PS/2 support. 1694 * 1695 * Bit 5 (0x20) sets the PS/2 data direction; setting this high 1696 * allows us to read data from the data lines. In theory we would get back 1697 * 0xff but any peripheral attached to the port may drag some or all of the 1698 * lines down to zero. So if we get back anything that isn't the contents 1699 * of the data register we deem PS/2 support to be present. 1700 * 1701 * Some SPP ports have "half PS/2" ability - you can't turn off the line 1702 * drivers, but an external peripheral with sufficiently beefy drivers of 1703 * its own can overpower them and assert its own levels onto the bus, from 1704 * where they can then be read back as normal. Ports with this property 1705 * and the right type of device attached are likely to fail the SPP test, 1706 * (as they will appear to have stuck bits) and so the fact that they might 1707 * be misdetected here is rather academic. 1708 */ 1709 1710 static int parport_PS2_supported(struct parport *pb) 1711 { 1712 int ok = 0; 1713 1714 clear_epp_timeout(pb); 1715 1716 /* try to tri-state the buffer */ 1717 parport_pc_data_reverse (pb); 1718 1719 parport_pc_write_data(pb, 0x55); 1720 if (parport_pc_read_data(pb) != 0x55) ok++; 1721 1722 parport_pc_write_data(pb, 0xaa); 1723 if (parport_pc_read_data(pb) != 0xaa) ok++; 1724 1725 /* cancel input mode */ 1726 parport_pc_data_forward (pb); 1727 1728 if (ok) { 1729 pb->modes |= PARPORT_MODE_TRISTATE; 1730 } else { 1731 struct parport_pc_private *priv = pb->private_data; 1732 priv->ctr_writable &= ~0x20; 1733 } 1734 1735 return ok; 1736 } 1737 1738 #ifdef CONFIG_PARPORT_PC_FIFO 1739 static int __devinit parport_ECP_supported(struct parport *pb) 1740 { 1741 int i; 1742 int config, configb; 1743 int pword; 1744 struct parport_pc_private *priv = pb->private_data; 1745 /* Translate ECP intrLine to ISA irq value */ 1746 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 }; 1747 1748 /* If there is no ECR, we have no hope of supporting ECP. */ 1749 if (!priv->ecr) 1750 return 0; 1751 1752 /* Find out FIFO depth */ 1753 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1754 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */ 1755 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++) 1756 outb (0xaa, FIFO (pb)); 1757 1758 /* 1759 * Using LGS chipset it uses ECR register, but 1760 * it doesn't support ECP or FIFO MODE 1761 */ 1762 if (i == 1024) { 1763 ECR_WRITE (pb, ECR_SPP << 5); 1764 return 0; 1765 } 1766 1767 priv->fifo_depth = i; 1768 if (verbose_probing) 1769 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); 1770 1771 /* Find out writeIntrThreshold */ 1772 frob_econtrol (pb, 1<<2, 1<<2); 1773 frob_econtrol (pb, 1<<2, 0); 1774 for (i = 1; i <= priv->fifo_depth; i++) { 1775 inb (FIFO (pb)); 1776 udelay (50); 1777 if (inb (ECONTROL (pb)) & (1<<2)) 1778 break; 1779 } 1780 1781 if (i <= priv->fifo_depth) { 1782 if (verbose_probing) 1783 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", 1784 pb->base, i); 1785 } else 1786 /* Number of bytes we know we can write if we get an 1787 interrupt. */ 1788 i = 0; 1789 1790 priv->writeIntrThreshold = i; 1791 1792 /* Find out readIntrThreshold */ 1793 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */ 1794 parport_pc_data_reverse (pb); /* Must be in PS2 mode */ 1795 frob_set_mode (pb, ECR_TST); /* Test FIFO */ 1796 frob_econtrol (pb, 1<<2, 1<<2); 1797 frob_econtrol (pb, 1<<2, 0); 1798 for (i = 1; i <= priv->fifo_depth; i++) { 1799 outb (0xaa, FIFO (pb)); 1800 if (inb (ECONTROL (pb)) & (1<<2)) 1801 break; 1802 } 1803 1804 if (i <= priv->fifo_depth) { 1805 if (verbose_probing) 1806 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n", 1807 pb->base, i); 1808 } else 1809 /* Number of bytes we can read if we get an interrupt. */ 1810 i = 0; 1811 1812 priv->readIntrThreshold = i; 1813 1814 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1815 ECR_WRITE (pb, 0xf4); /* Configuration mode */ 1816 config = inb (CONFIGA (pb)); 1817 pword = (config >> 4) & 0x7; 1818 switch (pword) { 1819 case 0: 1820 pword = 2; 1821 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1822 pb->base); 1823 break; 1824 case 2: 1825 pword = 4; 1826 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n", 1827 pb->base); 1828 break; 1829 default: 1830 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n", 1831 pb->base); 1832 /* Assume 1 */ 1833 case 1: 1834 pword = 1; 1835 } 1836 priv->pword = pword; 1837 1838 if (verbose_probing) { 1839 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword); 1840 1841 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, 1842 config & 0x80 ? "Level" : "Pulses"); 1843 1844 configb = inb (CONFIGB (pb)); 1845 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", 1846 pb->base, config, configb); 1847 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); 1848 if ((configb >>3) & 0x07) 1849 printk("%d",intrline[(configb >>3) & 0x07]); 1850 else 1851 printk("<none or set by other means>"); 1852 printk (" dma="); 1853 if( (configb & 0x03 ) == 0x00) 1854 printk("<none or set by other means>\n"); 1855 else 1856 printk("%d\n",configb & 0x07); 1857 } 1858 1859 /* Go back to mode 000 */ 1860 frob_set_mode (pb, ECR_SPP); 1861 1862 return 1; 1863 } 1864 #endif 1865 1866 static int parport_ECPPS2_supported(struct parport *pb) 1867 { 1868 const struct parport_pc_private *priv = pb->private_data; 1869 int result; 1870 unsigned char oecr; 1871 1872 if (!priv->ecr) 1873 return 0; 1874 1875 oecr = inb (ECONTROL (pb)); 1876 ECR_WRITE (pb, ECR_PS2 << 5); 1877 result = parport_PS2_supported(pb); 1878 ECR_WRITE (pb, oecr); 1879 return result; 1880 } 1881 1882 /* EPP mode detection */ 1883 1884 static int parport_EPP_supported(struct parport *pb) 1885 { 1886 const struct parport_pc_private *priv = pb->private_data; 1887 1888 /* 1889 * Theory: 1890 * Bit 0 of STR is the EPP timeout bit, this bit is 0 1891 * when EPP is possible and is set high when an EPP timeout 1892 * occurs (EPP uses the HALT line to stop the CPU while it does 1893 * the byte transfer, an EPP timeout occurs if the attached 1894 * device fails to respond after 10 micro seconds). 1895 * 1896 * This bit is cleared by either reading it (National Semi) 1897 * or writing a 1 to the bit (SMC, UMC, WinBond), others ??? 1898 * This bit is always high in non EPP modes. 1899 */ 1900 1901 /* If EPP timeout bit clear then EPP available */ 1902 if (!clear_epp_timeout(pb)) { 1903 return 0; /* No way to clear timeout */ 1904 } 1905 1906 /* Check for Intel bug. */ 1907 if (priv->ecr) { 1908 unsigned char i; 1909 for (i = 0x00; i < 0x80; i += 0x20) { 1910 ECR_WRITE (pb, i); 1911 if (clear_epp_timeout (pb)) { 1912 /* Phony EPP in ECP. */ 1913 return 0; 1914 } 1915 } 1916 } 1917 1918 pb->modes |= PARPORT_MODE_EPP; 1919 1920 /* Set up access functions to use EPP hardware. */ 1921 pb->ops->epp_read_data = parport_pc_epp_read_data; 1922 pb->ops->epp_write_data = parport_pc_epp_write_data; 1923 pb->ops->epp_read_addr = parport_pc_epp_read_addr; 1924 pb->ops->epp_write_addr = parport_pc_epp_write_addr; 1925 1926 return 1; 1927 } 1928 1929 static int parport_ECPEPP_supported(struct parport *pb) 1930 { 1931 struct parport_pc_private *priv = pb->private_data; 1932 int result; 1933 unsigned char oecr; 1934 1935 if (!priv->ecr) { 1936 return 0; 1937 } 1938 1939 oecr = inb (ECONTROL (pb)); 1940 /* Search for SMC style EPP+ECP mode */ 1941 ECR_WRITE (pb, 0x80); 1942 outb (0x04, CONTROL (pb)); 1943 result = parport_EPP_supported(pb); 1944 1945 ECR_WRITE (pb, oecr); 1946 1947 if (result) { 1948 /* Set up access functions to use ECP+EPP hardware. */ 1949 pb->ops->epp_read_data = parport_pc_ecpepp_read_data; 1950 pb->ops->epp_write_data = parport_pc_ecpepp_write_data; 1951 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr; 1952 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr; 1953 } 1954 1955 return result; 1956 } 1957 1958 #else /* No IEEE 1284 support */ 1959 1960 /* Don't bother probing for modes we know we won't use. */ 1961 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; } 1962 #ifdef CONFIG_PARPORT_PC_FIFO 1963 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; } 1964 #endif 1965 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; } 1966 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;} 1967 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;} 1968 1969 #endif /* No IEEE 1284 support */ 1970 1971 /* --- IRQ detection -------------------------------------- */ 1972 1973 /* Only if supports ECP mode */ 1974 static int programmable_irq_support(struct parport *pb) 1975 { 1976 int irq, intrLine; 1977 unsigned char oecr = inb (ECONTROL (pb)); 1978 static const int lookup[8] = { 1979 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5 1980 }; 1981 1982 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */ 1983 1984 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07; 1985 irq = lookup[intrLine]; 1986 1987 ECR_WRITE (pb, oecr); 1988 return irq; 1989 } 1990 1991 static int irq_probe_ECP(struct parport *pb) 1992 { 1993 int i; 1994 unsigned long irqs; 1995 1996 irqs = probe_irq_on(); 1997 1998 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */ 1999 ECR_WRITE (pb, (ECR_TST << 5) | 0x04); 2000 ECR_WRITE (pb, ECR_TST << 5); 2001 2002 /* If Full FIFO sure that writeIntrThreshold is generated */ 2003 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++) 2004 outb (0xaa, FIFO (pb)); 2005 2006 pb->irq = probe_irq_off(irqs); 2007 ECR_WRITE (pb, ECR_SPP << 5); 2008 2009 if (pb->irq <= 0) 2010 pb->irq = PARPORT_IRQ_NONE; 2011 2012 return pb->irq; 2013 } 2014 2015 /* 2016 * This detection seems that only works in National Semiconductors 2017 * This doesn't work in SMC, LGS, and Winbond 2018 */ 2019 static int irq_probe_EPP(struct parport *pb) 2020 { 2021 #ifndef ADVANCED_DETECT 2022 return PARPORT_IRQ_NONE; 2023 #else 2024 int irqs; 2025 unsigned char oecr; 2026 2027 if (pb->modes & PARPORT_MODE_PCECR) 2028 oecr = inb (ECONTROL (pb)); 2029 2030 irqs = probe_irq_on(); 2031 2032 if (pb->modes & PARPORT_MODE_PCECR) 2033 frob_econtrol (pb, 0x10, 0x10); 2034 2035 clear_epp_timeout(pb); 2036 parport_pc_frob_control (pb, 0x20, 0x20); 2037 parport_pc_frob_control (pb, 0x10, 0x10); 2038 clear_epp_timeout(pb); 2039 2040 /* Device isn't expecting an EPP read 2041 * and generates an IRQ. 2042 */ 2043 parport_pc_read_epp(pb); 2044 udelay(20); 2045 2046 pb->irq = probe_irq_off (irqs); 2047 if (pb->modes & PARPORT_MODE_PCECR) 2048 ECR_WRITE (pb, oecr); 2049 parport_pc_write_control(pb, 0xc); 2050 2051 if (pb->irq <= 0) 2052 pb->irq = PARPORT_IRQ_NONE; 2053 2054 return pb->irq; 2055 #endif /* Advanced detection */ 2056 } 2057 2058 static int irq_probe_SPP(struct parport *pb) 2059 { 2060 /* Don't even try to do this. */ 2061 return PARPORT_IRQ_NONE; 2062 } 2063 2064 /* We will attempt to share interrupt requests since other devices 2065 * such as sound cards and network cards seem to like using the 2066 * printer IRQs. 2067 * 2068 * When ECP is available we can autoprobe for IRQs. 2069 * NOTE: If we can autoprobe it, we can register the IRQ. 2070 */ 2071 static int parport_irq_probe(struct parport *pb) 2072 { 2073 struct parport_pc_private *priv = pb->private_data; 2074 2075 if (priv->ecr) { 2076 pb->irq = programmable_irq_support(pb); 2077 2078 if (pb->irq == PARPORT_IRQ_NONE) 2079 pb->irq = irq_probe_ECP(pb); 2080 } 2081 2082 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr && 2083 (pb->modes & PARPORT_MODE_EPP)) 2084 pb->irq = irq_probe_EPP(pb); 2085 2086 clear_epp_timeout(pb); 2087 2088 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP)) 2089 pb->irq = irq_probe_EPP(pb); 2090 2091 clear_epp_timeout(pb); 2092 2093 if (pb->irq == PARPORT_IRQ_NONE) 2094 pb->irq = irq_probe_SPP(pb); 2095 2096 if (pb->irq == PARPORT_IRQ_NONE) 2097 pb->irq = get_superio_irq(pb); 2098 2099 return pb->irq; 2100 } 2101 2102 /* --- DMA detection -------------------------------------- */ 2103 2104 /* Only if chipset conforms to ECP ISA Interface Standard */ 2105 static int programmable_dma_support (struct parport *p) 2106 { 2107 unsigned char oecr = inb (ECONTROL (p)); 2108 int dma; 2109 2110 frob_set_mode (p, ECR_CNF); 2111 2112 dma = inb (CONFIGB(p)) & 0x07; 2113 /* 000: Indicates jumpered 8-bit DMA if read-only. 2114 100: Indicates jumpered 16-bit DMA if read-only. */ 2115 if ((dma & 0x03) == 0) 2116 dma = PARPORT_DMA_NONE; 2117 2118 ECR_WRITE (p, oecr); 2119 return dma; 2120 } 2121 2122 static int parport_dma_probe (struct parport *p) 2123 { 2124 const struct parport_pc_private *priv = p->private_data; 2125 if (priv->ecr) 2126 p->dma = programmable_dma_support(p); /* ask ECP chipset first */ 2127 if (p->dma == PARPORT_DMA_NONE) { 2128 /* ask known Super-IO chips proper, although these 2129 claim ECP compatible, some don't report their DMA 2130 conforming to ECP standards */ 2131 p->dma = get_superio_dma(p); 2132 } 2133 2134 return p->dma; 2135 } 2136 2137 /* --- Initialisation code -------------------------------- */ 2138 2139 static LIST_HEAD(ports_list); 2140 static DEFINE_SPINLOCK(ports_lock); 2141 2142 struct parport *parport_pc_probe_port (unsigned long int base, 2143 unsigned long int base_hi, 2144 int irq, int dma, 2145 struct device *dev) 2146 { 2147 struct parport_pc_private *priv; 2148 struct parport_operations *ops; 2149 struct parport *p; 2150 int probedirq = PARPORT_IRQ_NONE; 2151 struct resource *base_res; 2152 struct resource *ECR_res = NULL; 2153 struct resource *EPP_res = NULL; 2154 struct platform_device *pdev = NULL; 2155 2156 if (!dev) { 2157 /* We need a physical device to attach to, but none was 2158 * provided. Create our own. */ 2159 pdev = platform_device_register_simple("parport_pc", 2160 base, NULL, 0); 2161 if (IS_ERR(pdev)) 2162 return NULL; 2163 dev = &pdev->dev; 2164 } 2165 2166 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL); 2167 if (!ops) 2168 goto out1; 2169 2170 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL); 2171 if (!priv) 2172 goto out2; 2173 2174 /* a misnomer, actually - it's allocate and reserve parport number */ 2175 p = parport_register_port(base, irq, dma, ops); 2176 if (!p) 2177 goto out3; 2178 2179 base_res = request_region(base, 3, p->name); 2180 if (!base_res) 2181 goto out4; 2182 2183 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations)); 2184 priv->ctr = 0xc; 2185 priv->ctr_writable = ~0x10; 2186 priv->ecr = 0; 2187 priv->fifo_depth = 0; 2188 priv->dma_buf = NULL; 2189 priv->dma_handle = 0; 2190 INIT_LIST_HEAD(&priv->list); 2191 priv->port = p; 2192 2193 p->dev = dev; 2194 p->base_hi = base_hi; 2195 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2196 p->private_data = priv; 2197 2198 if (base_hi) { 2199 ECR_res = request_region(base_hi, 3, p->name); 2200 if (ECR_res) 2201 parport_ECR_present(p); 2202 } 2203 2204 if (base != 0x3bc) { 2205 EPP_res = request_region(base+0x3, 5, p->name); 2206 if (EPP_res) 2207 if (!parport_EPP_supported(p)) 2208 parport_ECPEPP_supported(p); 2209 } 2210 if (!parport_SPP_supported (p)) 2211 /* No port. */ 2212 goto out5; 2213 if (priv->ecr) 2214 parport_ECPPS2_supported(p); 2215 else 2216 parport_PS2_supported(p); 2217 2218 p->size = (p->modes & PARPORT_MODE_EPP)?8:3; 2219 2220 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); 2221 if (p->base_hi && priv->ecr) 2222 printk(" (0x%lx)", p->base_hi); 2223 if (p->irq == PARPORT_IRQ_AUTO) { 2224 p->irq = PARPORT_IRQ_NONE; 2225 parport_irq_probe(p); 2226 } else if (p->irq == PARPORT_IRQ_PROBEONLY) { 2227 p->irq = PARPORT_IRQ_NONE; 2228 parport_irq_probe(p); 2229 probedirq = p->irq; 2230 p->irq = PARPORT_IRQ_NONE; 2231 } 2232 if (p->irq != PARPORT_IRQ_NONE) { 2233 printk(", irq %d", p->irq); 2234 priv->ctr_writable |= 0x10; 2235 2236 if (p->dma == PARPORT_DMA_AUTO) { 2237 p->dma = PARPORT_DMA_NONE; 2238 parport_dma_probe(p); 2239 } 2240 } 2241 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq 2242 is mandatory (see above) */ 2243 p->dma = PARPORT_DMA_NONE; 2244 2245 #ifdef CONFIG_PARPORT_PC_FIFO 2246 if (parport_ECP_supported(p) && 2247 p->dma != PARPORT_DMA_NOFIFO && 2248 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { 2249 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; 2250 p->ops->compat_write_data = parport_pc_compat_write_block_pio; 2251 #ifdef CONFIG_PARPORT_1284 2252 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; 2253 /* currently broken, but working on it.. (FB) */ 2254 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ 2255 #endif /* IEEE 1284 support */ 2256 if (p->dma != PARPORT_DMA_NONE) { 2257 printk(", dma %d", p->dma); 2258 p->modes |= PARPORT_MODE_DMA; 2259 } 2260 else printk(", using FIFO"); 2261 } 2262 else 2263 /* We can't use the DMA channel after all. */ 2264 p->dma = PARPORT_DMA_NONE; 2265 #endif /* Allowed to use FIFO/DMA */ 2266 2267 printk(" ["); 2268 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}} 2269 { 2270 int f = 0; 2271 printmode(PCSPP); 2272 printmode(TRISTATE); 2273 printmode(COMPAT) 2274 printmode(EPP); 2275 printmode(ECP); 2276 printmode(DMA); 2277 } 2278 #undef printmode 2279 #ifndef CONFIG_PARPORT_1284 2280 printk ("(,...)"); 2281 #endif /* CONFIG_PARPORT_1284 */ 2282 printk("]\n"); 2283 if (probedirq != PARPORT_IRQ_NONE) 2284 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); 2285 2286 /* If No ECP release the ports grabbed above. */ 2287 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { 2288 release_region(base_hi, 3); 2289 ECR_res = NULL; 2290 } 2291 /* Likewise for EEP ports */ 2292 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { 2293 release_region(base+3, 5); 2294 EPP_res = NULL; 2295 } 2296 if (p->irq != PARPORT_IRQ_NONE) { 2297 if (request_irq (p->irq, parport_irq_handler, 2298 0, p->name, p)) { 2299 printk (KERN_WARNING "%s: irq %d in use, " 2300 "resorting to polled operation\n", 2301 p->name, p->irq); 2302 p->irq = PARPORT_IRQ_NONE; 2303 p->dma = PARPORT_DMA_NONE; 2304 } 2305 2306 #ifdef CONFIG_PARPORT_PC_FIFO 2307 #ifdef HAS_DMA 2308 if (p->dma != PARPORT_DMA_NONE) { 2309 if (request_dma (p->dma, p->name)) { 2310 printk (KERN_WARNING "%s: dma %d in use, " 2311 "resorting to PIO operation\n", 2312 p->name, p->dma); 2313 p->dma = PARPORT_DMA_NONE; 2314 } else { 2315 priv->dma_buf = 2316 dma_alloc_coherent(dev, 2317 PAGE_SIZE, 2318 &priv->dma_handle, 2319 GFP_KERNEL); 2320 if (! priv->dma_buf) { 2321 printk (KERN_WARNING "%s: " 2322 "cannot get buffer for DMA, " 2323 "resorting to PIO operation\n", 2324 p->name); 2325 free_dma(p->dma); 2326 p->dma = PARPORT_DMA_NONE; 2327 } 2328 } 2329 } 2330 #endif 2331 #endif 2332 } 2333 2334 /* Done probing. Now put the port into a sensible start-up state. */ 2335 if (priv->ecr) 2336 /* 2337 * Put the ECP detected port in PS2 mode. 2338 * Do this also for ports that have ECR but don't do ECP. 2339 */ 2340 ECR_WRITE (p, 0x34); 2341 2342 parport_pc_write_data(p, 0); 2343 parport_pc_data_forward (p); 2344 2345 /* Now that we've told the sharing engine about the port, and 2346 found out its characteristics, let the high-level drivers 2347 know about it. */ 2348 spin_lock(&ports_lock); 2349 list_add(&priv->list, &ports_list); 2350 spin_unlock(&ports_lock); 2351 parport_announce_port (p); 2352 2353 return p; 2354 2355 out5: 2356 if (ECR_res) 2357 release_region(base_hi, 3); 2358 if (EPP_res) 2359 release_region(base+0x3, 5); 2360 release_region(base, 3); 2361 out4: 2362 parport_put_port(p); 2363 out3: 2364 kfree (priv); 2365 out2: 2366 kfree (ops); 2367 out1: 2368 if (pdev) 2369 platform_device_unregister(pdev); 2370 return NULL; 2371 } 2372 2373 EXPORT_SYMBOL (parport_pc_probe_port); 2374 2375 void parport_pc_unregister_port (struct parport *p) 2376 { 2377 struct parport_pc_private *priv = p->private_data; 2378 struct parport_operations *ops = p->ops; 2379 2380 parport_remove_port(p); 2381 spin_lock(&ports_lock); 2382 list_del_init(&priv->list); 2383 spin_unlock(&ports_lock); 2384 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2385 if (p->dma != PARPORT_DMA_NONE) 2386 free_dma(p->dma); 2387 #endif 2388 if (p->irq != PARPORT_IRQ_NONE) 2389 free_irq(p->irq, p); 2390 release_region(p->base, 3); 2391 if (p->size > 3) 2392 release_region(p->base + 3, p->size - 3); 2393 if (p->modes & PARPORT_MODE_ECP) 2394 release_region(p->base_hi, 3); 2395 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA) 2396 if (priv->dma_buf) 2397 dma_free_coherent(p->physport->dev, PAGE_SIZE, 2398 priv->dma_buf, 2399 priv->dma_handle); 2400 #endif 2401 kfree (p->private_data); 2402 parport_put_port(p); 2403 kfree (ops); /* hope no-one cached it */ 2404 } 2405 2406 EXPORT_SYMBOL (parport_pc_unregister_port); 2407 2408 #ifdef CONFIG_PCI 2409 2410 /* ITE support maintained by Rich Liu <richliu@poorman.org> */ 2411 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq, 2412 int autodma, 2413 const struct parport_pc_via_data *via) 2414 { 2415 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; 2416 struct resource *base_res; 2417 u32 ite8872set; 2418 u32 ite8872_lpt, ite8872_lpthi; 2419 u8 ite8872_irq, type; 2420 int irq; 2421 int i; 2422 2423 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n"); 2424 2425 // make sure which one chip 2426 for(i = 0; i < 5; i++) { 2427 base_res = request_region(inta_addr[i], 32, "it887x"); 2428 if (base_res) { 2429 int test; 2430 pci_write_config_dword (pdev, 0x60, 2431 0xe5000000 | inta_addr[i]); 2432 pci_write_config_dword (pdev, 0x78, 2433 0x00000000 | inta_addr[i]); 2434 test = inb (inta_addr[i]); 2435 if (test != 0xff) break; 2436 release_region(inta_addr[i], 0x8); 2437 } 2438 } 2439 if(i >= 5) { 2440 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); 2441 return 0; 2442 } 2443 2444 type = inb (inta_addr[i] + 0x18); 2445 type &= 0x0f; 2446 2447 switch (type) { 2448 case 0x2: 2449 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n"); 2450 ite8872set = 0x64200000; 2451 break; 2452 case 0xa: 2453 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n"); 2454 ite8872set = 0x64200000; 2455 break; 2456 case 0xe: 2457 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); 2458 ite8872set = 0x64e00000; 2459 break; 2460 case 0x6: 2461 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n"); 2462 return 0; 2463 case 0x8: 2464 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n"); 2465 return 0; 2466 default: 2467 printk (KERN_INFO "parport_pc: unknown ITE887x\n"); 2468 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' " 2469 "output to Rich.Liu@ite.com.tw\n"); 2470 return 0; 2471 } 2472 2473 pci_read_config_byte (pdev, 0x3c, &ite8872_irq); 2474 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt); 2475 ite8872_lpt &= 0x0000ff00; 2476 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi); 2477 ite8872_lpthi &= 0x0000ff00; 2478 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt); 2479 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi); 2480 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); 2481 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function 2482 // SET Parallel IRQ 2483 pci_write_config_dword (pdev, 0x9c, 2484 ite8872set | (ite8872_irq * 0x11111)); 2485 2486 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); 2487 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", 2488 ite8872_lpt); 2489 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", 2490 ite8872_lpthi); 2491 2492 /* Let the user (or defaults) steer us away from interrupts */ 2493 irq = ite8872_irq; 2494 if (autoirq != PARPORT_IRQ_AUTO) 2495 irq = PARPORT_IRQ_NONE; 2496 2497 /* 2498 * Release the resource so that parport_pc_probe_port can get it. 2499 */ 2500 release_resource(base_res); 2501 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi, 2502 irq, PARPORT_DMA_NONE, &pdev->dev)) { 2503 printk (KERN_INFO 2504 "parport_pc: ITE 8872 parallel port: io=0x%X", 2505 ite8872_lpt); 2506 if (irq != PARPORT_IRQ_NONE) 2507 printk (", irq=%d", irq); 2508 printk ("\n"); 2509 return 1; 2510 } 2511 2512 return 0; 2513 } 2514 2515 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru> 2516 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */ 2517 static int __devinitdata parport_init_mode = 0; 2518 2519 /* Data for two known VIA chips */ 2520 static struct parport_pc_via_data via_686a_data __devinitdata = { 2521 0x51, 2522 0x50, 2523 0x85, 2524 0x02, 2525 0xE2, 2526 0xF0, 2527 0xE6 2528 }; 2529 static struct parport_pc_via_data via_8231_data __devinitdata = { 2530 0x45, 2531 0x44, 2532 0x50, 2533 0x04, 2534 0xF2, 2535 0xFA, 2536 0xF6 2537 }; 2538 2539 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq, 2540 int autodma, 2541 const struct parport_pc_via_data *via) 2542 { 2543 u8 tmp, tmp2, siofunc; 2544 u8 ppcontrol = 0; 2545 int dma, irq; 2546 unsigned port1, port2; 2547 unsigned have_epp = 0; 2548 2549 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n"); 2550 2551 switch(parport_init_mode) 2552 { 2553 case 1: 2554 printk(KERN_DEBUG "parport_pc: setting SPP mode\n"); 2555 siofunc = VIA_FUNCTION_PARPORT_SPP; 2556 break; 2557 case 2: 2558 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n"); 2559 siofunc = VIA_FUNCTION_PARPORT_SPP; 2560 ppcontrol = VIA_PARPORT_BIDIR; 2561 break; 2562 case 3: 2563 printk(KERN_DEBUG "parport_pc: setting EPP mode\n"); 2564 siofunc = VIA_FUNCTION_PARPORT_EPP; 2565 ppcontrol = VIA_PARPORT_BIDIR; 2566 have_epp = 1; 2567 break; 2568 case 4: 2569 printk(KERN_DEBUG "parport_pc: setting ECP mode\n"); 2570 siofunc = VIA_FUNCTION_PARPORT_ECP; 2571 ppcontrol = VIA_PARPORT_BIDIR; 2572 break; 2573 case 5: 2574 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n"); 2575 siofunc = VIA_FUNCTION_PARPORT_ECP; 2576 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP; 2577 have_epp = 1; 2578 break; 2579 default: 2580 printk(KERN_DEBUG "parport_pc: probing current configuration\n"); 2581 siofunc = VIA_FUNCTION_PROBE; 2582 break; 2583 } 2584 /* 2585 * unlock super i/o configuration 2586 */ 2587 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2588 tmp |= via->via_pci_superio_config_data; 2589 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2590 2591 /* Bits 1-0: Parallel Port Mode / Enable */ 2592 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2593 tmp = inb (VIA_CONFIG_DATA); 2594 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */ 2595 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2596 tmp2 = inb (VIA_CONFIG_DATA); 2597 if (siofunc == VIA_FUNCTION_PROBE) 2598 { 2599 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE; 2600 ppcontrol = tmp2; 2601 } 2602 else 2603 { 2604 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE; 2605 tmp |= siofunc; 2606 outb(via->viacfg_function, VIA_CONFIG_INDEX); 2607 outb(tmp, VIA_CONFIG_DATA); 2608 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP); 2609 tmp2 |= ppcontrol; 2610 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX); 2611 outb(tmp2, VIA_CONFIG_DATA); 2612 } 2613 2614 /* Parallel Port I/O Base Address, bits 9-2 */ 2615 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2616 port1 = inb(VIA_CONFIG_DATA) << 2; 2617 2618 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1); 2619 if ((port1 == 0x3BC) && have_epp) 2620 { 2621 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); 2622 outb((0x378 >> 2), VIA_CONFIG_DATA); 2623 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); 2624 port1 = 0x378; 2625 } 2626 2627 /* 2628 * lock super i/o configuration 2629 */ 2630 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp); 2631 tmp &= ~via->via_pci_superio_config_data; 2632 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); 2633 2634 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { 2635 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); 2636 return 0; 2637 } 2638 2639 /* Bits 7-4: PnP Routing for Parallel Port IRQ */ 2640 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp); 2641 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4); 2642 2643 if (siofunc == VIA_FUNCTION_PARPORT_ECP) 2644 { 2645 /* Bits 3-2: PnP Routing for Parallel Port DMA */ 2646 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp); 2647 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2); 2648 } 2649 else 2650 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */ 2651 dma = PARPORT_DMA_NONE; 2652 2653 /* Let the user (or defaults) steer us away from interrupts and DMA */ 2654 if (autoirq == PARPORT_IRQ_NONE) { 2655 irq = PARPORT_IRQ_NONE; 2656 dma = PARPORT_DMA_NONE; 2657 } 2658 if (autodma == PARPORT_DMA_NONE) 2659 dma = PARPORT_DMA_NONE; 2660 2661 switch (port1) { 2662 case 0x3bc: port2 = 0x7bc; break; 2663 case 0x378: port2 = 0x778; break; 2664 case 0x278: port2 = 0x678; break; 2665 default: 2666 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n", 2667 port1); 2668 return 0; 2669 } 2670 2671 /* filter bogus IRQs */ 2672 switch (irq) { 2673 case 0: 2674 case 2: 2675 case 8: 2676 case 13: 2677 irq = PARPORT_IRQ_NONE; 2678 break; 2679 2680 default: /* do nothing */ 2681 break; 2682 } 2683 2684 /* finally, do the probe with values obtained */ 2685 if (parport_pc_probe_port (port1, port2, irq, dma, &pdev->dev)) { 2686 printk (KERN_INFO 2687 "parport_pc: VIA parallel port: io=0x%X", port1); 2688 if (irq != PARPORT_IRQ_NONE) 2689 printk (", irq=%d", irq); 2690 if (dma != PARPORT_DMA_NONE) 2691 printk (", dma=%d", dma); 2692 printk ("\n"); 2693 return 1; 2694 } 2695 2696 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", 2697 port1, irq, dma); 2698 return 0; 2699 } 2700 2701 2702 enum parport_pc_sio_types { 2703 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */ 2704 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */ 2705 sio_ite_8872, 2706 last_sio 2707 }; 2708 2709 /* each element directly indexed from enum list, above */ 2710 static struct parport_pc_superio { 2711 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, 2712 const struct parport_pc_via_data *via); 2713 const struct parport_pc_via_data *via; 2714 } parport_pc_superio_info[] __devinitdata = { 2715 { sio_via_probe, &via_686a_data, }, 2716 { sio_via_probe, &via_8231_data, }, 2717 { sio_ite_8872_probe, NULL, }, 2718 }; 2719 2720 enum parport_pc_pci_cards { 2721 siig_1p_10x = last_sio, 2722 siig_2p_10x, 2723 siig_1p_20x, 2724 siig_2p_20x, 2725 lava_parallel, 2726 lava_parallel_dual_a, 2727 lava_parallel_dual_b, 2728 boca_ioppar, 2729 plx_9050, 2730 timedia_4078a, 2731 timedia_4079h, 2732 timedia_4085h, 2733 timedia_4088a, 2734 timedia_4089a, 2735 timedia_4095a, 2736 timedia_4096a, 2737 timedia_4078u, 2738 timedia_4079a, 2739 timedia_4085u, 2740 timedia_4079r, 2741 timedia_4079s, 2742 timedia_4079d, 2743 timedia_4079e, 2744 timedia_4079f, 2745 timedia_9079a, 2746 timedia_9079b, 2747 timedia_9079c, 2748 timedia_4006a, 2749 timedia_4014, 2750 timedia_4008a, 2751 timedia_4018, 2752 timedia_9018a, 2753 syba_2p_epp, 2754 syba_1p_ecp, 2755 titan_010l, 2756 titan_1284p1, 2757 titan_1284p2, 2758 avlab_1p, 2759 avlab_2p, 2760 oxsemi_952, 2761 oxsemi_954, 2762 oxsemi_840, 2763 aks_0100, 2764 mobility_pp, 2765 netmos_9705, 2766 netmos_9715, 2767 netmos_9755, 2768 netmos_9805, 2769 netmos_9815, 2770 }; 2771 2772 2773 /* each element directly indexed from enum list, above 2774 * (but offset by last_sio) */ 2775 static struct parport_pc_pci { 2776 int numports; 2777 struct { /* BAR (base address registers) numbers in the config 2778 space header */ 2779 int lo; 2780 int hi; /* -1 if not there, >6 for offset-method (max 2781 BAR is 6) */ 2782 } addr[4]; 2783 2784 /* If set, this is called immediately after pci_enable_device. 2785 * If it returns non-zero, no probing will take place and the 2786 * ports will not be used. */ 2787 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma); 2788 2789 /* If set, this is called after probing for ports. If 'failed' 2790 * is non-zero we couldn't use any of the ports. */ 2791 void (*postinit_hook) (struct pci_dev *pdev, int failed); 2792 } cards[] = { 2793 /* siig_1p_10x */ { 1, { { 2, 3 }, } }, 2794 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2795 /* siig_1p_20x */ { 1, { { 0, 1 }, } }, 2796 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2797 /* lava_parallel */ { 1, { { 0, -1 }, } }, 2798 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } }, 2799 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } }, 2800 /* boca_ioppar */ { 1, { { 0, -1 }, } }, 2801 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } }, 2802 /* timedia_4078a */ { 1, { { 2, -1 }, } }, 2803 /* timedia_4079h */ { 1, { { 2, 3 }, } }, 2804 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2805 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2806 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2807 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2808 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } }, 2809 /* timedia_4078u */ { 1, { { 2, -1 }, } }, 2810 /* timedia_4079a */ { 1, { { 2, 3 }, } }, 2811 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } }, 2812 /* timedia_4079r */ { 1, { { 2, 3 }, } }, 2813 /* timedia_4079s */ { 1, { { 2, 3 }, } }, 2814 /* timedia_4079d */ { 1, { { 2, 3 }, } }, 2815 /* timedia_4079e */ { 1, { { 2, 3 }, } }, 2816 /* timedia_4079f */ { 1, { { 2, 3 }, } }, 2817 /* timedia_9079a */ { 1, { { 2, 3 }, } }, 2818 /* timedia_9079b */ { 1, { { 2, 3 }, } }, 2819 /* timedia_9079c */ { 1, { { 2, 3 }, } }, 2820 /* timedia_4006a */ { 1, { { 0, -1 }, } }, 2821 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } }, 2822 /* timedia_4008a */ { 1, { { 0, 1 }, } }, 2823 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2824 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2825 /* SYBA uses fixed offsets in 2826 a 1K io window */ 2827 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } }, 2828 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } }, 2829 /* titan_010l */ { 1, { { 3, -1 }, } }, 2830 /* titan_1284p1 */ { 1, { { 0, 1 }, } }, 2831 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } }, 2832 /* avlab_1p */ { 1, { { 0, 1}, } }, 2833 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, 2834 /* The Oxford Semi cards are unusual: 954 doesn't support ECP, 2835 * and 840 locks up if you write 1 to bit 2! */ 2836 /* oxsemi_952 */ { 1, { { 0, 1 }, } }, 2837 /* oxsemi_954 */ { 1, { { 0, -1 }, } }, 2838 /* oxsemi_840 */ { 1, { { 0, -1 }, } }, 2839 /* aks_0100 */ { 1, { { 0, -1 }, } }, 2840 /* mobility_pp */ { 1, { { 0, 1 }, } }, 2841 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */ 2842 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2843 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */ 2844 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */ 2845 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */ 2846 }; 2847 2848 static const struct pci_device_id parport_pc_pci_tbl[] = { 2849 /* Super-IO onboard chips */ 2850 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a }, 2851 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 }, 2852 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 2853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 }, 2854 2855 /* PCI cards */ 2856 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x, 2857 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x }, 2858 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x, 2859 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x }, 2860 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x, 2861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x }, 2862 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x, 2863 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x }, 2864 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL, 2865 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel }, 2866 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A, 2867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a }, 2868 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B, 2869 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b }, 2870 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR, 2871 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar }, 2872 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2873 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 }, 2874 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/ 2875 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a }, 2876 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h }, 2877 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h }, 2878 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a }, 2879 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a }, 2880 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a }, 2881 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a }, 2882 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u }, 2883 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a }, 2884 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u }, 2885 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r }, 2886 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s }, 2887 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d }, 2888 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e }, 2889 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f }, 2890 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a }, 2891 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b }, 2892 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c }, 2893 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a }, 2894 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 }, 2895 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a }, 2896 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 }, 2897 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a }, 2898 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp }, 2899 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP, 2900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp }, 2901 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP, 2902 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp }, 2903 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L, 2904 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l }, 2905 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 }, 2906 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 }, 2907 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/ 2908 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */ 2909 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p}, 2910 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP, 2911 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 }, 2912 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP, 2913 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 }, 2914 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840, 2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 }, 2916 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD, 2917 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 }, 2918 /* NetMos communication controllers */ 2919 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705, 2920 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 }, 2921 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715, 2922 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 }, 2923 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755, 2924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 }, 2925 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805, 2926 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 }, 2927 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815, 2928 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 }, 2929 { 0, } /* terminate list */ 2930 }; 2931 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl); 2932 2933 struct pci_parport_data { 2934 int num; 2935 struct parport *ports[2]; 2936 }; 2937 2938 static int parport_pc_pci_probe (struct pci_dev *dev, 2939 const struct pci_device_id *id) 2940 { 2941 int err, count, n, i = id->driver_data; 2942 struct pci_parport_data *data; 2943 2944 if (i < last_sio) 2945 /* This is an onboard Super-IO and has already been probed */ 2946 return 0; 2947 2948 /* This is a PCI card */ 2949 i -= last_sio; 2950 count = 0; 2951 if ((err = pci_enable_device (dev)) != 0) 2952 return err; 2953 2954 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL); 2955 if (!data) 2956 return -ENOMEM; 2957 2958 if (cards[i].preinit_hook && 2959 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) { 2960 kfree(data); 2961 return -ENODEV; 2962 } 2963 2964 for (n = 0; n < cards[i].numports; n++) { 2965 int lo = cards[i].addr[n].lo; 2966 int hi = cards[i].addr[n].hi; 2967 unsigned long io_lo, io_hi; 2968 io_lo = pci_resource_start (dev, lo); 2969 io_hi = 0; 2970 if ((hi >= 0) && (hi <= 6)) 2971 io_hi = pci_resource_start (dev, hi); 2972 else if (hi > 6) 2973 io_lo += hi; /* Reinterpret the meaning of 2974 "hi" as an offset (see SYBA 2975 def.) */ 2976 /* TODO: test if sharing interrupts works */ 2977 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, " 2978 "I/O at %#lx(%#lx)\n", 2979 parport_pc_pci_tbl[i + last_sio].vendor, 2980 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi); 2981 data->ports[count] = 2982 parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE, 2983 PARPORT_DMA_NONE, &dev->dev); 2984 if (data->ports[count]) 2985 count++; 2986 } 2987 2988 data->num = count; 2989 2990 if (cards[i].postinit_hook) 2991 cards[i].postinit_hook (dev, count == 0); 2992 2993 if (count) { 2994 pci_set_drvdata(dev, data); 2995 return 0; 2996 } 2997 2998 kfree(data); 2999 3000 return -ENODEV; 3001 } 3002 3003 static void __devexit parport_pc_pci_remove(struct pci_dev *dev) 3004 { 3005 struct pci_parport_data *data = pci_get_drvdata(dev); 3006 int i; 3007 3008 pci_set_drvdata(dev, NULL); 3009 3010 if (data) { 3011 for (i = data->num - 1; i >= 0; i--) 3012 parport_pc_unregister_port(data->ports[i]); 3013 3014 kfree(data); 3015 } 3016 } 3017 3018 static struct pci_driver parport_pc_pci_driver = { 3019 .name = "parport_pc", 3020 .id_table = parport_pc_pci_tbl, 3021 .probe = parport_pc_pci_probe, 3022 .remove = __devexit_p(parport_pc_pci_remove), 3023 }; 3024 3025 static int __init parport_pc_init_superio (int autoirq, int autodma) 3026 { 3027 const struct pci_device_id *id; 3028 struct pci_dev *pdev = NULL; 3029 int ret = 0; 3030 3031 for_each_pci_dev(pdev) { 3032 id = pci_match_id(parport_pc_pci_tbl, pdev); 3033 if (id == NULL || id->driver_data >= last_sio) 3034 continue; 3035 3036 if (parport_pc_superio_info[id->driver_data].probe 3037 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) { 3038 ret++; 3039 } 3040 } 3041 3042 return ret; /* number of devices found */ 3043 } 3044 #else 3045 static struct pci_driver parport_pc_pci_driver; 3046 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;} 3047 #endif /* CONFIG_PCI */ 3048 3049 3050 static const struct pnp_device_id parport_pc_pnp_tbl[] = { 3051 /* Standard LPT Printer Port */ 3052 {.id = "PNP0400", .driver_data = 0}, 3053 /* ECP Printer Port */ 3054 {.id = "PNP0401", .driver_data = 0}, 3055 { } 3056 }; 3057 3058 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl); 3059 3060 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) 3061 { 3062 struct parport *pdata; 3063 unsigned long io_lo, io_hi; 3064 int dma, irq; 3065 3066 if (pnp_port_valid(dev,0) && 3067 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) { 3068 io_lo = pnp_port_start(dev,0); 3069 } else 3070 return -EINVAL; 3071 3072 if (pnp_port_valid(dev,1) && 3073 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) { 3074 io_hi = pnp_port_start(dev,1); 3075 } else 3076 io_hi = 0; 3077 3078 if (pnp_irq_valid(dev,0) && 3079 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) { 3080 irq = pnp_irq(dev,0); 3081 } else 3082 irq = PARPORT_IRQ_NONE; 3083 3084 if (pnp_dma_valid(dev,0) && 3085 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) { 3086 dma = pnp_dma(dev,0); 3087 } else 3088 dma = PARPORT_DMA_NONE; 3089 3090 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name); 3091 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, &dev->dev))) 3092 return -ENODEV; 3093 3094 pnp_set_drvdata(dev,pdata); 3095 return 0; 3096 } 3097 3098 static void parport_pc_pnp_remove(struct pnp_dev *dev) 3099 { 3100 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev); 3101 if (!pdata) 3102 return; 3103 3104 parport_pc_unregister_port(pdata); 3105 } 3106 3107 /* we only need the pnp layer to activate the device, at least for now */ 3108 static struct pnp_driver parport_pc_pnp_driver = { 3109 .name = "parport_pc", 3110 .id_table = parport_pc_pnp_tbl, 3111 .probe = parport_pc_pnp_probe, 3112 .remove = parport_pc_pnp_remove, 3113 }; 3114 3115 3116 static int __devinit parport_pc_platform_probe(struct platform_device *pdev) 3117 { 3118 /* Always succeed, the actual probing is done in 3119 * parport_pc_probe_port(). */ 3120 return 0; 3121 } 3122 3123 static struct platform_driver parport_pc_platform_driver = { 3124 .driver = { 3125 .owner = THIS_MODULE, 3126 .name = "parport_pc", 3127 }, 3128 .probe = parport_pc_platform_probe, 3129 }; 3130 3131 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */ 3132 static int __devinit __attribute__((unused)) 3133 parport_pc_find_isa_ports (int autoirq, int autodma) 3134 { 3135 int count = 0; 3136 3137 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL)) 3138 count++; 3139 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL)) 3140 count++; 3141 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL)) 3142 count++; 3143 3144 return count; 3145 } 3146 3147 /* This function is called by parport_pc_init if the user didn't 3148 * specify any ports to probe. Its job is to find some ports. Order 3149 * is important here -- we want ISA ports to be registered first, 3150 * followed by PCI cards (for least surprise), but before that we want 3151 * to do chipset-specific tests for some onboard ports that we know 3152 * about. 3153 * 3154 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY 3155 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO 3156 */ 3157 static void __init parport_pc_find_ports (int autoirq, int autodma) 3158 { 3159 int count = 0, err; 3160 3161 #ifdef CONFIG_PARPORT_PC_SUPERIO 3162 detect_and_report_winbond (); 3163 detect_and_report_smsc (); 3164 #endif 3165 3166 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */ 3167 count += parport_pc_init_superio (autoirq, autodma); 3168 3169 /* PnP ports, skip detection if SuperIO already found them */ 3170 if (!count) { 3171 err = pnp_register_driver (&parport_pc_pnp_driver); 3172 if (!err) 3173 pnp_registered_parport = 1; 3174 } 3175 3176 /* ISA ports and whatever (see asm/parport.h). */ 3177 parport_pc_find_nonpci_ports (autoirq, autodma); 3178 3179 err = pci_register_driver (&parport_pc_pci_driver); 3180 if (!err) 3181 pci_registered_parport = 1; 3182 } 3183 3184 /* 3185 * Piles of crap below pretend to be a parser for module and kernel 3186 * parameters. Say "thank you" to whoever had come up with that 3187 * syntax and keep in mind that code below is a cleaned up version. 3188 */ 3189 3190 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 }; 3191 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = 3192 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO }; 3193 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE }; 3194 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY }; 3195 3196 static int __init parport_parse_param(const char *s, int *val, 3197 int automatic, int none, int nofifo) 3198 { 3199 if (!s) 3200 return 0; 3201 if (!strncmp(s, "auto", 4)) 3202 *val = automatic; 3203 else if (!strncmp(s, "none", 4)) 3204 *val = none; 3205 else if (nofifo && !strncmp(s, "nofifo", 4)) 3206 *val = nofifo; 3207 else { 3208 char *ep; 3209 unsigned long r = simple_strtoul(s, &ep, 0); 3210 if (ep != s) 3211 *val = r; 3212 else { 3213 printk(KERN_ERR "parport: bad specifier `%s'\n", s); 3214 return -1; 3215 } 3216 } 3217 return 0; 3218 } 3219 3220 static int __init parport_parse_irq(const char *irqstr, int *val) 3221 { 3222 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO, 3223 PARPORT_IRQ_NONE, 0); 3224 } 3225 3226 static int __init parport_parse_dma(const char *dmastr, int *val) 3227 { 3228 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO, 3229 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO); 3230 } 3231 3232 #ifdef CONFIG_PCI 3233 static int __init parport_init_mode_setup(char *str) 3234 { 3235 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); 3236 3237 if (!strcmp (str, "spp")) 3238 parport_init_mode=1; 3239 if (!strcmp (str, "ps2")) 3240 parport_init_mode=2; 3241 if (!strcmp (str, "epp")) 3242 parport_init_mode=3; 3243 if (!strcmp (str, "ecp")) 3244 parport_init_mode=4; 3245 if (!strcmp (str, "ecpepp")) 3246 parport_init_mode=5; 3247 return 1; 3248 } 3249 #endif 3250 3251 #ifdef MODULE 3252 static const char *irq[PARPORT_PC_MAX_PORTS]; 3253 static const char *dma[PARPORT_PC_MAX_PORTS]; 3254 3255 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)"); 3256 module_param_array(io, int, NULL, 0); 3257 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)"); 3258 module_param_array(io_hi, int, NULL, 0); 3259 MODULE_PARM_DESC(irq, "IRQ line"); 3260 module_param_array(irq, charp, NULL, 0); 3261 MODULE_PARM_DESC(dma, "DMA channel"); 3262 module_param_array(dma, charp, NULL, 0); 3263 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \ 3264 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO)) 3265 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation"); 3266 module_param(verbose_probing, int, 0644); 3267 #endif 3268 #ifdef CONFIG_PCI 3269 static char *init_mode; 3270 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)"); 3271 module_param(init_mode, charp, 0); 3272 #endif 3273 3274 static int __init parse_parport_params(void) 3275 { 3276 unsigned int i; 3277 int val; 3278 3279 #ifdef CONFIG_PCI 3280 if (init_mode) 3281 parport_init_mode_setup(init_mode); 3282 #endif 3283 3284 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { 3285 if (parport_parse_irq(irq[i], &val)) 3286 return 1; 3287 irqval[i] = val; 3288 if (parport_parse_dma(dma[i], &val)) 3289 return 1; 3290 dmaval[i] = val; 3291 } 3292 if (!io[0]) { 3293 /* The user can make us use any IRQs or DMAs we find. */ 3294 if (irq[0] && !parport_parse_irq(irq[0], &val)) 3295 switch (val) { 3296 case PARPORT_IRQ_NONE: 3297 case PARPORT_IRQ_AUTO: 3298 irqval[0] = val; 3299 break; 3300 default: 3301 printk (KERN_WARNING 3302 "parport_pc: irq specified " 3303 "without base address. Use 'io=' " 3304 "to specify one\n"); 3305 } 3306 3307 if (dma[0] && !parport_parse_dma(dma[0], &val)) 3308 switch (val) { 3309 case PARPORT_DMA_NONE: 3310 case PARPORT_DMA_AUTO: 3311 dmaval[0] = val; 3312 break; 3313 default: 3314 printk (KERN_WARNING 3315 "parport_pc: dma specified " 3316 "without base address. Use 'io=' " 3317 "to specify one\n"); 3318 } 3319 } 3320 return 0; 3321 } 3322 3323 #else 3324 3325 static int parport_setup_ptr __initdata = 0; 3326 3327 /* 3328 * Acceptable parameters: 3329 * 3330 * parport=0 3331 * parport=auto 3332 * parport=0xBASE[,IRQ[,DMA]] 3333 * 3334 * IRQ/DMA may be numeric or 'auto' or 'none' 3335 */ 3336 static int __init parport_setup (char *str) 3337 { 3338 char *endptr; 3339 char *sep; 3340 int val; 3341 3342 if (!str || !*str || (*str == '0' && !*(str+1))) { 3343 /* Disable parport if "parport=0" in cmdline */ 3344 io[0] = PARPORT_DISABLE; 3345 return 1; 3346 } 3347 3348 if (!strncmp (str, "auto", 4)) { 3349 irqval[0] = PARPORT_IRQ_AUTO; 3350 dmaval[0] = PARPORT_DMA_AUTO; 3351 return 1; 3352 } 3353 3354 val = simple_strtoul (str, &endptr, 0); 3355 if (endptr == str) { 3356 printk (KERN_WARNING "parport=%s not understood\n", str); 3357 return 1; 3358 } 3359 3360 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { 3361 printk(KERN_ERR "parport=%s ignored, too many ports\n", str); 3362 return 1; 3363 } 3364 3365 io[parport_setup_ptr] = val; 3366 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE; 3367 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE; 3368 3369 sep = strchr(str, ','); 3370 if (sep++) { 3371 if (parport_parse_irq(sep, &val)) 3372 return 1; 3373 irqval[parport_setup_ptr] = val; 3374 sep = strchr(sep, ','); 3375 if (sep++) { 3376 if (parport_parse_dma(sep, &val)) 3377 return 1; 3378 dmaval[parport_setup_ptr] = val; 3379 } 3380 } 3381 parport_setup_ptr++; 3382 return 1; 3383 } 3384 3385 static int __init parse_parport_params(void) 3386 { 3387 return io[0] == PARPORT_DISABLE; 3388 } 3389 3390 __setup ("parport=", parport_setup); 3391 3392 /* 3393 * Acceptable parameters: 3394 * 3395 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp] 3396 */ 3397 #ifdef CONFIG_PCI 3398 __setup("parport_init_mode=",parport_init_mode_setup); 3399 #endif 3400 #endif 3401 3402 /* "Parser" ends here */ 3403 3404 static int __init parport_pc_init(void) 3405 { 3406 int err; 3407 3408 if (parse_parport_params()) 3409 return -EINVAL; 3410 3411 err = platform_driver_register(&parport_pc_platform_driver); 3412 if (err) 3413 return err; 3414 3415 if (io[0]) { 3416 int i; 3417 /* Only probe the ports we were given. */ 3418 user_specified = 1; 3419 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { 3420 if (!io[i]) 3421 break; 3422 if ((io_hi[i]) == PARPORT_IOHI_AUTO) 3423 io_hi[i] = 0x400 + io[i]; 3424 parport_pc_probe_port(io[i], io_hi[i], 3425 irqval[i], dmaval[i], NULL); 3426 } 3427 } else 3428 parport_pc_find_ports (irqval[0], dmaval[0]); 3429 3430 return 0; 3431 } 3432 3433 static void __exit parport_pc_exit(void) 3434 { 3435 if (pci_registered_parport) 3436 pci_unregister_driver (&parport_pc_pci_driver); 3437 if (pnp_registered_parport) 3438 pnp_unregister_driver (&parport_pc_pnp_driver); 3439 platform_driver_unregister(&parport_pc_platform_driver); 3440 3441 while (!list_empty(&ports_list)) { 3442 struct parport_pc_private *priv; 3443 struct parport *port; 3444 priv = list_entry(ports_list.next, 3445 struct parport_pc_private, list); 3446 port = priv->port; 3447 if (port->dev && port->dev->bus == &platform_bus_type) 3448 platform_device_unregister( 3449 to_platform_device(port->dev)); 3450 parport_pc_unregister_port(port); 3451 } 3452 } 3453 3454 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others"); 3455 MODULE_DESCRIPTION("PC-style parallel port driver"); 3456 MODULE_LICENSE("GPL"); 3457 module_init(parport_pc_init) 3458 module_exit(parport_pc_exit) 3459