1 /* Low-level parallel port routines for built-in port on SGI IP32 2 * 3 * Author: Arnaud Giersch <arnaud.giersch@free.fr> 4 * 5 * Based on parport_pc.c by 6 * Phil Blundell, Tim Waugh, Jose Renau, David Campbell, 7 * Andrea Arcangeli, et al. 8 * 9 * Thanks to Ilya A. Volynets-Evenbakh for his help. 10 * 11 * Copyright (C) 2005, 2006 Arnaud Giersch. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the Free 15 * Software Foundation; either version 2 of the License, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, but WITHOUT 19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 21 * more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 59 25 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 26 */ 27 28 /* Current status: 29 * 30 * Basic SPP and PS2 modes are supported. 31 * Support for parallel port IRQ is present. 32 * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are 33 * supported. 34 * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with 35 * or without interrupt support. 36 * 37 * Hardware ECP mode is not fully implemented (ecp_read_data and 38 * ecp_write_addr are actually missing). 39 * 40 * To do: 41 * 42 * Fully implement ECP mode. 43 * EPP and ECP mode need to be tested. I currently do not own any 44 * peripheral supporting these extended mode, and cannot test them. 45 * If DMA mode works well, decide if support for PIO FIFO modes should be 46 * dropped. 47 * Use the io{read,write} family functions when they become available in 48 * the linux-mips.org tree. Note: the MIPS specific functions readsb() 49 * and writesb() are to be translated by ioread8_rep() and iowrite8_rep() 50 * respectively. 51 */ 52 53 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an 54 * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1]. 55 * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte 56 * FIFO buffer and supports DMA transfers. 57 * 58 * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html 59 * 60 * Theoretically, we could simply use the parport_pc module. It is however 61 * not so simple. The parport_pc code assumes that the parallel port 62 * registers are port-mapped. On the O2, they are memory-mapped. 63 * Furthermore, each register is replicated on 256 consecutive addresses (as 64 * it is for the built-in serial ports on the same chip). 65 */ 66 67 /*--- Some configuration defines ---------------------------------------*/ 68 69 /* DEBUG_PARPORT_IP32 70 * 0 disable debug 71 * 1 standard level: pr_debug1 is enabled 72 * 2 parport_ip32_dump_state is enabled 73 * >=3 verbose level: pr_debug is enabled 74 */ 75 #if !defined(DEBUG_PARPORT_IP32) 76 # define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */ 77 #endif 78 79 /*----------------------------------------------------------------------*/ 80 81 /* Setup DEBUG macros. This is done before any includes, just in case we 82 * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3. 83 */ 84 #if DEBUG_PARPORT_IP32 == 1 85 # warning DEBUG_PARPORT_IP32 == 1 86 #elif DEBUG_PARPORT_IP32 == 2 87 # warning DEBUG_PARPORT_IP32 == 2 88 #elif DEBUG_PARPORT_IP32 >= 3 89 # warning DEBUG_PARPORT_IP32 >= 3 90 # if !defined(DEBUG) 91 # define DEBUG /* enable pr_debug() in kernel.h */ 92 # endif 93 #endif 94 95 #include <linux/completion.h> 96 #include <linux/delay.h> 97 #include <linux/dma-mapping.h> 98 #include <linux/err.h> 99 #include <linux/init.h> 100 #include <linux/interrupt.h> 101 #include <linux/jiffies.h> 102 #include <linux/kernel.h> 103 #include <linux/module.h> 104 #include <linux/parport.h> 105 #include <linux/sched/signal.h> 106 #include <linux/slab.h> 107 #include <linux/spinlock.h> 108 #include <linux/stddef.h> 109 #include <linux/types.h> 110 #include <asm/io.h> 111 #include <asm/ip32/ip32_ints.h> 112 #include <asm/ip32/mace.h> 113 114 /*--- Global variables -------------------------------------------------*/ 115 116 /* Verbose probing on by default for debugging. */ 117 #if DEBUG_PARPORT_IP32 >= 1 118 # define DEFAULT_VERBOSE_PROBING 1 119 #else 120 # define DEFAULT_VERBOSE_PROBING 0 121 #endif 122 123 /* Default prefix for printk */ 124 #define PPIP32 "parport_ip32: " 125 126 /* 127 * These are the module parameters: 128 * @features: bit mask of features to enable/disable 129 * (all enabled by default) 130 * @verbose_probing: log chit-chat during initialization 131 */ 132 #define PARPORT_IP32_ENABLE_IRQ (1U << 0) 133 #define PARPORT_IP32_ENABLE_DMA (1U << 1) 134 #define PARPORT_IP32_ENABLE_SPP (1U << 2) 135 #define PARPORT_IP32_ENABLE_EPP (1U << 3) 136 #define PARPORT_IP32_ENABLE_ECP (1U << 4) 137 static unsigned int features = ~0U; 138 static bool verbose_probing = DEFAULT_VERBOSE_PROBING; 139 140 /* We do not support more than one port. */ 141 static struct parport *this_port; 142 143 /* Timing constants for FIFO modes. */ 144 #define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */ 145 #define FIFO_POLLING_INTERVAL 50 /* microseconds */ 146 147 /*--- I/O register definitions -----------------------------------------*/ 148 149 /** 150 * struct parport_ip32_regs - virtual addresses of parallel port registers 151 * @data: Data Register 152 * @dsr: Device Status Register 153 * @dcr: Device Control Register 154 * @eppAddr: EPP Address Register 155 * @eppData0: EPP Data Register 0 156 * @eppData1: EPP Data Register 1 157 * @eppData2: EPP Data Register 2 158 * @eppData3: EPP Data Register 3 159 * @ecpAFifo: ECP Address FIFO 160 * @fifo: General FIFO register. The same address is used for: 161 * - cFifo, the Parallel Port DATA FIFO 162 * - ecpDFifo, the ECP Data FIFO 163 * - tFifo, the ECP Test FIFO 164 * @cnfgA: Configuration Register A 165 * @cnfgB: Configuration Register B 166 * @ecr: Extended Control Register 167 */ 168 struct parport_ip32_regs { 169 void __iomem *data; 170 void __iomem *dsr; 171 void __iomem *dcr; 172 void __iomem *eppAddr; 173 void __iomem *eppData0; 174 void __iomem *eppData1; 175 void __iomem *eppData2; 176 void __iomem *eppData3; 177 void __iomem *ecpAFifo; 178 void __iomem *fifo; 179 void __iomem *cnfgA; 180 void __iomem *cnfgB; 181 void __iomem *ecr; 182 }; 183 184 /* Device Status Register */ 185 #define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */ 186 #define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */ 187 #define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */ 188 #define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */ 189 #define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */ 190 #define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */ 191 /* #define DSR_reserved (1U << 1) */ 192 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */ 193 194 /* Device Control Register */ 195 /* #define DCR_reserved (1U << 7) | (1U << 6) */ 196 #define DCR_DIR (1U << 5) /* direction */ 197 #define DCR_IRQ (1U << 4) /* interrupt on nAck */ 198 #define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */ 199 #define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */ 200 #define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */ 201 #define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */ 202 203 /* ECP Configuration Register A */ 204 #define CNFGA_IRQ (1U << 7) 205 #define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4)) 206 #define CNFGA_ID_SHIFT 4 207 #define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT) 208 #define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT) 209 #define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT) 210 /* #define CNFGA_reserved (1U << 3) */ 211 #define CNFGA_nBYTEINTRANS (1U << 2) 212 #define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0)) 213 214 /* ECP Configuration Register B */ 215 #define CNFGB_COMPRESS (1U << 7) 216 #define CNFGB_INTRVAL (1U << 6) 217 #define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3)) 218 #define CNFGB_IRQ_SHIFT 3 219 #define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0)) 220 #define CNFGB_DMA_SHIFT 0 221 222 /* Extended Control Register */ 223 #define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5)) 224 #define ECR_MODE_SHIFT 5 225 #define ECR_MODE_SPP (00U << ECR_MODE_SHIFT) 226 #define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT) 227 #define ECR_MODE_PPF (02U << ECR_MODE_SHIFT) 228 #define ECR_MODE_ECP (03U << ECR_MODE_SHIFT) 229 #define ECR_MODE_EPP (04U << ECR_MODE_SHIFT) 230 /* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */ 231 #define ECR_MODE_TST (06U << ECR_MODE_SHIFT) 232 #define ECR_MODE_CFG (07U << ECR_MODE_SHIFT) 233 #define ECR_nERRINTR (1U << 4) 234 #define ECR_DMAEN (1U << 3) 235 #define ECR_SERVINTR (1U << 2) 236 #define ECR_F_FULL (1U << 1) 237 #define ECR_F_EMPTY (1U << 0) 238 239 /*--- Private data -----------------------------------------------------*/ 240 241 /** 242 * enum parport_ip32_irq_mode - operation mode of interrupt handler 243 * @PARPORT_IP32_IRQ_FWD: forward interrupt to the upper parport layer 244 * @PARPORT_IP32_IRQ_HERE: interrupt is handled locally 245 */ 246 enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE }; 247 248 /** 249 * struct parport_ip32_private - private stuff for &struct parport 250 * @regs: register addresses 251 * @dcr_cache: cached contents of DCR 252 * @dcr_writable: bit mask of writable DCR bits 253 * @pword: number of bytes per PWord 254 * @fifo_depth: number of PWords that FIFO will hold 255 * @readIntrThreshold: minimum number of PWords we can read 256 * if we get an interrupt 257 * @writeIntrThreshold: minimum number of PWords we can write 258 * if we get an interrupt 259 * @irq_mode: operation mode of interrupt handler for this port 260 * @irq_complete: mutex used to wait for an interrupt to occur 261 */ 262 struct parport_ip32_private { 263 struct parport_ip32_regs regs; 264 unsigned int dcr_cache; 265 unsigned int dcr_writable; 266 unsigned int pword; 267 unsigned int fifo_depth; 268 unsigned int readIntrThreshold; 269 unsigned int writeIntrThreshold; 270 enum parport_ip32_irq_mode irq_mode; 271 struct completion irq_complete; 272 }; 273 274 /*--- Debug code -------------------------------------------------------*/ 275 276 /* 277 * pr_debug1 - print debug messages 278 * 279 * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1 280 */ 281 #if DEBUG_PARPORT_IP32 >= 1 282 # define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__) 283 #else /* DEBUG_PARPORT_IP32 < 1 */ 284 # define pr_debug1(...) do { } while (0) 285 #endif 286 287 /* 288 * pr_trace, pr_trace1 - trace function calls 289 * @p: pointer to &struct parport 290 * @fmt: printk format string 291 * @...: parameters for format string 292 * 293 * Macros used to trace function calls. The given string is formatted after 294 * function name. pr_trace() uses pr_debug(), and pr_trace1() uses 295 * pr_debug1(). __pr_trace() is the low-level macro and is not to be used 296 * directly. 297 */ 298 #define __pr_trace(pr, p, fmt, ...) \ 299 pr("%s: %s" fmt "\n", \ 300 ({ const struct parport *__p = (p); \ 301 __p ? __p->name : "parport_ip32"; }), \ 302 __func__ , ##__VA_ARGS__) 303 #define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__) 304 #define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__) 305 306 /* 307 * __pr_probe, pr_probe - print message if @verbose_probing is true 308 * @p: pointer to &struct parport 309 * @fmt: printk format string 310 * @...: parameters for format string 311 * 312 * For new lines, use pr_probe(). Use __pr_probe() for continued lines. 313 */ 314 #define __pr_probe(...) \ 315 do { if (verbose_probing) printk(__VA_ARGS__); } while (0) 316 #define pr_probe(p, fmt, ...) \ 317 __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__) 318 319 /* 320 * parport_ip32_dump_state - print register status of parport 321 * @p: pointer to &struct parport 322 * @str: string to add in message 323 * @show_ecp_config: shall we dump ECP configuration registers too? 324 * 325 * This function is only here for debugging purpose, and should be used with 326 * care. Reading the parallel port registers may have undesired side effects. 327 * Especially if @show_ecp_config is true, the parallel port is resetted. 328 * This function is only defined if %DEBUG_PARPORT_IP32 >= 2. 329 */ 330 #if DEBUG_PARPORT_IP32 >= 2 331 static void parport_ip32_dump_state(struct parport *p, char *str, 332 unsigned int show_ecp_config) 333 { 334 struct parport_ip32_private * const priv = p->physport->private_data; 335 unsigned int i; 336 337 printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str); 338 { 339 static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF", 340 "ECP", "EPP", "???", 341 "TST", "CFG"}; 342 unsigned int ecr = readb(priv->regs.ecr); 343 printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr); 344 printk(" %s", 345 ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); 346 if (ecr & ECR_nERRINTR) 347 printk(",nErrIntrEn"); 348 if (ecr & ECR_DMAEN) 349 printk(",dmaEn"); 350 if (ecr & ECR_SERVINTR) 351 printk(",serviceIntr"); 352 if (ecr & ECR_F_FULL) 353 printk(",f_full"); 354 if (ecr & ECR_F_EMPTY) 355 printk(",f_empty"); 356 printk("\n"); 357 } 358 if (show_ecp_config) { 359 unsigned int oecr, cnfgA, cnfgB; 360 oecr = readb(priv->regs.ecr); 361 writeb(ECR_MODE_PS2, priv->regs.ecr); 362 writeb(ECR_MODE_CFG, priv->regs.ecr); 363 cnfgA = readb(priv->regs.cnfgA); 364 cnfgB = readb(priv->regs.cnfgB); 365 writeb(ECR_MODE_PS2, priv->regs.ecr); 366 writeb(oecr, priv->regs.ecr); 367 printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA); 368 printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); 369 switch (cnfgA & CNFGA_ID_MASK) { 370 case CNFGA_ID_8: 371 printk(",8 bits"); 372 break; 373 case CNFGA_ID_16: 374 printk(",16 bits"); 375 break; 376 case CNFGA_ID_32: 377 printk(",32 bits"); 378 break; 379 default: 380 printk(",unknown ID"); 381 break; 382 } 383 if (!(cnfgA & CNFGA_nBYTEINTRANS)) 384 printk(",ByteInTrans"); 385 if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8) 386 printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT, 387 ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); 388 printk("\n"); 389 printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB); 390 printk(" irq=%u,dma=%u", 391 (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, 392 (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); 393 printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); 394 if (cnfgB & CNFGB_COMPRESS) 395 printk(",compress"); 396 printk("\n"); 397 } 398 for (i = 0; i < 2; i++) { 399 unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr); 400 printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x", 401 i ? "soft" : "hard", dcr); 402 printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); 403 if (dcr & DCR_IRQ) 404 printk(",ackIntEn"); 405 if (!(dcr & DCR_SELECT)) 406 printk(",nSelectIn"); 407 if (dcr & DCR_nINIT) 408 printk(",nInit"); 409 if (!(dcr & DCR_AUTOFD)) 410 printk(",nAutoFD"); 411 if (!(dcr & DCR_STROBE)) 412 printk(",nStrobe"); 413 printk("\n"); 414 } 415 #define sep (f++ ? ',' : ' ') 416 { 417 unsigned int f = 0; 418 unsigned int dsr = readb(priv->regs.dsr); 419 printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr); 420 if (!(dsr & DSR_nBUSY)) 421 printk("%cBusy", sep); 422 if (dsr & DSR_nACK) 423 printk("%cnAck", sep); 424 if (dsr & DSR_PERROR) 425 printk("%cPError", sep); 426 if (dsr & DSR_SELECT) 427 printk("%cSelect", sep); 428 if (dsr & DSR_nFAULT) 429 printk("%cnFault", sep); 430 if (!(dsr & DSR_nPRINT)) 431 printk("%c(Print)", sep); 432 if (dsr & DSR_TIMEOUT) 433 printk("%cTimeout", sep); 434 printk("\n"); 435 } 436 #undef sep 437 } 438 #else /* DEBUG_PARPORT_IP32 < 2 */ 439 #define parport_ip32_dump_state(...) do { } while (0) 440 #endif 441 442 /* 443 * CHECK_EXTRA_BITS - track and log extra bits 444 * @p: pointer to &struct parport 445 * @b: byte to inspect 446 * @m: bit mask of authorized bits 447 * 448 * This is used to track and log extra bits that should not be there in 449 * parport_ip32_write_control() and parport_ip32_frob_control(). It is only 450 * defined if %DEBUG_PARPORT_IP32 >= 1. 451 */ 452 #if DEBUG_PARPORT_IP32 >= 1 453 #define CHECK_EXTRA_BITS(p, b, m) \ 454 do { \ 455 unsigned int __b = (b), __m = (m); \ 456 if (__b & ~__m) \ 457 pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \ 458 "0x%02x/0x%02x\n", \ 459 (p)->name, __func__, #b, __b, __m); \ 460 } while (0) 461 #else /* DEBUG_PARPORT_IP32 < 1 */ 462 #define CHECK_EXTRA_BITS(...) do { } while (0) 463 #endif 464 465 /*--- IP32 parallel port DMA operations --------------------------------*/ 466 467 /** 468 * struct parport_ip32_dma_data - private data needed for DMA operation 469 * @dir: DMA direction (from or to device) 470 * @buf: buffer physical address 471 * @len: buffer length 472 * @next: address of next bytes to DMA transfer 473 * @left: number of bytes remaining 474 * @ctx: next context to write (0: context_a; 1: context_b) 475 * @irq_on: are the DMA IRQs currently enabled? 476 * @lock: spinlock to protect access to the structure 477 */ 478 struct parport_ip32_dma_data { 479 enum dma_data_direction dir; 480 dma_addr_t buf; 481 dma_addr_t next; 482 size_t len; 483 size_t left; 484 unsigned int ctx; 485 unsigned int irq_on; 486 spinlock_t lock; 487 }; 488 static struct parport_ip32_dma_data parport_ip32_dma; 489 490 /** 491 * parport_ip32_dma_setup_context - setup next DMA context 492 * @limit: maximum data size for the context 493 * 494 * The alignment constraints must be verified in caller function, and the 495 * parameter @limit must be set accordingly. 496 */ 497 static void parport_ip32_dma_setup_context(unsigned int limit) 498 { 499 unsigned long flags; 500 501 spin_lock_irqsave(&parport_ip32_dma.lock, flags); 502 if (parport_ip32_dma.left > 0) { 503 /* Note: ctxreg is "volatile" here only because 504 * mace->perif.ctrl.parport.context_a and context_b are 505 * "volatile". */ 506 volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ? 507 &mace->perif.ctrl.parport.context_a : 508 &mace->perif.ctrl.parport.context_b; 509 u64 count; 510 u64 ctxval; 511 if (parport_ip32_dma.left <= limit) { 512 count = parport_ip32_dma.left; 513 ctxval = MACEPAR_CONTEXT_LASTFLAG; 514 } else { 515 count = limit; 516 ctxval = 0; 517 } 518 519 pr_trace(NULL, 520 "(%u): 0x%04x:0x%04x, %u -> %u%s", 521 limit, 522 (unsigned int)parport_ip32_dma.buf, 523 (unsigned int)parport_ip32_dma.next, 524 (unsigned int)count, 525 parport_ip32_dma.ctx, ctxval ? "*" : ""); 526 527 ctxval |= parport_ip32_dma.next & 528 MACEPAR_CONTEXT_BASEADDR_MASK; 529 ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) & 530 MACEPAR_CONTEXT_DATALEN_MASK; 531 writeq(ctxval, ctxreg); 532 parport_ip32_dma.next += count; 533 parport_ip32_dma.left -= count; 534 parport_ip32_dma.ctx ^= 1U; 535 } 536 /* If there is nothing more to send, disable IRQs to avoid to 537 * face an IRQ storm which can lock the machine. Disable them 538 * only once. */ 539 if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) { 540 pr_debug(PPIP32 "IRQ off (ctx)\n"); 541 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ); 542 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ); 543 parport_ip32_dma.irq_on = 0; 544 } 545 spin_unlock_irqrestore(&parport_ip32_dma.lock, flags); 546 } 547 548 /** 549 * parport_ip32_dma_interrupt - DMA interrupt handler 550 * @irq: interrupt number 551 * @dev_id: unused 552 */ 553 static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id) 554 { 555 if (parport_ip32_dma.left) 556 pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx); 557 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND); 558 return IRQ_HANDLED; 559 } 560 561 #if DEBUG_PARPORT_IP32 562 static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id) 563 { 564 pr_trace1(NULL, "(%d)", irq); 565 return IRQ_HANDLED; 566 } 567 #endif 568 569 /** 570 * parport_ip32_dma_start - begins a DMA transfer 571 * @p: partport to work on 572 * @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE 573 * @addr: pointer to data buffer 574 * @count: buffer size 575 * 576 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 577 * correctly balanced. 578 */ 579 static int parport_ip32_dma_start(struct parport *p, 580 enum dma_data_direction dir, void *addr, size_t count) 581 { 582 unsigned int limit; 583 u64 ctrl; 584 585 pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count); 586 587 /* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must 588 * be 64 bytes aligned. */ 589 BUG_ON(dir != DMA_TO_DEVICE); 590 591 /* Reset DMA controller */ 592 ctrl = MACEPAR_CTLSTAT_RESET; 593 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 594 595 /* DMA IRQs should normally be enabled */ 596 if (!parport_ip32_dma.irq_on) { 597 WARN_ON(1); 598 enable_irq(MACEISA_PAR_CTXA_IRQ); 599 enable_irq(MACEISA_PAR_CTXB_IRQ); 600 parport_ip32_dma.irq_on = 1; 601 } 602 603 /* Prepare DMA pointers */ 604 parport_ip32_dma.dir = dir; 605 parport_ip32_dma.buf = dma_map_single(&p->bus_dev, addr, count, dir); 606 parport_ip32_dma.len = count; 607 parport_ip32_dma.next = parport_ip32_dma.buf; 608 parport_ip32_dma.left = parport_ip32_dma.len; 609 parport_ip32_dma.ctx = 0; 610 611 /* Setup DMA direction and first two contexts */ 612 ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION; 613 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 614 /* Single transfer should not cross a 4K page boundary */ 615 limit = MACEPAR_CONTEXT_DATA_BOUND - 616 (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1)); 617 parport_ip32_dma_setup_context(limit); 618 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND); 619 620 /* Real start of DMA transfer */ 621 ctrl |= MACEPAR_CTLSTAT_ENABLE; 622 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 623 624 return 0; 625 } 626 627 /** 628 * parport_ip32_dma_stop - ends a running DMA transfer 629 * @p: partport to work on 630 * 631 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 632 * correctly balanced. 633 */ 634 static void parport_ip32_dma_stop(struct parport *p) 635 { 636 u64 ctx_a; 637 u64 ctx_b; 638 u64 ctrl; 639 u64 diag; 640 size_t res[2]; /* {[0] = res_a, [1] = res_b} */ 641 642 pr_trace(NULL, "()"); 643 644 /* Disable IRQs */ 645 spin_lock_irq(&parport_ip32_dma.lock); 646 if (parport_ip32_dma.irq_on) { 647 pr_debug(PPIP32 "IRQ off (stop)\n"); 648 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ); 649 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ); 650 parport_ip32_dma.irq_on = 0; 651 } 652 spin_unlock_irq(&parport_ip32_dma.lock); 653 /* Force IRQ synchronization, even if the IRQs were disabled 654 * elsewhere. */ 655 synchronize_irq(MACEISA_PAR_CTXA_IRQ); 656 synchronize_irq(MACEISA_PAR_CTXB_IRQ); 657 658 /* Stop DMA transfer */ 659 ctrl = readq(&mace->perif.ctrl.parport.cntlstat); 660 ctrl &= ~MACEPAR_CTLSTAT_ENABLE; 661 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 662 663 /* Adjust residue (parport_ip32_dma.left) */ 664 ctx_a = readq(&mace->perif.ctrl.parport.context_a); 665 ctx_b = readq(&mace->perif.ctrl.parport.context_b); 666 ctrl = readq(&mace->perif.ctrl.parport.cntlstat); 667 diag = readq(&mace->perif.ctrl.parport.diagnostic); 668 res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ? 669 1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >> 670 MACEPAR_CONTEXT_DATALEN_SHIFT) : 671 0; 672 res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ? 673 1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >> 674 MACEPAR_CONTEXT_DATALEN_SHIFT) : 675 0; 676 if (diag & MACEPAR_DIAG_DMACTIVE) 677 res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] = 678 1 + ((diag & MACEPAR_DIAG_CTRMASK) >> 679 MACEPAR_DIAG_CTRSHIFT); 680 parport_ip32_dma.left += res[0] + res[1]; 681 682 /* Reset DMA controller, and re-enable IRQs */ 683 ctrl = MACEPAR_CTLSTAT_RESET; 684 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 685 pr_debug(PPIP32 "IRQ on (stop)\n"); 686 enable_irq(MACEISA_PAR_CTXA_IRQ); 687 enable_irq(MACEISA_PAR_CTXB_IRQ); 688 parport_ip32_dma.irq_on = 1; 689 690 dma_unmap_single(&p->bus_dev, parport_ip32_dma.buf, 691 parport_ip32_dma.len, parport_ip32_dma.dir); 692 } 693 694 /** 695 * parport_ip32_dma_get_residue - get residue from last DMA transfer 696 * 697 * Returns the number of bytes remaining from last DMA transfer. 698 */ 699 static inline size_t parport_ip32_dma_get_residue(void) 700 { 701 return parport_ip32_dma.left; 702 } 703 704 /** 705 * parport_ip32_dma_register - initialize DMA engine 706 * 707 * Returns zero for success. 708 */ 709 static int parport_ip32_dma_register(void) 710 { 711 int err; 712 713 spin_lock_init(&parport_ip32_dma.lock); 714 parport_ip32_dma.irq_on = 1; 715 716 /* Reset DMA controller */ 717 writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat); 718 719 /* Request IRQs */ 720 err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt, 721 0, "parport_ip32", NULL); 722 if (err) 723 goto fail_a; 724 err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt, 725 0, "parport_ip32", NULL); 726 if (err) 727 goto fail_b; 728 #if DEBUG_PARPORT_IP32 729 /* FIXME - what is this IRQ for? */ 730 err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt, 731 0, "parport_ip32", NULL); 732 if (err) 733 goto fail_merr; 734 #endif 735 return 0; 736 737 #if DEBUG_PARPORT_IP32 738 fail_merr: 739 free_irq(MACEISA_PAR_CTXB_IRQ, NULL); 740 #endif 741 fail_b: 742 free_irq(MACEISA_PAR_CTXA_IRQ, NULL); 743 fail_a: 744 return err; 745 } 746 747 /** 748 * parport_ip32_dma_unregister - release and free resources for DMA engine 749 */ 750 static void parport_ip32_dma_unregister(void) 751 { 752 #if DEBUG_PARPORT_IP32 753 free_irq(MACEISA_PAR_MERR_IRQ, NULL); 754 #endif 755 free_irq(MACEISA_PAR_CTXB_IRQ, NULL); 756 free_irq(MACEISA_PAR_CTXA_IRQ, NULL); 757 } 758 759 /*--- Interrupt handlers and associates --------------------------------*/ 760 761 /** 762 * parport_ip32_wakeup - wakes up code waiting for an interrupt 763 * @p: pointer to &struct parport 764 */ 765 static inline void parport_ip32_wakeup(struct parport *p) 766 { 767 struct parport_ip32_private * const priv = p->physport->private_data; 768 complete(&priv->irq_complete); 769 } 770 771 /** 772 * parport_ip32_interrupt - interrupt handler 773 * @irq: interrupt number 774 * @dev_id: pointer to &struct parport 775 * 776 * Caught interrupts are forwarded to the upper parport layer if IRQ_mode is 777 * %PARPORT_IP32_IRQ_FWD. 778 */ 779 static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id) 780 { 781 struct parport * const p = dev_id; 782 struct parport_ip32_private * const priv = p->physport->private_data; 783 enum parport_ip32_irq_mode irq_mode = priv->irq_mode; 784 785 switch (irq_mode) { 786 case PARPORT_IP32_IRQ_FWD: 787 return parport_irq_handler(irq, dev_id); 788 789 case PARPORT_IP32_IRQ_HERE: 790 parport_ip32_wakeup(p); 791 break; 792 } 793 794 return IRQ_HANDLED; 795 } 796 797 /*--- Some utility function to manipulate ECR register -----------------*/ 798 799 /** 800 * parport_ip32_read_econtrol - read contents of the ECR register 801 * @p: pointer to &struct parport 802 */ 803 static inline unsigned int parport_ip32_read_econtrol(struct parport *p) 804 { 805 struct parport_ip32_private * const priv = p->physport->private_data; 806 return readb(priv->regs.ecr); 807 } 808 809 /** 810 * parport_ip32_write_econtrol - write new contents to the ECR register 811 * @p: pointer to &struct parport 812 * @c: new value to write 813 */ 814 static inline void parport_ip32_write_econtrol(struct parport *p, 815 unsigned int c) 816 { 817 struct parport_ip32_private * const priv = p->physport->private_data; 818 writeb(c, priv->regs.ecr); 819 } 820 821 /** 822 * parport_ip32_frob_econtrol - change bits from the ECR register 823 * @p: pointer to &struct parport 824 * @mask: bit mask of bits to change 825 * @val: new value for changed bits 826 * 827 * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits 828 * in @val, and write the result to the ECR. 829 */ 830 static inline void parport_ip32_frob_econtrol(struct parport *p, 831 unsigned int mask, 832 unsigned int val) 833 { 834 unsigned int c; 835 c = (parport_ip32_read_econtrol(p) & ~mask) ^ val; 836 parport_ip32_write_econtrol(p, c); 837 } 838 839 /** 840 * parport_ip32_set_mode - change mode of ECP port 841 * @p: pointer to &struct parport 842 * @mode: new mode to write in ECR 843 * 844 * ECR is reset in a sane state (interrupts and DMA disabled), and placed in 845 * mode @mode. Go through PS2 mode if needed. 846 */ 847 static void parport_ip32_set_mode(struct parport *p, unsigned int mode) 848 { 849 unsigned int omode; 850 851 mode &= ECR_MODE_MASK; 852 omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK; 853 854 if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2 855 || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) { 856 /* We have to go through PS2 mode */ 857 unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 858 parport_ip32_write_econtrol(p, ecr); 859 } 860 parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR); 861 } 862 863 /*--- Basic functions needed for parport -------------------------------*/ 864 865 /** 866 * parport_ip32_read_data - return current contents of the DATA register 867 * @p: pointer to &struct parport 868 */ 869 static inline unsigned char parport_ip32_read_data(struct parport *p) 870 { 871 struct parport_ip32_private * const priv = p->physport->private_data; 872 return readb(priv->regs.data); 873 } 874 875 /** 876 * parport_ip32_write_data - set new contents for the DATA register 877 * @p: pointer to &struct parport 878 * @d: new value to write 879 */ 880 static inline void parport_ip32_write_data(struct parport *p, unsigned char d) 881 { 882 struct parport_ip32_private * const priv = p->physport->private_data; 883 writeb(d, priv->regs.data); 884 } 885 886 /** 887 * parport_ip32_read_status - return current contents of the DSR register 888 * @p: pointer to &struct parport 889 */ 890 static inline unsigned char parport_ip32_read_status(struct parport *p) 891 { 892 struct parport_ip32_private * const priv = p->physport->private_data; 893 return readb(priv->regs.dsr); 894 } 895 896 /** 897 * __parport_ip32_read_control - return cached contents of the DCR register 898 * @p: pointer to &struct parport 899 */ 900 static inline unsigned int __parport_ip32_read_control(struct parport *p) 901 { 902 struct parport_ip32_private * const priv = p->physport->private_data; 903 return priv->dcr_cache; /* use soft copy */ 904 } 905 906 /** 907 * __parport_ip32_write_control - set new contents for the DCR register 908 * @p: pointer to &struct parport 909 * @c: new value to write 910 */ 911 static inline void __parport_ip32_write_control(struct parport *p, 912 unsigned int c) 913 { 914 struct parport_ip32_private * const priv = p->physport->private_data; 915 CHECK_EXTRA_BITS(p, c, priv->dcr_writable); 916 c &= priv->dcr_writable; /* only writable bits */ 917 writeb(c, priv->regs.dcr); 918 priv->dcr_cache = c; /* update soft copy */ 919 } 920 921 /** 922 * __parport_ip32_frob_control - change bits from the DCR register 923 * @p: pointer to &struct parport 924 * @mask: bit mask of bits to change 925 * @val: new value for changed bits 926 * 927 * This is equivalent to read from the DCR, mask out the bits in @mask, 928 * exclusive-or with the bits in @val, and write the result to the DCR. 929 * Actually, the cached contents of the DCR is used. 930 */ 931 static inline void __parport_ip32_frob_control(struct parport *p, 932 unsigned int mask, 933 unsigned int val) 934 { 935 unsigned int c; 936 c = (__parport_ip32_read_control(p) & ~mask) ^ val; 937 __parport_ip32_write_control(p, c); 938 } 939 940 /** 941 * parport_ip32_read_control - return cached contents of the DCR register 942 * @p: pointer to &struct parport 943 * 944 * The return value is masked so as to only return the value of %DCR_STROBE, 945 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 946 */ 947 static inline unsigned char parport_ip32_read_control(struct parport *p) 948 { 949 const unsigned int rm = 950 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 951 return __parport_ip32_read_control(p) & rm; 952 } 953 954 /** 955 * parport_ip32_write_control - set new contents for the DCR register 956 * @p: pointer to &struct parport 957 * @c: new value to write 958 * 959 * The value is masked so as to only change the value of %DCR_STROBE, 960 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 961 */ 962 static inline void parport_ip32_write_control(struct parport *p, 963 unsigned char c) 964 { 965 const unsigned int wm = 966 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 967 CHECK_EXTRA_BITS(p, c, wm); 968 __parport_ip32_frob_control(p, wm, c & wm); 969 } 970 971 /** 972 * parport_ip32_frob_control - change bits from the DCR register 973 * @p: pointer to &struct parport 974 * @mask: bit mask of bits to change 975 * @val: new value for changed bits 976 * 977 * This differs from __parport_ip32_frob_control() in that it only allows to 978 * change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 979 */ 980 static inline unsigned char parport_ip32_frob_control(struct parport *p, 981 unsigned char mask, 982 unsigned char val) 983 { 984 const unsigned int wm = 985 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 986 CHECK_EXTRA_BITS(p, mask, wm); 987 CHECK_EXTRA_BITS(p, val, wm); 988 __parport_ip32_frob_control(p, mask & wm, val & wm); 989 return parport_ip32_read_control(p); 990 } 991 992 /** 993 * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK 994 * @p: pointer to &struct parport 995 */ 996 static inline void parport_ip32_disable_irq(struct parport *p) 997 { 998 __parport_ip32_frob_control(p, DCR_IRQ, 0); 999 } 1000 1001 /** 1002 * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK 1003 * @p: pointer to &struct parport 1004 */ 1005 static inline void parport_ip32_enable_irq(struct parport *p) 1006 { 1007 __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ); 1008 } 1009 1010 /** 1011 * parport_ip32_data_forward - enable host-to-peripheral communications 1012 * @p: pointer to &struct parport 1013 * 1014 * Enable the data line drivers, for 8-bit host-to-peripheral communications. 1015 */ 1016 static inline void parport_ip32_data_forward(struct parport *p) 1017 { 1018 __parport_ip32_frob_control(p, DCR_DIR, 0); 1019 } 1020 1021 /** 1022 * parport_ip32_data_reverse - enable peripheral-to-host communications 1023 * @p: pointer to &struct parport 1024 * 1025 * Place the data bus in a high impedance state, if @p->modes has the 1026 * PARPORT_MODE_TRISTATE bit set. 1027 */ 1028 static inline void parport_ip32_data_reverse(struct parport *p) 1029 { 1030 __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR); 1031 } 1032 1033 /** 1034 * parport_ip32_init_state - for core parport code 1035 * @dev: pointer to &struct pardevice 1036 * @s: pointer to &struct parport_state to initialize 1037 */ 1038 static void parport_ip32_init_state(struct pardevice *dev, 1039 struct parport_state *s) 1040 { 1041 s->u.ip32.dcr = DCR_SELECT | DCR_nINIT; 1042 s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 1043 } 1044 1045 /** 1046 * parport_ip32_save_state - for core parport code 1047 * @p: pointer to &struct parport 1048 * @s: pointer to &struct parport_state to save state to 1049 */ 1050 static void parport_ip32_save_state(struct parport *p, 1051 struct parport_state *s) 1052 { 1053 s->u.ip32.dcr = __parport_ip32_read_control(p); 1054 s->u.ip32.ecr = parport_ip32_read_econtrol(p); 1055 } 1056 1057 /** 1058 * parport_ip32_restore_state - for core parport code 1059 * @p: pointer to &struct parport 1060 * @s: pointer to &struct parport_state to restore state from 1061 */ 1062 static void parport_ip32_restore_state(struct parport *p, 1063 struct parport_state *s) 1064 { 1065 parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK); 1066 parport_ip32_write_econtrol(p, s->u.ip32.ecr); 1067 __parport_ip32_write_control(p, s->u.ip32.dcr); 1068 } 1069 1070 /*--- EPP mode functions -----------------------------------------------*/ 1071 1072 /** 1073 * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode 1074 * @p: pointer to &struct parport 1075 * 1076 * Returns 1 if the Timeout bit is clear, and 0 otherwise. 1077 */ 1078 static unsigned int parport_ip32_clear_epp_timeout(struct parport *p) 1079 { 1080 struct parport_ip32_private * const priv = p->physport->private_data; 1081 unsigned int cleared; 1082 1083 if (!(parport_ip32_read_status(p) & DSR_TIMEOUT)) 1084 cleared = 1; 1085 else { 1086 unsigned int r; 1087 /* To clear timeout some chips require double read */ 1088 parport_ip32_read_status(p); 1089 r = parport_ip32_read_status(p); 1090 /* Some reset by writing 1 */ 1091 writeb(r | DSR_TIMEOUT, priv->regs.dsr); 1092 /* Others by writing 0 */ 1093 writeb(r & ~DSR_TIMEOUT, priv->regs.dsr); 1094 1095 r = parport_ip32_read_status(p); 1096 cleared = !(r & DSR_TIMEOUT); 1097 } 1098 1099 pr_trace(p, "(): %s", cleared ? "cleared" : "failed"); 1100 return cleared; 1101 } 1102 1103 /** 1104 * parport_ip32_epp_read - generic EPP read function 1105 * @eppreg: I/O register to read from 1106 * @p: pointer to &struct parport 1107 * @buf: buffer to store read data 1108 * @len: length of buffer @buf 1109 * @flags: may be PARPORT_EPP_FAST 1110 */ 1111 static size_t parport_ip32_epp_read(void __iomem *eppreg, 1112 struct parport *p, void *buf, 1113 size_t len, int flags) 1114 { 1115 struct parport_ip32_private * const priv = p->physport->private_data; 1116 size_t got; 1117 parport_ip32_set_mode(p, ECR_MODE_EPP); 1118 parport_ip32_data_reverse(p); 1119 parport_ip32_write_control(p, DCR_nINIT); 1120 if ((flags & PARPORT_EPP_FAST) && (len > 1)) { 1121 readsb(eppreg, buf, len); 1122 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1123 parport_ip32_clear_epp_timeout(p); 1124 return -EIO; 1125 } 1126 got = len; 1127 } else { 1128 u8 *bufp = buf; 1129 for (got = 0; got < len; got++) { 1130 *bufp++ = readb(eppreg); 1131 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1132 parport_ip32_clear_epp_timeout(p); 1133 break; 1134 } 1135 } 1136 } 1137 parport_ip32_data_forward(p); 1138 parport_ip32_set_mode(p, ECR_MODE_PS2); 1139 return got; 1140 } 1141 1142 /** 1143 * parport_ip32_epp_write - generic EPP write function 1144 * @eppreg: I/O register to write to 1145 * @p: pointer to &struct parport 1146 * @buf: buffer of data to write 1147 * @len: length of buffer @buf 1148 * @flags: may be PARPORT_EPP_FAST 1149 */ 1150 static size_t parport_ip32_epp_write(void __iomem *eppreg, 1151 struct parport *p, const void *buf, 1152 size_t len, int flags) 1153 { 1154 struct parport_ip32_private * const priv = p->physport->private_data; 1155 size_t written; 1156 parport_ip32_set_mode(p, ECR_MODE_EPP); 1157 parport_ip32_data_forward(p); 1158 parport_ip32_write_control(p, DCR_nINIT); 1159 if ((flags & PARPORT_EPP_FAST) && (len > 1)) { 1160 writesb(eppreg, buf, len); 1161 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1162 parport_ip32_clear_epp_timeout(p); 1163 return -EIO; 1164 } 1165 written = len; 1166 } else { 1167 const u8 *bufp = buf; 1168 for (written = 0; written < len; written++) { 1169 writeb(*bufp++, eppreg); 1170 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1171 parport_ip32_clear_epp_timeout(p); 1172 break; 1173 } 1174 } 1175 } 1176 parport_ip32_set_mode(p, ECR_MODE_PS2); 1177 return written; 1178 } 1179 1180 /** 1181 * parport_ip32_epp_read_data - read a block of data in EPP mode 1182 * @p: pointer to &struct parport 1183 * @buf: buffer to store read data 1184 * @len: length of buffer @buf 1185 * @flags: may be PARPORT_EPP_FAST 1186 */ 1187 static size_t parport_ip32_epp_read_data(struct parport *p, void *buf, 1188 size_t len, int flags) 1189 { 1190 struct parport_ip32_private * const priv = p->physport->private_data; 1191 return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags); 1192 } 1193 1194 /** 1195 * parport_ip32_epp_write_data - write a block of data in EPP mode 1196 * @p: pointer to &struct parport 1197 * @buf: buffer of data to write 1198 * @len: length of buffer @buf 1199 * @flags: may be PARPORT_EPP_FAST 1200 */ 1201 static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf, 1202 size_t len, int flags) 1203 { 1204 struct parport_ip32_private * const priv = p->physport->private_data; 1205 return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags); 1206 } 1207 1208 /** 1209 * parport_ip32_epp_read_addr - read a block of addresses in EPP mode 1210 * @p: pointer to &struct parport 1211 * @buf: buffer to store read data 1212 * @len: length of buffer @buf 1213 * @flags: may be PARPORT_EPP_FAST 1214 */ 1215 static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf, 1216 size_t len, int flags) 1217 { 1218 struct parport_ip32_private * const priv = p->physport->private_data; 1219 return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags); 1220 } 1221 1222 /** 1223 * parport_ip32_epp_write_addr - write a block of addresses in EPP mode 1224 * @p: pointer to &struct parport 1225 * @buf: buffer of data to write 1226 * @len: length of buffer @buf 1227 * @flags: may be PARPORT_EPP_FAST 1228 */ 1229 static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf, 1230 size_t len, int flags) 1231 { 1232 struct parport_ip32_private * const priv = p->physport->private_data; 1233 return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags); 1234 } 1235 1236 /*--- ECP mode functions (FIFO) ----------------------------------------*/ 1237 1238 /** 1239 * parport_ip32_fifo_wait_break - check if the waiting function should return 1240 * @p: pointer to &struct parport 1241 * @expire: timeout expiring date, in jiffies 1242 * 1243 * parport_ip32_fifo_wait_break() checks if the waiting function should return 1244 * immediately or not. The break conditions are: 1245 * - expired timeout; 1246 * - a pending signal; 1247 * - nFault asserted low. 1248 * This function also calls cond_resched(). 1249 */ 1250 static unsigned int parport_ip32_fifo_wait_break(struct parport *p, 1251 unsigned long expire) 1252 { 1253 cond_resched(); 1254 if (time_after(jiffies, expire)) { 1255 pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name); 1256 return 1; 1257 } 1258 if (signal_pending(current)) { 1259 pr_debug1(PPIP32 "%s: Signal pending\n", p->name); 1260 return 1; 1261 } 1262 if (!(parport_ip32_read_status(p) & DSR_nFAULT)) { 1263 pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name); 1264 return 1; 1265 } 1266 return 0; 1267 } 1268 1269 /** 1270 * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling) 1271 * @p: pointer to &struct parport 1272 * 1273 * Returns the number of bytes that can safely be written in the FIFO. A 1274 * return value of zero means that the calling function should terminate as 1275 * fast as possible. 1276 */ 1277 static unsigned int parport_ip32_fwp_wait_polling(struct parport *p) 1278 { 1279 struct parport_ip32_private * const priv = p->physport->private_data; 1280 struct parport * const physport = p->physport; 1281 unsigned long expire; 1282 unsigned int count; 1283 unsigned int ecr; 1284 1285 expire = jiffies + physport->cad->timeout; 1286 count = 0; 1287 while (1) { 1288 if (parport_ip32_fifo_wait_break(p, expire)) 1289 break; 1290 1291 /* Check FIFO state. We do nothing when the FIFO is nor full, 1292 * nor empty. It appears that the FIFO full bit is not always 1293 * reliable, the FIFO state is sometimes wrongly reported, and 1294 * the chip gets confused if we give it another byte. */ 1295 ecr = parport_ip32_read_econtrol(p); 1296 if (ecr & ECR_F_EMPTY) { 1297 /* FIFO is empty, fill it up */ 1298 count = priv->fifo_depth; 1299 break; 1300 } 1301 1302 /* Wait a moment... */ 1303 udelay(FIFO_POLLING_INTERVAL); 1304 } /* while (1) */ 1305 1306 return count; 1307 } 1308 1309 /** 1310 * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven) 1311 * @p: pointer to &struct parport 1312 * 1313 * Returns the number of bytes that can safely be written in the FIFO. A 1314 * return value of zero means that the calling function should terminate as 1315 * fast as possible. 1316 */ 1317 static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p) 1318 { 1319 static unsigned int lost_interrupt = 0; 1320 struct parport_ip32_private * const priv = p->physport->private_data; 1321 struct parport * const physport = p->physport; 1322 unsigned long nfault_timeout; 1323 unsigned long expire; 1324 unsigned int count; 1325 unsigned int ecr; 1326 1327 nfault_timeout = min((unsigned long)physport->cad->timeout, 1328 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT)); 1329 expire = jiffies + physport->cad->timeout; 1330 count = 0; 1331 while (1) { 1332 if (parport_ip32_fifo_wait_break(p, expire)) 1333 break; 1334 1335 /* Initialize mutex used to take interrupts into account */ 1336 reinit_completion(&priv->irq_complete); 1337 1338 /* Enable serviceIntr */ 1339 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1340 1341 /* Enabling serviceIntr while the FIFO is empty does not 1342 * always generate an interrupt, so check for emptiness 1343 * now. */ 1344 ecr = parport_ip32_read_econtrol(p); 1345 if (!(ecr & ECR_F_EMPTY)) { 1346 /* FIFO is not empty: wait for an interrupt or a 1347 * timeout to occur */ 1348 wait_for_completion_interruptible_timeout( 1349 &priv->irq_complete, nfault_timeout); 1350 ecr = parport_ip32_read_econtrol(p); 1351 if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR) 1352 && !lost_interrupt) { 1353 printk(KERN_WARNING PPIP32 1354 "%s: lost interrupt in %s\n", 1355 p->name, __func__); 1356 lost_interrupt = 1; 1357 } 1358 } 1359 1360 /* Disable serviceIntr */ 1361 parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR); 1362 1363 /* Check FIFO state */ 1364 if (ecr & ECR_F_EMPTY) { 1365 /* FIFO is empty, fill it up */ 1366 count = priv->fifo_depth; 1367 break; 1368 } else if (ecr & ECR_SERVINTR) { 1369 /* FIFO is not empty, but we know that can safely push 1370 * writeIntrThreshold bytes into it */ 1371 count = priv->writeIntrThreshold; 1372 break; 1373 } 1374 /* FIFO is not empty, and we did not get any interrupt. 1375 * Either it's time to check for nFault, or a signal is 1376 * pending. This is verified in 1377 * parport_ip32_fifo_wait_break(), so we continue the loop. */ 1378 } /* while (1) */ 1379 1380 return count; 1381 } 1382 1383 /** 1384 * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode) 1385 * @p: pointer to &struct parport 1386 * @buf: buffer of data to write 1387 * @len: length of buffer @buf 1388 * 1389 * Uses PIO to write the contents of the buffer @buf into the parallel port 1390 * FIFO. Returns the number of bytes that were actually written. It can work 1391 * with or without the help of interrupts. The parallel port must be 1392 * correctly initialized before calling parport_ip32_fifo_write_block_pio(). 1393 */ 1394 static size_t parport_ip32_fifo_write_block_pio(struct parport *p, 1395 const void *buf, size_t len) 1396 { 1397 struct parport_ip32_private * const priv = p->physport->private_data; 1398 const u8 *bufp = buf; 1399 size_t left = len; 1400 1401 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1402 1403 while (left > 0) { 1404 unsigned int count; 1405 1406 count = (p->irq == PARPORT_IRQ_NONE) ? 1407 parport_ip32_fwp_wait_polling(p) : 1408 parport_ip32_fwp_wait_interrupt(p); 1409 if (count == 0) 1410 break; /* Transmission should be stopped */ 1411 if (count > left) 1412 count = left; 1413 if (count == 1) { 1414 writeb(*bufp, priv->regs.fifo); 1415 bufp++, left--; 1416 } else { 1417 writesb(priv->regs.fifo, bufp, count); 1418 bufp += count, left -= count; 1419 } 1420 } 1421 1422 priv->irq_mode = PARPORT_IP32_IRQ_FWD; 1423 1424 return len - left; 1425 } 1426 1427 /** 1428 * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode) 1429 * @p: pointer to &struct parport 1430 * @buf: buffer of data to write 1431 * @len: length of buffer @buf 1432 * 1433 * Uses DMA to write the contents of the buffer @buf into the parallel port 1434 * FIFO. Returns the number of bytes that were actually written. The 1435 * parallel port must be correctly initialized before calling 1436 * parport_ip32_fifo_write_block_dma(). 1437 */ 1438 static size_t parport_ip32_fifo_write_block_dma(struct parport *p, 1439 const void *buf, size_t len) 1440 { 1441 struct parport_ip32_private * const priv = p->physport->private_data; 1442 struct parport * const physport = p->physport; 1443 unsigned long nfault_timeout; 1444 unsigned long expire; 1445 size_t written; 1446 unsigned int ecr; 1447 1448 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1449 1450 parport_ip32_dma_start(p, DMA_TO_DEVICE, (void *)buf, len); 1451 reinit_completion(&priv->irq_complete); 1452 parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN); 1453 1454 nfault_timeout = min((unsigned long)physport->cad->timeout, 1455 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT)); 1456 expire = jiffies + physport->cad->timeout; 1457 while (1) { 1458 if (parport_ip32_fifo_wait_break(p, expire)) 1459 break; 1460 wait_for_completion_interruptible_timeout(&priv->irq_complete, 1461 nfault_timeout); 1462 ecr = parport_ip32_read_econtrol(p); 1463 if (ecr & ECR_SERVINTR) 1464 break; /* DMA transfer just finished */ 1465 } 1466 parport_ip32_dma_stop(p); 1467 written = len - parport_ip32_dma_get_residue(); 1468 1469 priv->irq_mode = PARPORT_IP32_IRQ_FWD; 1470 1471 return written; 1472 } 1473 1474 /** 1475 * parport_ip32_fifo_write_block - write a block of data 1476 * @p: pointer to &struct parport 1477 * @buf: buffer of data to write 1478 * @len: length of buffer @buf 1479 * 1480 * Uses PIO or DMA to write the contents of the buffer @buf into the parallel 1481 * p FIFO. Returns the number of bytes that were actually written. 1482 */ 1483 static size_t parport_ip32_fifo_write_block(struct parport *p, 1484 const void *buf, size_t len) 1485 { 1486 size_t written = 0; 1487 if (len) 1488 /* FIXME - Maybe some threshold value should be set for @len 1489 * under which we revert to PIO mode? */ 1490 written = (p->modes & PARPORT_MODE_DMA) ? 1491 parport_ip32_fifo_write_block_dma(p, buf, len) : 1492 parport_ip32_fifo_write_block_pio(p, buf, len); 1493 return written; 1494 } 1495 1496 /** 1497 * parport_ip32_drain_fifo - wait for FIFO to empty 1498 * @p: pointer to &struct parport 1499 * @timeout: timeout, in jiffies 1500 * 1501 * This function waits for FIFO to empty. It returns 1 when FIFO is empty, or 1502 * 0 if the timeout @timeout is reached before, or if a signal is pending. 1503 */ 1504 static unsigned int parport_ip32_drain_fifo(struct parport *p, 1505 unsigned long timeout) 1506 { 1507 unsigned long expire = jiffies + timeout; 1508 unsigned int polling_interval; 1509 unsigned int counter; 1510 1511 /* Busy wait for approx. 200us */ 1512 for (counter = 0; counter < 40; counter++) { 1513 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY) 1514 break; 1515 if (time_after(jiffies, expire)) 1516 break; 1517 if (signal_pending(current)) 1518 break; 1519 udelay(5); 1520 } 1521 /* Poll slowly. Polling interval starts with 1 millisecond, and is 1522 * increased exponentially until 128. */ 1523 polling_interval = 1; /* msecs */ 1524 while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) { 1525 if (time_after_eq(jiffies, expire)) 1526 break; 1527 msleep_interruptible(polling_interval); 1528 if (signal_pending(current)) 1529 break; 1530 if (polling_interval < 128) 1531 polling_interval *= 2; 1532 } 1533 1534 return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY); 1535 } 1536 1537 /** 1538 * parport_ip32_get_fifo_residue - reset FIFO 1539 * @p: pointer to &struct parport 1540 * @mode: current operation mode (ECR_MODE_PPF or ECR_MODE_ECP) 1541 * 1542 * This function resets FIFO, and returns the number of bytes remaining in it. 1543 */ 1544 static unsigned int parport_ip32_get_fifo_residue(struct parport *p, 1545 unsigned int mode) 1546 { 1547 struct parport_ip32_private * const priv = p->physport->private_data; 1548 unsigned int residue; 1549 unsigned int cnfga; 1550 1551 /* FIXME - We are missing one byte if the printer is off-line. I 1552 * don't know how to detect this. It looks that the full bit is not 1553 * always reliable. For the moment, the problem is avoided in most 1554 * cases by testing for BUSY in parport_ip32_compat_write_data(). 1555 */ 1556 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY) 1557 residue = 0; 1558 else { 1559 pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name); 1560 1561 /* Stop all transfers. 1562 * 1563 * Microsoft's document instructs to drive DCR_STROBE to 0, 1564 * but it doesn't work (at least in Compatibility mode, not 1565 * tested in ECP mode). Switching directly to Test mode (as 1566 * in parport_pc) is not an option: it does confuse the port, 1567 * ECP service interrupts are no more working after that. A 1568 * hard reset is then needed to revert to a sane state. 1569 * 1570 * Let's hope that the FIFO is really stuck and that the 1571 * peripheral doesn't wake up now. 1572 */ 1573 parport_ip32_frob_control(p, DCR_STROBE, 0); 1574 1575 /* Fill up FIFO */ 1576 for (residue = priv->fifo_depth; residue > 0; residue--) { 1577 if (parport_ip32_read_econtrol(p) & ECR_F_FULL) 1578 break; 1579 writeb(0x00, priv->regs.fifo); 1580 } 1581 } 1582 if (residue) 1583 pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n", 1584 p->name, residue, 1585 (residue == 1) ? " was" : "s were"); 1586 1587 /* Now reset the FIFO */ 1588 parport_ip32_set_mode(p, ECR_MODE_PS2); 1589 1590 /* Host recovery for ECP mode */ 1591 if (mode == ECR_MODE_ECP) { 1592 parport_ip32_data_reverse(p); 1593 parport_ip32_frob_control(p, DCR_nINIT, 0); 1594 if (parport_wait_peripheral(p, DSR_PERROR, 0)) 1595 pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n", 1596 p->name, __func__); 1597 parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE); 1598 parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT); 1599 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) 1600 pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n", 1601 p->name, __func__); 1602 } 1603 1604 /* Adjust residue if needed */ 1605 parport_ip32_set_mode(p, ECR_MODE_CFG); 1606 cnfga = readb(priv->regs.cnfgA); 1607 if (!(cnfga & CNFGA_nBYTEINTRANS)) { 1608 pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n", 1609 p->name, cnfga); 1610 pr_debug1(PPIP32 "%s: Accounting for extra byte\n", 1611 p->name); 1612 residue++; 1613 } 1614 1615 /* Don't care about partial PWords since we do not support 1616 * PWord != 1 byte. */ 1617 1618 /* Back to forward PS2 mode. */ 1619 parport_ip32_set_mode(p, ECR_MODE_PS2); 1620 parport_ip32_data_forward(p); 1621 1622 return residue; 1623 } 1624 1625 /** 1626 * parport_ip32_compat_write_data - write a block of data in SPP mode 1627 * @p: pointer to &struct parport 1628 * @buf: buffer of data to write 1629 * @len: length of buffer @buf 1630 * @flags: ignored 1631 */ 1632 static size_t parport_ip32_compat_write_data(struct parport *p, 1633 const void *buf, size_t len, 1634 int flags) 1635 { 1636 static unsigned int ready_before = 1; 1637 struct parport_ip32_private * const priv = p->physport->private_data; 1638 struct parport * const physport = p->physport; 1639 size_t written = 0; 1640 1641 /* Special case: a timeout of zero means we cannot call schedule(). 1642 * Also if O_NONBLOCK is set then use the default implementation. */ 1643 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 1644 return parport_ieee1284_write_compat(p, buf, len, flags); 1645 1646 /* Reset FIFO, go in forward mode, and disable ackIntEn */ 1647 parport_ip32_set_mode(p, ECR_MODE_PS2); 1648 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1649 parport_ip32_data_forward(p); 1650 parport_ip32_disable_irq(p); 1651 parport_ip32_set_mode(p, ECR_MODE_PPF); 1652 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 1653 1654 /* Wait for peripheral to become ready */ 1655 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT, 1656 DSR_nBUSY | DSR_nFAULT)) { 1657 /* Avoid to flood the logs */ 1658 if (ready_before) 1659 printk(KERN_INFO PPIP32 "%s: not ready in %s\n", 1660 p->name, __func__); 1661 ready_before = 0; 1662 goto stop; 1663 } 1664 ready_before = 1; 1665 1666 written = parport_ip32_fifo_write_block(p, buf, len); 1667 1668 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */ 1669 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth); 1670 1671 /* Check for a potential residue */ 1672 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF); 1673 1674 /* Then, wait for BUSY to get low. */ 1675 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY)) 1676 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n", 1677 p->name, __func__); 1678 1679 stop: 1680 /* Reset FIFO */ 1681 parport_ip32_set_mode(p, ECR_MODE_PS2); 1682 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1683 1684 return written; 1685 } 1686 1687 /* 1688 * FIXME - Insert here parport_ip32_ecp_read_data(). 1689 */ 1690 1691 /** 1692 * parport_ip32_ecp_write_data - write a block of data in ECP mode 1693 * @p: pointer to &struct parport 1694 * @buf: buffer of data to write 1695 * @len: length of buffer @buf 1696 * @flags: ignored 1697 */ 1698 static size_t parport_ip32_ecp_write_data(struct parport *p, 1699 const void *buf, size_t len, 1700 int flags) 1701 { 1702 static unsigned int ready_before = 1; 1703 struct parport_ip32_private * const priv = p->physport->private_data; 1704 struct parport * const physport = p->physport; 1705 size_t written = 0; 1706 1707 /* Special case: a timeout of zero means we cannot call schedule(). 1708 * Also if O_NONBLOCK is set then use the default implementation. */ 1709 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 1710 return parport_ieee1284_ecp_write_data(p, buf, len, flags); 1711 1712 /* Negotiate to forward mode if necessary. */ 1713 if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 1714 /* Event 47: Set nInit high. */ 1715 parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD, 1716 DCR_nINIT | DCR_AUTOFD); 1717 1718 /* Event 49: PError goes high. */ 1719 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) { 1720 printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s", 1721 p->name, __func__); 1722 physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; 1723 return 0; 1724 } 1725 } 1726 1727 /* Reset FIFO, go in forward mode, and disable ackIntEn */ 1728 parport_ip32_set_mode(p, ECR_MODE_PS2); 1729 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1730 parport_ip32_data_forward(p); 1731 parport_ip32_disable_irq(p); 1732 parport_ip32_set_mode(p, ECR_MODE_ECP); 1733 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 1734 1735 /* Wait for peripheral to become ready */ 1736 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT, 1737 DSR_nBUSY | DSR_nFAULT)) { 1738 /* Avoid to flood the logs */ 1739 if (ready_before) 1740 printk(KERN_INFO PPIP32 "%s: not ready in %s\n", 1741 p->name, __func__); 1742 ready_before = 0; 1743 goto stop; 1744 } 1745 ready_before = 1; 1746 1747 written = parport_ip32_fifo_write_block(p, buf, len); 1748 1749 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */ 1750 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth); 1751 1752 /* Check for a potential residue */ 1753 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP); 1754 1755 /* Then, wait for BUSY to get low. */ 1756 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY)) 1757 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n", 1758 p->name, __func__); 1759 1760 stop: 1761 /* Reset FIFO */ 1762 parport_ip32_set_mode(p, ECR_MODE_PS2); 1763 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1764 1765 return written; 1766 } 1767 1768 /* 1769 * FIXME - Insert here parport_ip32_ecp_write_addr(). 1770 */ 1771 1772 /*--- Default parport operations ---------------------------------------*/ 1773 1774 static const struct parport_operations parport_ip32_ops __initconst = { 1775 .write_data = parport_ip32_write_data, 1776 .read_data = parport_ip32_read_data, 1777 1778 .write_control = parport_ip32_write_control, 1779 .read_control = parport_ip32_read_control, 1780 .frob_control = parport_ip32_frob_control, 1781 1782 .read_status = parport_ip32_read_status, 1783 1784 .enable_irq = parport_ip32_enable_irq, 1785 .disable_irq = parport_ip32_disable_irq, 1786 1787 .data_forward = parport_ip32_data_forward, 1788 .data_reverse = parport_ip32_data_reverse, 1789 1790 .init_state = parport_ip32_init_state, 1791 .save_state = parport_ip32_save_state, 1792 .restore_state = parport_ip32_restore_state, 1793 1794 .epp_write_data = parport_ieee1284_epp_write_data, 1795 .epp_read_data = parport_ieee1284_epp_read_data, 1796 .epp_write_addr = parport_ieee1284_epp_write_addr, 1797 .epp_read_addr = parport_ieee1284_epp_read_addr, 1798 1799 .ecp_write_data = parport_ieee1284_ecp_write_data, 1800 .ecp_read_data = parport_ieee1284_ecp_read_data, 1801 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1802 1803 .compat_write_data = parport_ieee1284_write_compat, 1804 .nibble_read_data = parport_ieee1284_read_nibble, 1805 .byte_read_data = parport_ieee1284_read_byte, 1806 1807 .owner = THIS_MODULE, 1808 }; 1809 1810 /*--- Device detection -------------------------------------------------*/ 1811 1812 /** 1813 * parport_ip32_ecp_supported - check for an ECP port 1814 * @p: pointer to the &parport structure 1815 * 1816 * Returns 1 if an ECP port is found, and 0 otherwise. This function actually 1817 * checks if an Extended Control Register seems to be present. On successful 1818 * return, the port is placed in SPP mode. 1819 */ 1820 static __init unsigned int parport_ip32_ecp_supported(struct parport *p) 1821 { 1822 struct parport_ip32_private * const priv = p->physport->private_data; 1823 unsigned int ecr; 1824 1825 ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 1826 writeb(ecr, priv->regs.ecr); 1827 if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY)) 1828 goto fail; 1829 1830 pr_probe(p, "Found working ECR register\n"); 1831 parport_ip32_set_mode(p, ECR_MODE_SPP); 1832 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1833 return 1; 1834 1835 fail: 1836 pr_probe(p, "ECR register not found\n"); 1837 return 0; 1838 } 1839 1840 /** 1841 * parport_ip32_fifo_supported - check for FIFO parameters 1842 * @p: pointer to the &parport structure 1843 * 1844 * Check for FIFO parameters of an Extended Capabilities Port. Returns 1 on 1845 * success, and 0 otherwise. Adjust FIFO parameters in the parport structure. 1846 * On return, the port is placed in SPP mode. 1847 */ 1848 static __init unsigned int parport_ip32_fifo_supported(struct parport *p) 1849 { 1850 struct parport_ip32_private * const priv = p->physport->private_data; 1851 unsigned int configa, configb; 1852 unsigned int pword; 1853 unsigned int i; 1854 1855 /* Configuration mode */ 1856 parport_ip32_set_mode(p, ECR_MODE_CFG); 1857 configa = readb(priv->regs.cnfgA); 1858 configb = readb(priv->regs.cnfgB); 1859 1860 /* Find out PWord size */ 1861 switch (configa & CNFGA_ID_MASK) { 1862 case CNFGA_ID_8: 1863 pword = 1; 1864 break; 1865 case CNFGA_ID_16: 1866 pword = 2; 1867 break; 1868 case CNFGA_ID_32: 1869 pword = 4; 1870 break; 1871 default: 1872 pr_probe(p, "Unknown implementation ID: 0x%0x\n", 1873 (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT); 1874 goto fail; 1875 break; 1876 } 1877 if (pword != 1) { 1878 pr_probe(p, "Unsupported PWord size: %u\n", pword); 1879 goto fail; 1880 } 1881 priv->pword = pword; 1882 pr_probe(p, "PWord is %u bits\n", 8 * priv->pword); 1883 1884 /* Check for compression support */ 1885 writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB); 1886 if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS) 1887 pr_probe(p, "Hardware compression detected (unsupported)\n"); 1888 writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB); 1889 1890 /* Reset FIFO and go in test mode (no interrupt, no DMA) */ 1891 parport_ip32_set_mode(p, ECR_MODE_TST); 1892 1893 /* FIFO must be empty now */ 1894 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) { 1895 pr_probe(p, "FIFO not reset\n"); 1896 goto fail; 1897 } 1898 1899 /* Find out FIFO depth. */ 1900 priv->fifo_depth = 0; 1901 for (i = 0; i < 1024; i++) { 1902 if (readb(priv->regs.ecr) & ECR_F_FULL) { 1903 /* FIFO full */ 1904 priv->fifo_depth = i; 1905 break; 1906 } 1907 writeb((u8)i, priv->regs.fifo); 1908 } 1909 if (i >= 1024) { 1910 pr_probe(p, "Can't fill FIFO\n"); 1911 goto fail; 1912 } 1913 if (!priv->fifo_depth) { 1914 pr_probe(p, "Can't get FIFO depth\n"); 1915 goto fail; 1916 } 1917 pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth); 1918 1919 /* Enable interrupts */ 1920 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1921 1922 /* Find out writeIntrThreshold: number of PWords we know we can write 1923 * if we get an interrupt. */ 1924 priv->writeIntrThreshold = 0; 1925 for (i = 0; i < priv->fifo_depth; i++) { 1926 if (readb(priv->regs.fifo) != (u8)i) { 1927 pr_probe(p, "Invalid data in FIFO\n"); 1928 goto fail; 1929 } 1930 if (!priv->writeIntrThreshold 1931 && readb(priv->regs.ecr) & ECR_SERVINTR) 1932 /* writeIntrThreshold reached */ 1933 priv->writeIntrThreshold = i + 1; 1934 if (i + 1 < priv->fifo_depth 1935 && readb(priv->regs.ecr) & ECR_F_EMPTY) { 1936 /* FIFO empty before the last byte? */ 1937 pr_probe(p, "Data lost in FIFO\n"); 1938 goto fail; 1939 } 1940 } 1941 if (!priv->writeIntrThreshold) { 1942 pr_probe(p, "Can't get writeIntrThreshold\n"); 1943 goto fail; 1944 } 1945 pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold); 1946 1947 /* FIFO must be empty now */ 1948 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) { 1949 pr_probe(p, "Can't empty FIFO\n"); 1950 goto fail; 1951 } 1952 1953 /* Reset FIFO */ 1954 parport_ip32_set_mode(p, ECR_MODE_PS2); 1955 /* Set reverse direction (must be in PS2 mode) */ 1956 parport_ip32_data_reverse(p); 1957 /* Test FIFO, no interrupt, no DMA */ 1958 parport_ip32_set_mode(p, ECR_MODE_TST); 1959 /* Enable interrupts */ 1960 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1961 1962 /* Find out readIntrThreshold: number of PWords we can read if we get 1963 * an interrupt. */ 1964 priv->readIntrThreshold = 0; 1965 for (i = 0; i < priv->fifo_depth; i++) { 1966 writeb(0xaa, priv->regs.fifo); 1967 if (readb(priv->regs.ecr) & ECR_SERVINTR) { 1968 /* readIntrThreshold reached */ 1969 priv->readIntrThreshold = i + 1; 1970 break; 1971 } 1972 } 1973 if (!priv->readIntrThreshold) { 1974 pr_probe(p, "Can't get readIntrThreshold\n"); 1975 goto fail; 1976 } 1977 pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold); 1978 1979 /* Reset ECR */ 1980 parport_ip32_set_mode(p, ECR_MODE_PS2); 1981 parport_ip32_data_forward(p); 1982 parport_ip32_set_mode(p, ECR_MODE_SPP); 1983 return 1; 1984 1985 fail: 1986 priv->fifo_depth = 0; 1987 parport_ip32_set_mode(p, ECR_MODE_SPP); 1988 return 0; 1989 } 1990 1991 /*--- Initialization code ----------------------------------------------*/ 1992 1993 /** 1994 * parport_ip32_make_isa_registers - compute (ISA) register addresses 1995 * @regs: pointer to &struct parport_ip32_regs to fill 1996 * @base: base address of standard and EPP registers 1997 * @base_hi: base address of ECP registers 1998 * @regshift: how much to shift register offset by 1999 * 2000 * Compute register addresses, according to the ISA standard. The addresses 2001 * of the standard and EPP registers are computed from address @base. The 2002 * addresses of the ECP registers are computed from address @base_hi. 2003 */ 2004 static void __init 2005 parport_ip32_make_isa_registers(struct parport_ip32_regs *regs, 2006 void __iomem *base, void __iomem *base_hi, 2007 unsigned int regshift) 2008 { 2009 #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift)) 2010 #define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift)) 2011 *regs = (struct parport_ip32_regs){ 2012 .data = r_base(0), 2013 .dsr = r_base(1), 2014 .dcr = r_base(2), 2015 .eppAddr = r_base(3), 2016 .eppData0 = r_base(4), 2017 .eppData1 = r_base(5), 2018 .eppData2 = r_base(6), 2019 .eppData3 = r_base(7), 2020 .ecpAFifo = r_base(0), 2021 .fifo = r_base_hi(0), 2022 .cnfgA = r_base_hi(0), 2023 .cnfgB = r_base_hi(1), 2024 .ecr = r_base_hi(2) 2025 }; 2026 #undef r_base_hi 2027 #undef r_base 2028 } 2029 2030 /** 2031 * parport_ip32_probe_port - probe and register IP32 built-in parallel port 2032 * 2033 * Returns the new allocated &parport structure. On error, an error code is 2034 * encoded in return value with the ERR_PTR function. 2035 */ 2036 static __init struct parport *parport_ip32_probe_port(void) 2037 { 2038 struct parport_ip32_regs regs; 2039 struct parport_ip32_private *priv = NULL; 2040 struct parport_operations *ops = NULL; 2041 struct parport *p = NULL; 2042 int err; 2043 2044 parport_ip32_make_isa_registers(®s, &mace->isa.parallel, 2045 &mace->isa.ecp1284, 8 /* regshift */); 2046 2047 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); 2048 priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL); 2049 p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops); 2050 if (ops == NULL || priv == NULL || p == NULL) { 2051 err = -ENOMEM; 2052 goto fail; 2053 } 2054 p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel); 2055 p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284); 2056 p->private_data = priv; 2057 2058 *ops = parport_ip32_ops; 2059 *priv = (struct parport_ip32_private){ 2060 .regs = regs, 2061 .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT | 2062 DCR_AUTOFD | DCR_STROBE, 2063 .irq_mode = PARPORT_IP32_IRQ_FWD, 2064 }; 2065 init_completion(&priv->irq_complete); 2066 2067 /* Probe port. */ 2068 if (!parport_ip32_ecp_supported(p)) { 2069 err = -ENODEV; 2070 goto fail; 2071 } 2072 parport_ip32_dump_state(p, "begin init", 0); 2073 2074 /* We found what looks like a working ECR register. Simply assume 2075 * that all modes are correctly supported. Enable basic modes. */ 2076 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2077 p->modes |= PARPORT_MODE_TRISTATE; 2078 2079 if (!parport_ip32_fifo_supported(p)) { 2080 printk(KERN_WARNING PPIP32 2081 "%s: error: FIFO disabled\n", p->name); 2082 /* Disable hardware modes depending on a working FIFO. */ 2083 features &= ~PARPORT_IP32_ENABLE_SPP; 2084 features &= ~PARPORT_IP32_ENABLE_ECP; 2085 /* DMA is not needed if FIFO is not supported. */ 2086 features &= ~PARPORT_IP32_ENABLE_DMA; 2087 } 2088 2089 /* Request IRQ */ 2090 if (features & PARPORT_IP32_ENABLE_IRQ) { 2091 int irq = MACEISA_PARALLEL_IRQ; 2092 if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) { 2093 printk(KERN_WARNING PPIP32 2094 "%s: error: IRQ disabled\n", p->name); 2095 /* DMA cannot work without interrupts. */ 2096 features &= ~PARPORT_IP32_ENABLE_DMA; 2097 } else { 2098 pr_probe(p, "Interrupt support enabled\n"); 2099 p->irq = irq; 2100 priv->dcr_writable |= DCR_IRQ; 2101 } 2102 } 2103 2104 /* Allocate DMA resources */ 2105 if (features & PARPORT_IP32_ENABLE_DMA) { 2106 if (parport_ip32_dma_register()) 2107 printk(KERN_WARNING PPIP32 2108 "%s: error: DMA disabled\n", p->name); 2109 else { 2110 pr_probe(p, "DMA support enabled\n"); 2111 p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */ 2112 p->modes |= PARPORT_MODE_DMA; 2113 } 2114 } 2115 2116 if (features & PARPORT_IP32_ENABLE_SPP) { 2117 /* Enable compatibility FIFO mode */ 2118 p->ops->compat_write_data = parport_ip32_compat_write_data; 2119 p->modes |= PARPORT_MODE_COMPAT; 2120 pr_probe(p, "Hardware support for SPP mode enabled\n"); 2121 } 2122 if (features & PARPORT_IP32_ENABLE_EPP) { 2123 /* Set up access functions to use EPP hardware. */ 2124 p->ops->epp_read_data = parport_ip32_epp_read_data; 2125 p->ops->epp_write_data = parport_ip32_epp_write_data; 2126 p->ops->epp_read_addr = parport_ip32_epp_read_addr; 2127 p->ops->epp_write_addr = parport_ip32_epp_write_addr; 2128 p->modes |= PARPORT_MODE_EPP; 2129 pr_probe(p, "Hardware support for EPP mode enabled\n"); 2130 } 2131 if (features & PARPORT_IP32_ENABLE_ECP) { 2132 /* Enable ECP FIFO mode */ 2133 p->ops->ecp_write_data = parport_ip32_ecp_write_data; 2134 /* FIXME - not implemented */ 2135 /* p->ops->ecp_read_data = parport_ip32_ecp_read_data; */ 2136 /* p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */ 2137 p->modes |= PARPORT_MODE_ECP; 2138 pr_probe(p, "Hardware support for ECP mode enabled\n"); 2139 } 2140 2141 /* Initialize the port with sensible values */ 2142 parport_ip32_set_mode(p, ECR_MODE_PS2); 2143 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 2144 parport_ip32_data_forward(p); 2145 parport_ip32_disable_irq(p); 2146 parport_ip32_write_data(p, 0x00); 2147 parport_ip32_dump_state(p, "end init", 0); 2148 2149 /* Print out what we found */ 2150 printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)", 2151 p->name, p->base, p->base_hi); 2152 if (p->irq != PARPORT_IRQ_NONE) 2153 printk(", irq %d", p->irq); 2154 printk(" ["); 2155 #define printmode(x) if (p->modes & PARPORT_MODE_##x) \ 2156 printk("%s%s", f++ ? "," : "", #x) 2157 { 2158 unsigned int f = 0; 2159 printmode(PCSPP); 2160 printmode(TRISTATE); 2161 printmode(COMPAT); 2162 printmode(EPP); 2163 printmode(ECP); 2164 printmode(DMA); 2165 } 2166 #undef printmode 2167 printk("]\n"); 2168 2169 parport_announce_port(p); 2170 return p; 2171 2172 fail: 2173 if (p) 2174 parport_put_port(p); 2175 kfree(priv); 2176 kfree(ops); 2177 return ERR_PTR(err); 2178 } 2179 2180 /** 2181 * parport_ip32_unregister_port - unregister a parallel port 2182 * @p: pointer to the &struct parport 2183 * 2184 * Unregisters a parallel port and free previously allocated resources 2185 * (memory, IRQ, ...). 2186 */ 2187 static __exit void parport_ip32_unregister_port(struct parport *p) 2188 { 2189 struct parport_ip32_private * const priv = p->physport->private_data; 2190 struct parport_operations *ops = p->ops; 2191 2192 parport_remove_port(p); 2193 if (p->modes & PARPORT_MODE_DMA) 2194 parport_ip32_dma_unregister(); 2195 if (p->irq != PARPORT_IRQ_NONE) 2196 free_irq(p->irq, p); 2197 parport_put_port(p); 2198 kfree(priv); 2199 kfree(ops); 2200 } 2201 2202 /** 2203 * parport_ip32_init - module initialization function 2204 */ 2205 static int __init parport_ip32_init(void) 2206 { 2207 pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n"); 2208 this_port = parport_ip32_probe_port(); 2209 return PTR_ERR_OR_ZERO(this_port); 2210 } 2211 2212 /** 2213 * parport_ip32_exit - module termination function 2214 */ 2215 static void __exit parport_ip32_exit(void) 2216 { 2217 parport_ip32_unregister_port(this_port); 2218 } 2219 2220 /*--- Module stuff -----------------------------------------------------*/ 2221 2222 MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>"); 2223 MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver"); 2224 MODULE_LICENSE("GPL"); 2225 MODULE_VERSION("0.6"); /* update in parport_ip32_init() too */ 2226 2227 module_init(parport_ip32_init); 2228 module_exit(parport_ip32_exit); 2229 2230 module_param(verbose_probing, bool, S_IRUGO); 2231 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization"); 2232 2233 module_param(features, uint, S_IRUGO); 2234 MODULE_PARM_DESC(features, 2235 "Bit mask of features to enable" 2236 ", bit 0: IRQ support" 2237 ", bit 1: DMA support" 2238 ", bit 2: hardware SPP mode" 2239 ", bit 3: hardware EPP mode" 2240 ", bit 4: hardware ECP mode"); 2241 2242 /*--- Inform (X)Emacs about preferred coding style ---------------------*/ 2243 /* 2244 * Local Variables: 2245 * mode: c 2246 * c-file-style: "linux" 2247 * indent-tabs-mode: t 2248 * tab-width: 8 2249 * fill-column: 78 2250 * ispell-local-dictionary: "american" 2251 * End: 2252 */ 2253