1 /* Low-level parallel port routines for built-in port on SGI IP32 2 * 3 * Author: Arnaud Giersch <arnaud.giersch@free.fr> 4 * 5 * Based on parport_pc.c by 6 * Phil Blundell, Tim Waugh, Jose Renau, David Campbell, 7 * Andrea Arcangeli, et al. 8 * 9 * Thanks to Ilya A. Volynets-Evenbakh for his help. 10 * 11 * Copyright (C) 2005, 2006 Arnaud Giersch. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the Free 15 * Software Foundation; either version 2 of the License, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, but WITHOUT 19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 21 * more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 59 25 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 26 */ 27 28 /* Current status: 29 * 30 * Basic SPP and PS2 modes are supported. 31 * Support for parallel port IRQ is present. 32 * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are 33 * supported. 34 * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with 35 * or without interrupt support. 36 * 37 * Hardware ECP mode is not fully implemented (ecp_read_data and 38 * ecp_write_addr are actually missing). 39 * 40 * To do: 41 * 42 * Fully implement ECP mode. 43 * EPP and ECP mode need to be tested. I currently do not own any 44 * peripheral supporting these extended mode, and cannot test them. 45 * If DMA mode works well, decide if support for PIO FIFO modes should be 46 * dropped. 47 * Use the io{read,write} family functions when they become available in 48 * the linux-mips.org tree. Note: the MIPS specific functions readsb() 49 * and writesb() are to be translated by ioread8_rep() and iowrite8_rep() 50 * respectively. 51 */ 52 53 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an 54 * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1]. 55 * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte 56 * FIFO buffer and supports DMA transfers. 57 * 58 * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html 59 * 60 * Theoretically, we could simply use the parport_pc module. It is however 61 * not so simple. The parport_pc code assumes that the parallel port 62 * registers are port-mapped. On the O2, they are memory-mapped. 63 * Furthermore, each register is replicated on 256 consecutive addresses (as 64 * it is for the built-in serial ports on the same chip). 65 */ 66 67 /*--- Some configuration defines ---------------------------------------*/ 68 69 /* DEBUG_PARPORT_IP32 70 * 0 disable debug 71 * 1 standard level: pr_debug1 is enabled 72 * 2 parport_ip32_dump_state is enabled 73 * >=3 verbose level: pr_debug is enabled 74 */ 75 #if !defined(DEBUG_PARPORT_IP32) 76 # define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */ 77 #endif 78 79 /*----------------------------------------------------------------------*/ 80 81 /* Setup DEBUG macros. This is done before any includes, just in case we 82 * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3. 83 */ 84 #if DEBUG_PARPORT_IP32 == 1 85 # warning DEBUG_PARPORT_IP32 == 1 86 #elif DEBUG_PARPORT_IP32 == 2 87 # warning DEBUG_PARPORT_IP32 == 2 88 #elif DEBUG_PARPORT_IP32 >= 3 89 # warning DEBUG_PARPORT_IP32 >= 3 90 # if !defined(DEBUG) 91 # define DEBUG /* enable pr_debug() in kernel.h */ 92 # endif 93 #endif 94 95 #include <linux/completion.h> 96 #include <linux/delay.h> 97 #include <linux/dma-mapping.h> 98 #include <linux/err.h> 99 #include <linux/init.h> 100 #include <linux/interrupt.h> 101 #include <linux/jiffies.h> 102 #include <linux/kernel.h> 103 #include <linux/module.h> 104 #include <linux/parport.h> 105 #include <linux/sched.h> 106 #include <linux/spinlock.h> 107 #include <linux/stddef.h> 108 #include <linux/types.h> 109 #include <asm/io.h> 110 #include <asm/ip32/ip32_ints.h> 111 #include <asm/ip32/mace.h> 112 113 /*--- Global variables -------------------------------------------------*/ 114 115 /* Verbose probing on by default for debugging. */ 116 #if DEBUG_PARPORT_IP32 >= 1 117 # define DEFAULT_VERBOSE_PROBING 1 118 #else 119 # define DEFAULT_VERBOSE_PROBING 0 120 #endif 121 122 /* Default prefix for printk */ 123 #define PPIP32 "parport_ip32: " 124 125 /* 126 * These are the module parameters: 127 * @features: bit mask of features to enable/disable 128 * (all enabled by default) 129 * @verbose_probing: log chit-chat during initialization 130 */ 131 #define PARPORT_IP32_ENABLE_IRQ (1U << 0) 132 #define PARPORT_IP32_ENABLE_DMA (1U << 1) 133 #define PARPORT_IP32_ENABLE_SPP (1U << 2) 134 #define PARPORT_IP32_ENABLE_EPP (1U << 3) 135 #define PARPORT_IP32_ENABLE_ECP (1U << 4) 136 static unsigned int features = ~0U; 137 static int verbose_probing = DEFAULT_VERBOSE_PROBING; 138 139 /* We do not support more than one port. */ 140 static struct parport *this_port = NULL; 141 142 /* Timing constants for FIFO modes. */ 143 #define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */ 144 #define FIFO_POLLING_INTERVAL 50 /* microseconds */ 145 146 /*--- I/O register definitions -----------------------------------------*/ 147 148 /** 149 * struct parport_ip32_regs - virtual addresses of parallel port registers 150 * @data: Data Register 151 * @dsr: Device Status Register 152 * @dcr: Device Control Register 153 * @eppAddr: EPP Address Register 154 * @eppData0: EPP Data Register 0 155 * @eppData1: EPP Data Register 1 156 * @eppData2: EPP Data Register 2 157 * @eppData3: EPP Data Register 3 158 * @ecpAFifo: ECP Address FIFO 159 * @fifo: General FIFO register. The same address is used for: 160 * - cFifo, the Parallel Port DATA FIFO 161 * - ecpDFifo, the ECP Data FIFO 162 * - tFifo, the ECP Test FIFO 163 * @cnfgA: Configuration Register A 164 * @cnfgB: Configuration Register B 165 * @ecr: Extended Control Register 166 */ 167 struct parport_ip32_regs { 168 void __iomem *data; 169 void __iomem *dsr; 170 void __iomem *dcr; 171 void __iomem *eppAddr; 172 void __iomem *eppData0; 173 void __iomem *eppData1; 174 void __iomem *eppData2; 175 void __iomem *eppData3; 176 void __iomem *ecpAFifo; 177 void __iomem *fifo; 178 void __iomem *cnfgA; 179 void __iomem *cnfgB; 180 void __iomem *ecr; 181 }; 182 183 /* Device Status Register */ 184 #define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */ 185 #define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */ 186 #define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */ 187 #define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */ 188 #define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */ 189 #define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */ 190 /* #define DSR_reserved (1U << 1) */ 191 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */ 192 193 /* Device Control Register */ 194 /* #define DCR_reserved (1U << 7) | (1U << 6) */ 195 #define DCR_DIR (1U << 5) /* direction */ 196 #define DCR_IRQ (1U << 4) /* interrupt on nAck */ 197 #define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */ 198 #define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */ 199 #define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */ 200 #define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */ 201 202 /* ECP Configuration Register A */ 203 #define CNFGA_IRQ (1U << 7) 204 #define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4)) 205 #define CNFGA_ID_SHIFT 4 206 #define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT) 207 #define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT) 208 #define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT) 209 /* #define CNFGA_reserved (1U << 3) */ 210 #define CNFGA_nBYTEINTRANS (1U << 2) 211 #define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0)) 212 213 /* ECP Configuration Register B */ 214 #define CNFGB_COMPRESS (1U << 7) 215 #define CNFGB_INTRVAL (1U << 6) 216 #define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3)) 217 #define CNFGB_IRQ_SHIFT 3 218 #define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0)) 219 #define CNFGB_DMA_SHIFT 0 220 221 /* Extended Control Register */ 222 #define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5)) 223 #define ECR_MODE_SHIFT 5 224 #define ECR_MODE_SPP (00U << ECR_MODE_SHIFT) 225 #define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT) 226 #define ECR_MODE_PPF (02U << ECR_MODE_SHIFT) 227 #define ECR_MODE_ECP (03U << ECR_MODE_SHIFT) 228 #define ECR_MODE_EPP (04U << ECR_MODE_SHIFT) 229 /* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */ 230 #define ECR_MODE_TST (06U << ECR_MODE_SHIFT) 231 #define ECR_MODE_CFG (07U << ECR_MODE_SHIFT) 232 #define ECR_nERRINTR (1U << 4) 233 #define ECR_DMAEN (1U << 3) 234 #define ECR_SERVINTR (1U << 2) 235 #define ECR_F_FULL (1U << 1) 236 #define ECR_F_EMPTY (1U << 0) 237 238 /*--- Private data -----------------------------------------------------*/ 239 240 /** 241 * enum parport_ip32_irq_mode - operation mode of interrupt handler 242 * @PARPORT_IP32_IRQ_FWD: forward interrupt to the upper parport layer 243 * @PARPORT_IP32_IRQ_HERE: interrupt is handled locally 244 */ 245 enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE }; 246 247 /** 248 * struct parport_ip32_private - private stuff for &struct parport 249 * @regs: register addresses 250 * @dcr_cache: cached contents of DCR 251 * @dcr_writable: bit mask of writable DCR bits 252 * @pword: number of bytes per PWord 253 * @fifo_depth: number of PWords that FIFO will hold 254 * @readIntrThreshold: minimum number of PWords we can read 255 * if we get an interrupt 256 * @writeIntrThreshold: minimum number of PWords we can write 257 * if we get an interrupt 258 * @irq_mode: operation mode of interrupt handler for this port 259 * @irq_complete: mutex used to wait for an interrupt to occur 260 */ 261 struct parport_ip32_private { 262 struct parport_ip32_regs regs; 263 unsigned int dcr_cache; 264 unsigned int dcr_writable; 265 unsigned int pword; 266 unsigned int fifo_depth; 267 unsigned int readIntrThreshold; 268 unsigned int writeIntrThreshold; 269 enum parport_ip32_irq_mode irq_mode; 270 struct completion irq_complete; 271 }; 272 273 /*--- Debug code -------------------------------------------------------*/ 274 275 /* 276 * pr_debug1 - print debug messages 277 * 278 * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1 279 */ 280 #if DEBUG_PARPORT_IP32 >= 1 281 # define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__) 282 #else /* DEBUG_PARPORT_IP32 < 1 */ 283 # define pr_debug1(...) do { } while (0) 284 #endif 285 286 /* 287 * pr_trace, pr_trace1 - trace function calls 288 * @p: pointer to &struct parport 289 * @fmt: printk format string 290 * @...: parameters for format string 291 * 292 * Macros used to trace function calls. The given string is formatted after 293 * function name. pr_trace() uses pr_debug(), and pr_trace1() uses 294 * pr_debug1(). __pr_trace() is the low-level macro and is not to be used 295 * directly. 296 */ 297 #define __pr_trace(pr, p, fmt, ...) \ 298 pr("%s: %s" fmt "\n", \ 299 ({ const struct parport *__p = (p); \ 300 __p ? __p->name : "parport_ip32"; }), \ 301 __func__ , ##__VA_ARGS__) 302 #define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__) 303 #define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__) 304 305 /* 306 * __pr_probe, pr_probe - print message if @verbose_probing is true 307 * @p: pointer to &struct parport 308 * @fmt: printk format string 309 * @...: parameters for format string 310 * 311 * For new lines, use pr_probe(). Use __pr_probe() for continued lines. 312 */ 313 #define __pr_probe(...) \ 314 do { if (verbose_probing) printk(__VA_ARGS__); } while (0) 315 #define pr_probe(p, fmt, ...) \ 316 __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__) 317 318 /* 319 * parport_ip32_dump_state - print register status of parport 320 * @p: pointer to &struct parport 321 * @str: string to add in message 322 * @show_ecp_config: shall we dump ECP configuration registers too? 323 * 324 * This function is only here for debugging purpose, and should be used with 325 * care. Reading the parallel port registers may have undesired side effects. 326 * Especially if @show_ecp_config is true, the parallel port is resetted. 327 * This function is only defined if %DEBUG_PARPORT_IP32 >= 2. 328 */ 329 #if DEBUG_PARPORT_IP32 >= 2 330 static void parport_ip32_dump_state(struct parport *p, char *str, 331 unsigned int show_ecp_config) 332 { 333 struct parport_ip32_private * const priv = p->physport->private_data; 334 unsigned int i; 335 336 printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str); 337 { 338 static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF", 339 "ECP", "EPP", "???", 340 "TST", "CFG"}; 341 unsigned int ecr = readb(priv->regs.ecr); 342 printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr); 343 printk(" %s", 344 ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); 345 if (ecr & ECR_nERRINTR) 346 printk(",nErrIntrEn"); 347 if (ecr & ECR_DMAEN) 348 printk(",dmaEn"); 349 if (ecr & ECR_SERVINTR) 350 printk(",serviceIntr"); 351 if (ecr & ECR_F_FULL) 352 printk(",f_full"); 353 if (ecr & ECR_F_EMPTY) 354 printk(",f_empty"); 355 printk("\n"); 356 } 357 if (show_ecp_config) { 358 unsigned int oecr, cnfgA, cnfgB; 359 oecr = readb(priv->regs.ecr); 360 writeb(ECR_MODE_PS2, priv->regs.ecr); 361 writeb(ECR_MODE_CFG, priv->regs.ecr); 362 cnfgA = readb(priv->regs.cnfgA); 363 cnfgB = readb(priv->regs.cnfgB); 364 writeb(ECR_MODE_PS2, priv->regs.ecr); 365 writeb(oecr, priv->regs.ecr); 366 printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA); 367 printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); 368 switch (cnfgA & CNFGA_ID_MASK) { 369 case CNFGA_ID_8: 370 printk(",8 bits"); 371 break; 372 case CNFGA_ID_16: 373 printk(",16 bits"); 374 break; 375 case CNFGA_ID_32: 376 printk(",32 bits"); 377 break; 378 default: 379 printk(",unknown ID"); 380 break; 381 } 382 if (!(cnfgA & CNFGA_nBYTEINTRANS)) 383 printk(",ByteInTrans"); 384 if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8) 385 printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT, 386 ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); 387 printk("\n"); 388 printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB); 389 printk(" irq=%u,dma=%u", 390 (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, 391 (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); 392 printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); 393 if (cnfgB & CNFGB_COMPRESS) 394 printk(",compress"); 395 printk("\n"); 396 } 397 for (i = 0; i < 2; i++) { 398 unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr); 399 printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x", 400 i ? "soft" : "hard", dcr); 401 printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); 402 if (dcr & DCR_IRQ) 403 printk(",ackIntEn"); 404 if (!(dcr & DCR_SELECT)) 405 printk(",nSelectIn"); 406 if (dcr & DCR_nINIT) 407 printk(",nInit"); 408 if (!(dcr & DCR_AUTOFD)) 409 printk(",nAutoFD"); 410 if (!(dcr & DCR_STROBE)) 411 printk(",nStrobe"); 412 printk("\n"); 413 } 414 #define sep (f++ ? ',' : ' ') 415 { 416 unsigned int f = 0; 417 unsigned int dsr = readb(priv->regs.dsr); 418 printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr); 419 if (!(dsr & DSR_nBUSY)) 420 printk("%cBusy", sep); 421 if (dsr & DSR_nACK) 422 printk("%cnAck", sep); 423 if (dsr & DSR_PERROR) 424 printk("%cPError", sep); 425 if (dsr & DSR_SELECT) 426 printk("%cSelect", sep); 427 if (dsr & DSR_nFAULT) 428 printk("%cnFault", sep); 429 if (!(dsr & DSR_nPRINT)) 430 printk("%c(Print)", sep); 431 if (dsr & DSR_TIMEOUT) 432 printk("%cTimeout", sep); 433 printk("\n"); 434 } 435 #undef sep 436 } 437 #else /* DEBUG_PARPORT_IP32 < 2 */ 438 #define parport_ip32_dump_state(...) do { } while (0) 439 #endif 440 441 /* 442 * CHECK_EXTRA_BITS - track and log extra bits 443 * @p: pointer to &struct parport 444 * @b: byte to inspect 445 * @m: bit mask of authorized bits 446 * 447 * This is used to track and log extra bits that should not be there in 448 * parport_ip32_write_control() and parport_ip32_frob_control(). It is only 449 * defined if %DEBUG_PARPORT_IP32 >= 1. 450 */ 451 #if DEBUG_PARPORT_IP32 >= 1 452 #define CHECK_EXTRA_BITS(p, b, m) \ 453 do { \ 454 unsigned int __b = (b), __m = (m); \ 455 if (__b & ~__m) \ 456 pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \ 457 "0x%02x/0x%02x\n", \ 458 (p)->name, __func__, #b, __b, __m); \ 459 } while (0) 460 #else /* DEBUG_PARPORT_IP32 < 1 */ 461 #define CHECK_EXTRA_BITS(...) do { } while (0) 462 #endif 463 464 /*--- IP32 parallel port DMA operations --------------------------------*/ 465 466 /** 467 * struct parport_ip32_dma_data - private data needed for DMA operation 468 * @dir: DMA direction (from or to device) 469 * @buf: buffer physical address 470 * @len: buffer length 471 * @next: address of next bytes to DMA transfer 472 * @left: number of bytes remaining 473 * @ctx: next context to write (0: context_a; 1: context_b) 474 * @irq_on: are the DMA IRQs currently enabled? 475 * @lock: spinlock to protect access to the structure 476 */ 477 struct parport_ip32_dma_data { 478 enum dma_data_direction dir; 479 dma_addr_t buf; 480 dma_addr_t next; 481 size_t len; 482 size_t left; 483 unsigned int ctx; 484 unsigned int irq_on; 485 spinlock_t lock; 486 }; 487 static struct parport_ip32_dma_data parport_ip32_dma; 488 489 /** 490 * parport_ip32_dma_setup_context - setup next DMA context 491 * @limit: maximum data size for the context 492 * 493 * The alignment constraints must be verified in caller function, and the 494 * parameter @limit must be set accordingly. 495 */ 496 static void parport_ip32_dma_setup_context(unsigned int limit) 497 { 498 unsigned long flags; 499 500 spin_lock_irqsave(&parport_ip32_dma.lock, flags); 501 if (parport_ip32_dma.left > 0) { 502 /* Note: ctxreg is "volatile" here only because 503 * mace->perif.ctrl.parport.context_a and context_b are 504 * "volatile". */ 505 volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ? 506 &mace->perif.ctrl.parport.context_a : 507 &mace->perif.ctrl.parport.context_b; 508 u64 count; 509 u64 ctxval; 510 if (parport_ip32_dma.left <= limit) { 511 count = parport_ip32_dma.left; 512 ctxval = MACEPAR_CONTEXT_LASTFLAG; 513 } else { 514 count = limit; 515 ctxval = 0; 516 } 517 518 pr_trace(NULL, 519 "(%u): 0x%04x:0x%04x, %u -> %u%s", 520 limit, 521 (unsigned int)parport_ip32_dma.buf, 522 (unsigned int)parport_ip32_dma.next, 523 (unsigned int)count, 524 parport_ip32_dma.ctx, ctxval ? "*" : ""); 525 526 ctxval |= parport_ip32_dma.next & 527 MACEPAR_CONTEXT_BASEADDR_MASK; 528 ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) & 529 MACEPAR_CONTEXT_DATALEN_MASK; 530 writeq(ctxval, ctxreg); 531 parport_ip32_dma.next += count; 532 parport_ip32_dma.left -= count; 533 parport_ip32_dma.ctx ^= 1U; 534 } 535 /* If there is nothing more to send, disable IRQs to avoid to 536 * face an IRQ storm which can lock the machine. Disable them 537 * only once. */ 538 if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) { 539 pr_debug(PPIP32 "IRQ off (ctx)\n"); 540 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ); 541 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ); 542 parport_ip32_dma.irq_on = 0; 543 } 544 spin_unlock_irqrestore(&parport_ip32_dma.lock, flags); 545 } 546 547 /** 548 * parport_ip32_dma_interrupt - DMA interrupt handler 549 * @irq: interrupt number 550 * @dev_id: unused 551 */ 552 static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id) 553 { 554 if (parport_ip32_dma.left) 555 pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx); 556 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND); 557 return IRQ_HANDLED; 558 } 559 560 #if DEBUG_PARPORT_IP32 561 static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id) 562 { 563 pr_trace1(NULL, "(%d)", irq); 564 return IRQ_HANDLED; 565 } 566 #endif 567 568 /** 569 * parport_ip32_dma_start - begins a DMA transfer 570 * @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE 571 * @addr: pointer to data buffer 572 * @count: buffer size 573 * 574 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 575 * correctly balanced. 576 */ 577 static int parport_ip32_dma_start(enum dma_data_direction dir, 578 void *addr, size_t count) 579 { 580 unsigned int limit; 581 u64 ctrl; 582 583 pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count); 584 585 /* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must 586 * be 64 bytes aligned. */ 587 BUG_ON(dir != DMA_TO_DEVICE); 588 589 /* Reset DMA controller */ 590 ctrl = MACEPAR_CTLSTAT_RESET; 591 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 592 593 /* DMA IRQs should normally be enabled */ 594 if (!parport_ip32_dma.irq_on) { 595 WARN_ON(1); 596 enable_irq(MACEISA_PAR_CTXA_IRQ); 597 enable_irq(MACEISA_PAR_CTXB_IRQ); 598 parport_ip32_dma.irq_on = 1; 599 } 600 601 /* Prepare DMA pointers */ 602 parport_ip32_dma.dir = dir; 603 parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir); 604 parport_ip32_dma.len = count; 605 parport_ip32_dma.next = parport_ip32_dma.buf; 606 parport_ip32_dma.left = parport_ip32_dma.len; 607 parport_ip32_dma.ctx = 0; 608 609 /* Setup DMA direction and first two contexts */ 610 ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION; 611 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 612 /* Single transfer should not cross a 4K page boundary */ 613 limit = MACEPAR_CONTEXT_DATA_BOUND - 614 (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1)); 615 parport_ip32_dma_setup_context(limit); 616 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND); 617 618 /* Real start of DMA transfer */ 619 ctrl |= MACEPAR_CTLSTAT_ENABLE; 620 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 621 622 return 0; 623 } 624 625 /** 626 * parport_ip32_dma_stop - ends a running DMA transfer 627 * 628 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 629 * correctly balanced. 630 */ 631 static void parport_ip32_dma_stop(void) 632 { 633 u64 ctx_a; 634 u64 ctx_b; 635 u64 ctrl; 636 u64 diag; 637 size_t res[2]; /* {[0] = res_a, [1] = res_b} */ 638 639 pr_trace(NULL, "()"); 640 641 /* Disable IRQs */ 642 spin_lock_irq(&parport_ip32_dma.lock); 643 if (parport_ip32_dma.irq_on) { 644 pr_debug(PPIP32 "IRQ off (stop)\n"); 645 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ); 646 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ); 647 parport_ip32_dma.irq_on = 0; 648 } 649 spin_unlock_irq(&parport_ip32_dma.lock); 650 /* Force IRQ synchronization, even if the IRQs were disabled 651 * elsewhere. */ 652 synchronize_irq(MACEISA_PAR_CTXA_IRQ); 653 synchronize_irq(MACEISA_PAR_CTXB_IRQ); 654 655 /* Stop DMA transfer */ 656 ctrl = readq(&mace->perif.ctrl.parport.cntlstat); 657 ctrl &= ~MACEPAR_CTLSTAT_ENABLE; 658 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 659 660 /* Adjust residue (parport_ip32_dma.left) */ 661 ctx_a = readq(&mace->perif.ctrl.parport.context_a); 662 ctx_b = readq(&mace->perif.ctrl.parport.context_b); 663 ctrl = readq(&mace->perif.ctrl.parport.cntlstat); 664 diag = readq(&mace->perif.ctrl.parport.diagnostic); 665 res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ? 666 1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >> 667 MACEPAR_CONTEXT_DATALEN_SHIFT) : 668 0; 669 res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ? 670 1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >> 671 MACEPAR_CONTEXT_DATALEN_SHIFT) : 672 0; 673 if (diag & MACEPAR_DIAG_DMACTIVE) 674 res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] = 675 1 + ((diag & MACEPAR_DIAG_CTRMASK) >> 676 MACEPAR_DIAG_CTRSHIFT); 677 parport_ip32_dma.left += res[0] + res[1]; 678 679 /* Reset DMA controller, and re-enable IRQs */ 680 ctrl = MACEPAR_CTLSTAT_RESET; 681 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 682 pr_debug(PPIP32 "IRQ on (stop)\n"); 683 enable_irq(MACEISA_PAR_CTXA_IRQ); 684 enable_irq(MACEISA_PAR_CTXB_IRQ); 685 parport_ip32_dma.irq_on = 1; 686 687 dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len, 688 parport_ip32_dma.dir); 689 } 690 691 /** 692 * parport_ip32_dma_get_residue - get residue from last DMA transfer 693 * 694 * Returns the number of bytes remaining from last DMA transfer. 695 */ 696 static inline size_t parport_ip32_dma_get_residue(void) 697 { 698 return parport_ip32_dma.left; 699 } 700 701 /** 702 * parport_ip32_dma_register - initialize DMA engine 703 * 704 * Returns zero for success. 705 */ 706 static int parport_ip32_dma_register(void) 707 { 708 int err; 709 710 spin_lock_init(&parport_ip32_dma.lock); 711 parport_ip32_dma.irq_on = 1; 712 713 /* Reset DMA controller */ 714 writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat); 715 716 /* Request IRQs */ 717 err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt, 718 0, "parport_ip32", NULL); 719 if (err) 720 goto fail_a; 721 err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt, 722 0, "parport_ip32", NULL); 723 if (err) 724 goto fail_b; 725 #if DEBUG_PARPORT_IP32 726 /* FIXME - what is this IRQ for? */ 727 err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt, 728 0, "parport_ip32", NULL); 729 if (err) 730 goto fail_merr; 731 #endif 732 return 0; 733 734 #if DEBUG_PARPORT_IP32 735 fail_merr: 736 free_irq(MACEISA_PAR_CTXB_IRQ, NULL); 737 #endif 738 fail_b: 739 free_irq(MACEISA_PAR_CTXA_IRQ, NULL); 740 fail_a: 741 return err; 742 } 743 744 /** 745 * parport_ip32_dma_unregister - release and free resources for DMA engine 746 */ 747 static void parport_ip32_dma_unregister(void) 748 { 749 #if DEBUG_PARPORT_IP32 750 free_irq(MACEISA_PAR_MERR_IRQ, NULL); 751 #endif 752 free_irq(MACEISA_PAR_CTXB_IRQ, NULL); 753 free_irq(MACEISA_PAR_CTXA_IRQ, NULL); 754 } 755 756 /*--- Interrupt handlers and associates --------------------------------*/ 757 758 /** 759 * parport_ip32_wakeup - wakes up code waiting for an interrupt 760 * @p: pointer to &struct parport 761 */ 762 static inline void parport_ip32_wakeup(struct parport *p) 763 { 764 struct parport_ip32_private * const priv = p->physport->private_data; 765 complete(&priv->irq_complete); 766 } 767 768 /** 769 * parport_ip32_interrupt - interrupt handler 770 * @irq: interrupt number 771 * @dev_id: pointer to &struct parport 772 * 773 * Caught interrupts are forwarded to the upper parport layer if IRQ_mode is 774 * %PARPORT_IP32_IRQ_FWD. 775 */ 776 static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id) 777 { 778 struct parport * const p = dev_id; 779 struct parport_ip32_private * const priv = p->physport->private_data; 780 enum parport_ip32_irq_mode irq_mode = priv->irq_mode; 781 switch (irq_mode) { 782 case PARPORT_IP32_IRQ_FWD: 783 parport_generic_irq(irq, p); 784 break; 785 case PARPORT_IP32_IRQ_HERE: 786 parport_ip32_wakeup(p); 787 break; 788 } 789 return IRQ_HANDLED; 790 } 791 792 /*--- Some utility function to manipulate ECR register -----------------*/ 793 794 /** 795 * parport_ip32_read_econtrol - read contents of the ECR register 796 * @p: pointer to &struct parport 797 */ 798 static inline unsigned int parport_ip32_read_econtrol(struct parport *p) 799 { 800 struct parport_ip32_private * const priv = p->physport->private_data; 801 return readb(priv->regs.ecr); 802 } 803 804 /** 805 * parport_ip32_write_econtrol - write new contents to the ECR register 806 * @p: pointer to &struct parport 807 * @c: new value to write 808 */ 809 static inline void parport_ip32_write_econtrol(struct parport *p, 810 unsigned int c) 811 { 812 struct parport_ip32_private * const priv = p->physport->private_data; 813 writeb(c, priv->regs.ecr); 814 } 815 816 /** 817 * parport_ip32_frob_econtrol - change bits from the ECR register 818 * @p: pointer to &struct parport 819 * @mask: bit mask of bits to change 820 * @val: new value for changed bits 821 * 822 * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits 823 * in @val, and write the result to the ECR. 824 */ 825 static inline void parport_ip32_frob_econtrol(struct parport *p, 826 unsigned int mask, 827 unsigned int val) 828 { 829 unsigned int c; 830 c = (parport_ip32_read_econtrol(p) & ~mask) ^ val; 831 parport_ip32_write_econtrol(p, c); 832 } 833 834 /** 835 * parport_ip32_set_mode - change mode of ECP port 836 * @p: pointer to &struct parport 837 * @mode: new mode to write in ECR 838 * 839 * ECR is reset in a sane state (interrupts and DMA disabled), and placed in 840 * mode @mode. Go through PS2 mode if needed. 841 */ 842 static void parport_ip32_set_mode(struct parport *p, unsigned int mode) 843 { 844 unsigned int omode; 845 846 mode &= ECR_MODE_MASK; 847 omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK; 848 849 if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2 850 || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) { 851 /* We have to go through PS2 mode */ 852 unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 853 parport_ip32_write_econtrol(p, ecr); 854 } 855 parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR); 856 } 857 858 /*--- Basic functions needed for parport -------------------------------*/ 859 860 /** 861 * parport_ip32_read_data - return current contents of the DATA register 862 * @p: pointer to &struct parport 863 */ 864 static inline unsigned char parport_ip32_read_data(struct parport *p) 865 { 866 struct parport_ip32_private * const priv = p->physport->private_data; 867 return readb(priv->regs.data); 868 } 869 870 /** 871 * parport_ip32_write_data - set new contents for the DATA register 872 * @p: pointer to &struct parport 873 * @d: new value to write 874 */ 875 static inline void parport_ip32_write_data(struct parport *p, unsigned char d) 876 { 877 struct parport_ip32_private * const priv = p->physport->private_data; 878 writeb(d, priv->regs.data); 879 } 880 881 /** 882 * parport_ip32_read_status - return current contents of the DSR register 883 * @p: pointer to &struct parport 884 */ 885 static inline unsigned char parport_ip32_read_status(struct parport *p) 886 { 887 struct parport_ip32_private * const priv = p->physport->private_data; 888 return readb(priv->regs.dsr); 889 } 890 891 /** 892 * __parport_ip32_read_control - return cached contents of the DCR register 893 * @p: pointer to &struct parport 894 */ 895 static inline unsigned int __parport_ip32_read_control(struct parport *p) 896 { 897 struct parport_ip32_private * const priv = p->physport->private_data; 898 return priv->dcr_cache; /* use soft copy */ 899 } 900 901 /** 902 * __parport_ip32_write_control - set new contents for the DCR register 903 * @p: pointer to &struct parport 904 * @c: new value to write 905 */ 906 static inline void __parport_ip32_write_control(struct parport *p, 907 unsigned int c) 908 { 909 struct parport_ip32_private * const priv = p->physport->private_data; 910 CHECK_EXTRA_BITS(p, c, priv->dcr_writable); 911 c &= priv->dcr_writable; /* only writable bits */ 912 writeb(c, priv->regs.dcr); 913 priv->dcr_cache = c; /* update soft copy */ 914 } 915 916 /** 917 * __parport_ip32_frob_control - change bits from the DCR register 918 * @p: pointer to &struct parport 919 * @mask: bit mask of bits to change 920 * @val: new value for changed bits 921 * 922 * This is equivalent to read from the DCR, mask out the bits in @mask, 923 * exclusive-or with the bits in @val, and write the result to the DCR. 924 * Actually, the cached contents of the DCR is used. 925 */ 926 static inline void __parport_ip32_frob_control(struct parport *p, 927 unsigned int mask, 928 unsigned int val) 929 { 930 unsigned int c; 931 c = (__parport_ip32_read_control(p) & ~mask) ^ val; 932 __parport_ip32_write_control(p, c); 933 } 934 935 /** 936 * parport_ip32_read_control - return cached contents of the DCR register 937 * @p: pointer to &struct parport 938 * 939 * The return value is masked so as to only return the value of %DCR_STROBE, 940 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 941 */ 942 static inline unsigned char parport_ip32_read_control(struct parport *p) 943 { 944 const unsigned int rm = 945 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 946 return __parport_ip32_read_control(p) & rm; 947 } 948 949 /** 950 * parport_ip32_write_control - set new contents for the DCR register 951 * @p: pointer to &struct parport 952 * @c: new value to write 953 * 954 * The value is masked so as to only change the value of %DCR_STROBE, 955 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 956 */ 957 static inline void parport_ip32_write_control(struct parport *p, 958 unsigned char c) 959 { 960 const unsigned int wm = 961 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 962 CHECK_EXTRA_BITS(p, c, wm); 963 __parport_ip32_frob_control(p, wm, c & wm); 964 } 965 966 /** 967 * parport_ip32_frob_control - change bits from the DCR register 968 * @p: pointer to &struct parport 969 * @mask: bit mask of bits to change 970 * @val: new value for changed bits 971 * 972 * This differs from __parport_ip32_frob_control() in that it only allows to 973 * change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 974 */ 975 static inline unsigned char parport_ip32_frob_control(struct parport *p, 976 unsigned char mask, 977 unsigned char val) 978 { 979 const unsigned int wm = 980 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 981 CHECK_EXTRA_BITS(p, mask, wm); 982 CHECK_EXTRA_BITS(p, val, wm); 983 __parport_ip32_frob_control(p, mask & wm, val & wm); 984 return parport_ip32_read_control(p); 985 } 986 987 /** 988 * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK 989 * @p: pointer to &struct parport 990 */ 991 static inline void parport_ip32_disable_irq(struct parport *p) 992 { 993 __parport_ip32_frob_control(p, DCR_IRQ, 0); 994 } 995 996 /** 997 * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK 998 * @p: pointer to &struct parport 999 */ 1000 static inline void parport_ip32_enable_irq(struct parport *p) 1001 { 1002 __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ); 1003 } 1004 1005 /** 1006 * parport_ip32_data_forward - enable host-to-peripheral communications 1007 * @p: pointer to &struct parport 1008 * 1009 * Enable the data line drivers, for 8-bit host-to-peripheral communications. 1010 */ 1011 static inline void parport_ip32_data_forward(struct parport *p) 1012 { 1013 __parport_ip32_frob_control(p, DCR_DIR, 0); 1014 } 1015 1016 /** 1017 * parport_ip32_data_reverse - enable peripheral-to-host communications 1018 * @p: pointer to &struct parport 1019 * 1020 * Place the data bus in a high impedance state, if @p->modes has the 1021 * PARPORT_MODE_TRISTATE bit set. 1022 */ 1023 static inline void parport_ip32_data_reverse(struct parport *p) 1024 { 1025 __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR); 1026 } 1027 1028 /** 1029 * parport_ip32_init_state - for core parport code 1030 * @dev: pointer to &struct pardevice 1031 * @s: pointer to &struct parport_state to initialize 1032 */ 1033 static void parport_ip32_init_state(struct pardevice *dev, 1034 struct parport_state *s) 1035 { 1036 s->u.ip32.dcr = DCR_SELECT | DCR_nINIT; 1037 s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 1038 } 1039 1040 /** 1041 * parport_ip32_save_state - for core parport code 1042 * @p: pointer to &struct parport 1043 * @s: pointer to &struct parport_state to save state to 1044 */ 1045 static void parport_ip32_save_state(struct parport *p, 1046 struct parport_state *s) 1047 { 1048 s->u.ip32.dcr = __parport_ip32_read_control(p); 1049 s->u.ip32.ecr = parport_ip32_read_econtrol(p); 1050 } 1051 1052 /** 1053 * parport_ip32_restore_state - for core parport code 1054 * @p: pointer to &struct parport 1055 * @s: pointer to &struct parport_state to restore state from 1056 */ 1057 static void parport_ip32_restore_state(struct parport *p, 1058 struct parport_state *s) 1059 { 1060 parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK); 1061 parport_ip32_write_econtrol(p, s->u.ip32.ecr); 1062 __parport_ip32_write_control(p, s->u.ip32.dcr); 1063 } 1064 1065 /*--- EPP mode functions -----------------------------------------------*/ 1066 1067 /** 1068 * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode 1069 * @p: pointer to &struct parport 1070 * 1071 * Returns 1 if the Timeout bit is clear, and 0 otherwise. 1072 */ 1073 static unsigned int parport_ip32_clear_epp_timeout(struct parport *p) 1074 { 1075 struct parport_ip32_private * const priv = p->physport->private_data; 1076 unsigned int cleared; 1077 1078 if (!(parport_ip32_read_status(p) & DSR_TIMEOUT)) 1079 cleared = 1; 1080 else { 1081 unsigned int r; 1082 /* To clear timeout some chips require double read */ 1083 parport_ip32_read_status(p); 1084 r = parport_ip32_read_status(p); 1085 /* Some reset by writing 1 */ 1086 writeb(r | DSR_TIMEOUT, priv->regs.dsr); 1087 /* Others by writing 0 */ 1088 writeb(r & ~DSR_TIMEOUT, priv->regs.dsr); 1089 1090 r = parport_ip32_read_status(p); 1091 cleared = !(r & DSR_TIMEOUT); 1092 } 1093 1094 pr_trace(p, "(): %s", cleared ? "cleared" : "failed"); 1095 return cleared; 1096 } 1097 1098 /** 1099 * parport_ip32_epp_read - generic EPP read function 1100 * @eppreg: I/O register to read from 1101 * @p: pointer to &struct parport 1102 * @buf: buffer to store read data 1103 * @len: length of buffer @buf 1104 * @flags: may be PARPORT_EPP_FAST 1105 */ 1106 static size_t parport_ip32_epp_read(void __iomem *eppreg, 1107 struct parport *p, void *buf, 1108 size_t len, int flags) 1109 { 1110 struct parport_ip32_private * const priv = p->physport->private_data; 1111 size_t got; 1112 parport_ip32_set_mode(p, ECR_MODE_EPP); 1113 parport_ip32_data_reverse(p); 1114 parport_ip32_write_control(p, DCR_nINIT); 1115 if ((flags & PARPORT_EPP_FAST) && (len > 1)) { 1116 readsb(eppreg, buf, len); 1117 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1118 parport_ip32_clear_epp_timeout(p); 1119 return -EIO; 1120 } 1121 got = len; 1122 } else { 1123 u8 *bufp = buf; 1124 for (got = 0; got < len; got++) { 1125 *bufp++ = readb(eppreg); 1126 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1127 parport_ip32_clear_epp_timeout(p); 1128 break; 1129 } 1130 } 1131 } 1132 parport_ip32_data_forward(p); 1133 parport_ip32_set_mode(p, ECR_MODE_PS2); 1134 return got; 1135 } 1136 1137 /** 1138 * parport_ip32_epp_write - generic EPP write function 1139 * @eppreg: I/O register to write to 1140 * @p: pointer to &struct parport 1141 * @buf: buffer of data to write 1142 * @len: length of buffer @buf 1143 * @flags: may be PARPORT_EPP_FAST 1144 */ 1145 static size_t parport_ip32_epp_write(void __iomem *eppreg, 1146 struct parport *p, const void *buf, 1147 size_t len, int flags) 1148 { 1149 struct parport_ip32_private * const priv = p->physport->private_data; 1150 size_t written; 1151 parport_ip32_set_mode(p, ECR_MODE_EPP); 1152 parport_ip32_data_forward(p); 1153 parport_ip32_write_control(p, DCR_nINIT); 1154 if ((flags & PARPORT_EPP_FAST) && (len > 1)) { 1155 writesb(eppreg, buf, len); 1156 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1157 parport_ip32_clear_epp_timeout(p); 1158 return -EIO; 1159 } 1160 written = len; 1161 } else { 1162 const u8 *bufp = buf; 1163 for (written = 0; written < len; written++) { 1164 writeb(*bufp++, eppreg); 1165 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1166 parport_ip32_clear_epp_timeout(p); 1167 break; 1168 } 1169 } 1170 } 1171 parport_ip32_set_mode(p, ECR_MODE_PS2); 1172 return written; 1173 } 1174 1175 /** 1176 * parport_ip32_epp_read_data - read a block of data in EPP mode 1177 * @p: pointer to &struct parport 1178 * @buf: buffer to store read data 1179 * @len: length of buffer @buf 1180 * @flags: may be PARPORT_EPP_FAST 1181 */ 1182 static size_t parport_ip32_epp_read_data(struct parport *p, void *buf, 1183 size_t len, int flags) 1184 { 1185 struct parport_ip32_private * const priv = p->physport->private_data; 1186 return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags); 1187 } 1188 1189 /** 1190 * parport_ip32_epp_write_data - write a block of data in EPP mode 1191 * @p: pointer to &struct parport 1192 * @buf: buffer of data to write 1193 * @len: length of buffer @buf 1194 * @flags: may be PARPORT_EPP_FAST 1195 */ 1196 static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf, 1197 size_t len, int flags) 1198 { 1199 struct parport_ip32_private * const priv = p->physport->private_data; 1200 return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags); 1201 } 1202 1203 /** 1204 * parport_ip32_epp_read_addr - read a block of addresses in EPP mode 1205 * @p: pointer to &struct parport 1206 * @buf: buffer to store read data 1207 * @len: length of buffer @buf 1208 * @flags: may be PARPORT_EPP_FAST 1209 */ 1210 static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf, 1211 size_t len, int flags) 1212 { 1213 struct parport_ip32_private * const priv = p->physport->private_data; 1214 return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags); 1215 } 1216 1217 /** 1218 * parport_ip32_epp_write_addr - write a block of addresses in EPP mode 1219 * @p: pointer to &struct parport 1220 * @buf: buffer of data to write 1221 * @len: length of buffer @buf 1222 * @flags: may be PARPORT_EPP_FAST 1223 */ 1224 static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf, 1225 size_t len, int flags) 1226 { 1227 struct parport_ip32_private * const priv = p->physport->private_data; 1228 return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags); 1229 } 1230 1231 /*--- ECP mode functions (FIFO) ----------------------------------------*/ 1232 1233 /** 1234 * parport_ip32_fifo_wait_break - check if the waiting function should return 1235 * @p: pointer to &struct parport 1236 * @expire: timeout expiring date, in jiffies 1237 * 1238 * parport_ip32_fifo_wait_break() checks if the waiting function should return 1239 * immediately or not. The break conditions are: 1240 * - expired timeout; 1241 * - a pending signal; 1242 * - nFault asserted low. 1243 * This function also calls cond_resched(). 1244 */ 1245 static unsigned int parport_ip32_fifo_wait_break(struct parport *p, 1246 unsigned long expire) 1247 { 1248 cond_resched(); 1249 if (time_after(jiffies, expire)) { 1250 pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name); 1251 return 1; 1252 } 1253 if (signal_pending(current)) { 1254 pr_debug1(PPIP32 "%s: Signal pending\n", p->name); 1255 return 1; 1256 } 1257 if (!(parport_ip32_read_status(p) & DSR_nFAULT)) { 1258 pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name); 1259 return 1; 1260 } 1261 return 0; 1262 } 1263 1264 /** 1265 * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling) 1266 * @p: pointer to &struct parport 1267 * 1268 * Returns the number of bytes that can safely be written in the FIFO. A 1269 * return value of zero means that the calling function should terminate as 1270 * fast as possible. 1271 */ 1272 static unsigned int parport_ip32_fwp_wait_polling(struct parport *p) 1273 { 1274 struct parport_ip32_private * const priv = p->physport->private_data; 1275 struct parport * const physport = p->physport; 1276 unsigned long expire; 1277 unsigned int count; 1278 unsigned int ecr; 1279 1280 expire = jiffies + physport->cad->timeout; 1281 count = 0; 1282 while (1) { 1283 if (parport_ip32_fifo_wait_break(p, expire)) 1284 break; 1285 1286 /* Check FIFO state. We do nothing when the FIFO is nor full, 1287 * nor empty. It appears that the FIFO full bit is not always 1288 * reliable, the FIFO state is sometimes wrongly reported, and 1289 * the chip gets confused if we give it another byte. */ 1290 ecr = parport_ip32_read_econtrol(p); 1291 if (ecr & ECR_F_EMPTY) { 1292 /* FIFO is empty, fill it up */ 1293 count = priv->fifo_depth; 1294 break; 1295 } 1296 1297 /* Wait a moment... */ 1298 udelay(FIFO_POLLING_INTERVAL); 1299 } /* while (1) */ 1300 1301 return count; 1302 } 1303 1304 /** 1305 * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven) 1306 * @p: pointer to &struct parport 1307 * 1308 * Returns the number of bytes that can safely be written in the FIFO. A 1309 * return value of zero means that the calling function should terminate as 1310 * fast as possible. 1311 */ 1312 static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p) 1313 { 1314 static unsigned int lost_interrupt = 0; 1315 struct parport_ip32_private * const priv = p->physport->private_data; 1316 struct parport * const physport = p->physport; 1317 unsigned long nfault_timeout; 1318 unsigned long expire; 1319 unsigned int count; 1320 unsigned int ecr; 1321 1322 nfault_timeout = min((unsigned long)physport->cad->timeout, 1323 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT)); 1324 expire = jiffies + physport->cad->timeout; 1325 count = 0; 1326 while (1) { 1327 if (parport_ip32_fifo_wait_break(p, expire)) 1328 break; 1329 1330 /* Initialize mutex used to take interrupts into account */ 1331 INIT_COMPLETION(priv->irq_complete); 1332 1333 /* Enable serviceIntr */ 1334 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1335 1336 /* Enabling serviceIntr while the FIFO is empty does not 1337 * always generate an interrupt, so check for emptiness 1338 * now. */ 1339 ecr = parport_ip32_read_econtrol(p); 1340 if (!(ecr & ECR_F_EMPTY)) { 1341 /* FIFO is not empty: wait for an interrupt or a 1342 * timeout to occur */ 1343 wait_for_completion_interruptible_timeout( 1344 &priv->irq_complete, nfault_timeout); 1345 ecr = parport_ip32_read_econtrol(p); 1346 if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR) 1347 && !lost_interrupt) { 1348 printk(KERN_WARNING PPIP32 1349 "%s: lost interrupt in %s\n", 1350 p->name, __func__); 1351 lost_interrupt = 1; 1352 } 1353 } 1354 1355 /* Disable serviceIntr */ 1356 parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR); 1357 1358 /* Check FIFO state */ 1359 if (ecr & ECR_F_EMPTY) { 1360 /* FIFO is empty, fill it up */ 1361 count = priv->fifo_depth; 1362 break; 1363 } else if (ecr & ECR_SERVINTR) { 1364 /* FIFO is not empty, but we know that can safely push 1365 * writeIntrThreshold bytes into it */ 1366 count = priv->writeIntrThreshold; 1367 break; 1368 } 1369 /* FIFO is not empty, and we did not get any interrupt. 1370 * Either it's time to check for nFault, or a signal is 1371 * pending. This is verified in 1372 * parport_ip32_fifo_wait_break(), so we continue the loop. */ 1373 } /* while (1) */ 1374 1375 return count; 1376 } 1377 1378 /** 1379 * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode) 1380 * @p: pointer to &struct parport 1381 * @buf: buffer of data to write 1382 * @len: length of buffer @buf 1383 * 1384 * Uses PIO to write the contents of the buffer @buf into the parallel port 1385 * FIFO. Returns the number of bytes that were actually written. It can work 1386 * with or without the help of interrupts. The parallel port must be 1387 * correctly initialized before calling parport_ip32_fifo_write_block_pio(). 1388 */ 1389 static size_t parport_ip32_fifo_write_block_pio(struct parport *p, 1390 const void *buf, size_t len) 1391 { 1392 struct parport_ip32_private * const priv = p->physport->private_data; 1393 const u8 *bufp = buf; 1394 size_t left = len; 1395 1396 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1397 1398 while (left > 0) { 1399 unsigned int count; 1400 1401 count = (p->irq == PARPORT_IRQ_NONE) ? 1402 parport_ip32_fwp_wait_polling(p) : 1403 parport_ip32_fwp_wait_interrupt(p); 1404 if (count == 0) 1405 break; /* Transmission should be stopped */ 1406 if (count > left) 1407 count = left; 1408 if (count == 1) { 1409 writeb(*bufp, priv->regs.fifo); 1410 bufp++, left--; 1411 } else { 1412 writesb(priv->regs.fifo, bufp, count); 1413 bufp += count, left -= count; 1414 } 1415 } 1416 1417 priv->irq_mode = PARPORT_IP32_IRQ_FWD; 1418 1419 return len - left; 1420 } 1421 1422 /** 1423 * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode) 1424 * @p: pointer to &struct parport 1425 * @buf: buffer of data to write 1426 * @len: length of buffer @buf 1427 * 1428 * Uses DMA to write the contents of the buffer @buf into the parallel port 1429 * FIFO. Returns the number of bytes that were actually written. The 1430 * parallel port must be correctly initialized before calling 1431 * parport_ip32_fifo_write_block_dma(). 1432 */ 1433 static size_t parport_ip32_fifo_write_block_dma(struct parport *p, 1434 const void *buf, size_t len) 1435 { 1436 struct parport_ip32_private * const priv = p->physport->private_data; 1437 struct parport * const physport = p->physport; 1438 unsigned long nfault_timeout; 1439 unsigned long expire; 1440 size_t written; 1441 unsigned int ecr; 1442 1443 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1444 1445 parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len); 1446 INIT_COMPLETION(priv->irq_complete); 1447 parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN); 1448 1449 nfault_timeout = min((unsigned long)physport->cad->timeout, 1450 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT)); 1451 expire = jiffies + physport->cad->timeout; 1452 while (1) { 1453 if (parport_ip32_fifo_wait_break(p, expire)) 1454 break; 1455 wait_for_completion_interruptible_timeout(&priv->irq_complete, 1456 nfault_timeout); 1457 ecr = parport_ip32_read_econtrol(p); 1458 if (ecr & ECR_SERVINTR) 1459 break; /* DMA transfer just finished */ 1460 } 1461 parport_ip32_dma_stop(); 1462 written = len - parport_ip32_dma_get_residue(); 1463 1464 priv->irq_mode = PARPORT_IP32_IRQ_FWD; 1465 1466 return written; 1467 } 1468 1469 /** 1470 * parport_ip32_fifo_write_block - write a block of data 1471 * @p: pointer to &struct parport 1472 * @buf: buffer of data to write 1473 * @len: length of buffer @buf 1474 * 1475 * Uses PIO or DMA to write the contents of the buffer @buf into the parallel 1476 * p FIFO. Returns the number of bytes that were actually written. 1477 */ 1478 static size_t parport_ip32_fifo_write_block(struct parport *p, 1479 const void *buf, size_t len) 1480 { 1481 size_t written = 0; 1482 if (len) 1483 /* FIXME - Maybe some threshold value should be set for @len 1484 * under which we revert to PIO mode? */ 1485 written = (p->modes & PARPORT_MODE_DMA) ? 1486 parport_ip32_fifo_write_block_dma(p, buf, len) : 1487 parport_ip32_fifo_write_block_pio(p, buf, len); 1488 return written; 1489 } 1490 1491 /** 1492 * parport_ip32_drain_fifo - wait for FIFO to empty 1493 * @p: pointer to &struct parport 1494 * @timeout: timeout, in jiffies 1495 * 1496 * This function waits for FIFO to empty. It returns 1 when FIFO is empty, or 1497 * 0 if the timeout @timeout is reached before, or if a signal is pending. 1498 */ 1499 static unsigned int parport_ip32_drain_fifo(struct parport *p, 1500 unsigned long timeout) 1501 { 1502 unsigned long expire = jiffies + timeout; 1503 unsigned int polling_interval; 1504 unsigned int counter; 1505 1506 /* Busy wait for approx. 200us */ 1507 for (counter = 0; counter < 40; counter++) { 1508 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY) 1509 break; 1510 if (time_after(jiffies, expire)) 1511 break; 1512 if (signal_pending(current)) 1513 break; 1514 udelay(5); 1515 } 1516 /* Poll slowly. Polling interval starts with 1 millisecond, and is 1517 * increased exponentially until 128. */ 1518 polling_interval = 1; /* msecs */ 1519 while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) { 1520 if (time_after_eq(jiffies, expire)) 1521 break; 1522 msleep_interruptible(polling_interval); 1523 if (signal_pending(current)) 1524 break; 1525 if (polling_interval < 128) 1526 polling_interval *= 2; 1527 } 1528 1529 return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY); 1530 } 1531 1532 /** 1533 * parport_ip32_get_fifo_residue - reset FIFO 1534 * @p: pointer to &struct parport 1535 * @mode: current operation mode (ECR_MODE_PPF or ECR_MODE_ECP) 1536 * 1537 * This function resets FIFO, and returns the number of bytes remaining in it. 1538 */ 1539 static unsigned int parport_ip32_get_fifo_residue(struct parport *p, 1540 unsigned int mode) 1541 { 1542 struct parport_ip32_private * const priv = p->physport->private_data; 1543 unsigned int residue; 1544 unsigned int cnfga; 1545 1546 /* FIXME - We are missing one byte if the printer is off-line. I 1547 * don't know how to detect this. It looks that the full bit is not 1548 * always reliable. For the moment, the problem is avoided in most 1549 * cases by testing for BUSY in parport_ip32_compat_write_data(). 1550 */ 1551 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY) 1552 residue = 0; 1553 else { 1554 pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name); 1555 1556 /* Stop all transfers. 1557 * 1558 * Microsoft's document instructs to drive DCR_STROBE to 0, 1559 * but it doesn't work (at least in Compatibility mode, not 1560 * tested in ECP mode). Switching directly to Test mode (as 1561 * in parport_pc) is not an option: it does confuse the port, 1562 * ECP service interrupts are no more working after that. A 1563 * hard reset is then needed to revert to a sane state. 1564 * 1565 * Let's hope that the FIFO is really stuck and that the 1566 * peripheral doesn't wake up now. 1567 */ 1568 parport_ip32_frob_control(p, DCR_STROBE, 0); 1569 1570 /* Fill up FIFO */ 1571 for (residue = priv->fifo_depth; residue > 0; residue--) { 1572 if (parport_ip32_read_econtrol(p) & ECR_F_FULL) 1573 break; 1574 writeb(0x00, priv->regs.fifo); 1575 } 1576 } 1577 if (residue) 1578 pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n", 1579 p->name, residue, 1580 (residue == 1) ? " was" : "s were"); 1581 1582 /* Now reset the FIFO */ 1583 parport_ip32_set_mode(p, ECR_MODE_PS2); 1584 1585 /* Host recovery for ECP mode */ 1586 if (mode == ECR_MODE_ECP) { 1587 parport_ip32_data_reverse(p); 1588 parport_ip32_frob_control(p, DCR_nINIT, 0); 1589 if (parport_wait_peripheral(p, DSR_PERROR, 0)) 1590 pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n", 1591 p->name, __func__); 1592 parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE); 1593 parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT); 1594 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) 1595 pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n", 1596 p->name, __func__); 1597 } 1598 1599 /* Adjust residue if needed */ 1600 parport_ip32_set_mode(p, ECR_MODE_CFG); 1601 cnfga = readb(priv->regs.cnfgA); 1602 if (!(cnfga & CNFGA_nBYTEINTRANS)) { 1603 pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n", 1604 p->name, cnfga); 1605 pr_debug1(PPIP32 "%s: Accounting for extra byte\n", 1606 p->name); 1607 residue++; 1608 } 1609 1610 /* Don't care about partial PWords since we do not support 1611 * PWord != 1 byte. */ 1612 1613 /* Back to forward PS2 mode. */ 1614 parport_ip32_set_mode(p, ECR_MODE_PS2); 1615 parport_ip32_data_forward(p); 1616 1617 return residue; 1618 } 1619 1620 /** 1621 * parport_ip32_compat_write_data - write a block of data in SPP mode 1622 * @p: pointer to &struct parport 1623 * @buf: buffer of data to write 1624 * @len: length of buffer @buf 1625 * @flags: ignored 1626 */ 1627 static size_t parport_ip32_compat_write_data(struct parport *p, 1628 const void *buf, size_t len, 1629 int flags) 1630 { 1631 static unsigned int ready_before = 1; 1632 struct parport_ip32_private * const priv = p->physport->private_data; 1633 struct parport * const physport = p->physport; 1634 size_t written = 0; 1635 1636 /* Special case: a timeout of zero means we cannot call schedule(). 1637 * Also if O_NONBLOCK is set then use the default implementation. */ 1638 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 1639 return parport_ieee1284_write_compat(p, buf, len, flags); 1640 1641 /* Reset FIFO, go in forward mode, and disable ackIntEn */ 1642 parport_ip32_set_mode(p, ECR_MODE_PS2); 1643 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1644 parport_ip32_data_forward(p); 1645 parport_ip32_disable_irq(p); 1646 parport_ip32_set_mode(p, ECR_MODE_PPF); 1647 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 1648 1649 /* Wait for peripheral to become ready */ 1650 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT, 1651 DSR_nBUSY | DSR_nFAULT)) { 1652 /* Avoid to flood the logs */ 1653 if (ready_before) 1654 printk(KERN_INFO PPIP32 "%s: not ready in %s\n", 1655 p->name, __func__); 1656 ready_before = 0; 1657 goto stop; 1658 } 1659 ready_before = 1; 1660 1661 written = parport_ip32_fifo_write_block(p, buf, len); 1662 1663 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */ 1664 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth); 1665 1666 /* Check for a potential residue */ 1667 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF); 1668 1669 /* Then, wait for BUSY to get low. */ 1670 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY)) 1671 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n", 1672 p->name, __func__); 1673 1674 stop: 1675 /* Reset FIFO */ 1676 parport_ip32_set_mode(p, ECR_MODE_PS2); 1677 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1678 1679 return written; 1680 } 1681 1682 /* 1683 * FIXME - Insert here parport_ip32_ecp_read_data(). 1684 */ 1685 1686 /** 1687 * parport_ip32_ecp_write_data - write a block of data in ECP mode 1688 * @p: pointer to &struct parport 1689 * @buf: buffer of data to write 1690 * @len: length of buffer @buf 1691 * @flags: ignored 1692 */ 1693 static size_t parport_ip32_ecp_write_data(struct parport *p, 1694 const void *buf, size_t len, 1695 int flags) 1696 { 1697 static unsigned int ready_before = 1; 1698 struct parport_ip32_private * const priv = p->physport->private_data; 1699 struct parport * const physport = p->physport; 1700 size_t written = 0; 1701 1702 /* Special case: a timeout of zero means we cannot call schedule(). 1703 * Also if O_NONBLOCK is set then use the default implementation. */ 1704 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 1705 return parport_ieee1284_ecp_write_data(p, buf, len, flags); 1706 1707 /* Negotiate to forward mode if necessary. */ 1708 if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 1709 /* Event 47: Set nInit high. */ 1710 parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD, 1711 DCR_nINIT | DCR_AUTOFD); 1712 1713 /* Event 49: PError goes high. */ 1714 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) { 1715 printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s", 1716 p->name, __func__); 1717 physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; 1718 return 0; 1719 } 1720 } 1721 1722 /* Reset FIFO, go in forward mode, and disable ackIntEn */ 1723 parport_ip32_set_mode(p, ECR_MODE_PS2); 1724 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1725 parport_ip32_data_forward(p); 1726 parport_ip32_disable_irq(p); 1727 parport_ip32_set_mode(p, ECR_MODE_ECP); 1728 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 1729 1730 /* Wait for peripheral to become ready */ 1731 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT, 1732 DSR_nBUSY | DSR_nFAULT)) { 1733 /* Avoid to flood the logs */ 1734 if (ready_before) 1735 printk(KERN_INFO PPIP32 "%s: not ready in %s\n", 1736 p->name, __func__); 1737 ready_before = 0; 1738 goto stop; 1739 } 1740 ready_before = 1; 1741 1742 written = parport_ip32_fifo_write_block(p, buf, len); 1743 1744 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */ 1745 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth); 1746 1747 /* Check for a potential residue */ 1748 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP); 1749 1750 /* Then, wait for BUSY to get low. */ 1751 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY)) 1752 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n", 1753 p->name, __func__); 1754 1755 stop: 1756 /* Reset FIFO */ 1757 parport_ip32_set_mode(p, ECR_MODE_PS2); 1758 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1759 1760 return written; 1761 } 1762 1763 /* 1764 * FIXME - Insert here parport_ip32_ecp_write_addr(). 1765 */ 1766 1767 /*--- Default parport operations ---------------------------------------*/ 1768 1769 static __initdata struct parport_operations parport_ip32_ops = { 1770 .write_data = parport_ip32_write_data, 1771 .read_data = parport_ip32_read_data, 1772 1773 .write_control = parport_ip32_write_control, 1774 .read_control = parport_ip32_read_control, 1775 .frob_control = parport_ip32_frob_control, 1776 1777 .read_status = parport_ip32_read_status, 1778 1779 .enable_irq = parport_ip32_enable_irq, 1780 .disable_irq = parport_ip32_disable_irq, 1781 1782 .data_forward = parport_ip32_data_forward, 1783 .data_reverse = parport_ip32_data_reverse, 1784 1785 .init_state = parport_ip32_init_state, 1786 .save_state = parport_ip32_save_state, 1787 .restore_state = parport_ip32_restore_state, 1788 1789 .epp_write_data = parport_ieee1284_epp_write_data, 1790 .epp_read_data = parport_ieee1284_epp_read_data, 1791 .epp_write_addr = parport_ieee1284_epp_write_addr, 1792 .epp_read_addr = parport_ieee1284_epp_read_addr, 1793 1794 .ecp_write_data = parport_ieee1284_ecp_write_data, 1795 .ecp_read_data = parport_ieee1284_ecp_read_data, 1796 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1797 1798 .compat_write_data = parport_ieee1284_write_compat, 1799 .nibble_read_data = parport_ieee1284_read_nibble, 1800 .byte_read_data = parport_ieee1284_read_byte, 1801 1802 .owner = THIS_MODULE, 1803 }; 1804 1805 /*--- Device detection -------------------------------------------------*/ 1806 1807 /** 1808 * parport_ip32_ecp_supported - check for an ECP port 1809 * @p: pointer to the &parport structure 1810 * 1811 * Returns 1 if an ECP port is found, and 0 otherwise. This function actually 1812 * checks if an Extended Control Register seems to be present. On successful 1813 * return, the port is placed in SPP mode. 1814 */ 1815 static __init unsigned int parport_ip32_ecp_supported(struct parport *p) 1816 { 1817 struct parport_ip32_private * const priv = p->physport->private_data; 1818 unsigned int ecr; 1819 1820 ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 1821 writeb(ecr, priv->regs.ecr); 1822 if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY)) 1823 goto fail; 1824 1825 pr_probe(p, "Found working ECR register\n"); 1826 parport_ip32_set_mode(p, ECR_MODE_SPP); 1827 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1828 return 1; 1829 1830 fail: 1831 pr_probe(p, "ECR register not found\n"); 1832 return 0; 1833 } 1834 1835 /** 1836 * parport_ip32_fifo_supported - check for FIFO parameters 1837 * @p: pointer to the &parport structure 1838 * 1839 * Check for FIFO parameters of an Extended Capabilities Port. Returns 1 on 1840 * success, and 0 otherwise. Adjust FIFO parameters in the parport structure. 1841 * On return, the port is placed in SPP mode. 1842 */ 1843 static __init unsigned int parport_ip32_fifo_supported(struct parport *p) 1844 { 1845 struct parport_ip32_private * const priv = p->physport->private_data; 1846 unsigned int configa, configb; 1847 unsigned int pword; 1848 unsigned int i; 1849 1850 /* Configuration mode */ 1851 parport_ip32_set_mode(p, ECR_MODE_CFG); 1852 configa = readb(priv->regs.cnfgA); 1853 configb = readb(priv->regs.cnfgB); 1854 1855 /* Find out PWord size */ 1856 switch (configa & CNFGA_ID_MASK) { 1857 case CNFGA_ID_8: 1858 pword = 1; 1859 break; 1860 case CNFGA_ID_16: 1861 pword = 2; 1862 break; 1863 case CNFGA_ID_32: 1864 pword = 4; 1865 break; 1866 default: 1867 pr_probe(p, "Unknown implementation ID: 0x%0x\n", 1868 (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT); 1869 goto fail; 1870 break; 1871 } 1872 if (pword != 1) { 1873 pr_probe(p, "Unsupported PWord size: %u\n", pword); 1874 goto fail; 1875 } 1876 priv->pword = pword; 1877 pr_probe(p, "PWord is %u bits\n", 8 * priv->pword); 1878 1879 /* Check for compression support */ 1880 writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB); 1881 if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS) 1882 pr_probe(p, "Hardware compression detected (unsupported)\n"); 1883 writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB); 1884 1885 /* Reset FIFO and go in test mode (no interrupt, no DMA) */ 1886 parport_ip32_set_mode(p, ECR_MODE_TST); 1887 1888 /* FIFO must be empty now */ 1889 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) { 1890 pr_probe(p, "FIFO not reset\n"); 1891 goto fail; 1892 } 1893 1894 /* Find out FIFO depth. */ 1895 priv->fifo_depth = 0; 1896 for (i = 0; i < 1024; i++) { 1897 if (readb(priv->regs.ecr) & ECR_F_FULL) { 1898 /* FIFO full */ 1899 priv->fifo_depth = i; 1900 break; 1901 } 1902 writeb((u8)i, priv->regs.fifo); 1903 } 1904 if (i >= 1024) { 1905 pr_probe(p, "Can't fill FIFO\n"); 1906 goto fail; 1907 } 1908 if (!priv->fifo_depth) { 1909 pr_probe(p, "Can't get FIFO depth\n"); 1910 goto fail; 1911 } 1912 pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth); 1913 1914 /* Enable interrupts */ 1915 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1916 1917 /* Find out writeIntrThreshold: number of PWords we know we can write 1918 * if we get an interrupt. */ 1919 priv->writeIntrThreshold = 0; 1920 for (i = 0; i < priv->fifo_depth; i++) { 1921 if (readb(priv->regs.fifo) != (u8)i) { 1922 pr_probe(p, "Invalid data in FIFO\n"); 1923 goto fail; 1924 } 1925 if (!priv->writeIntrThreshold 1926 && readb(priv->regs.ecr) & ECR_SERVINTR) 1927 /* writeIntrThreshold reached */ 1928 priv->writeIntrThreshold = i + 1; 1929 if (i + 1 < priv->fifo_depth 1930 && readb(priv->regs.ecr) & ECR_F_EMPTY) { 1931 /* FIFO empty before the last byte? */ 1932 pr_probe(p, "Data lost in FIFO\n"); 1933 goto fail; 1934 } 1935 } 1936 if (!priv->writeIntrThreshold) { 1937 pr_probe(p, "Can't get writeIntrThreshold\n"); 1938 goto fail; 1939 } 1940 pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold); 1941 1942 /* FIFO must be empty now */ 1943 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) { 1944 pr_probe(p, "Can't empty FIFO\n"); 1945 goto fail; 1946 } 1947 1948 /* Reset FIFO */ 1949 parport_ip32_set_mode(p, ECR_MODE_PS2); 1950 /* Set reverse direction (must be in PS2 mode) */ 1951 parport_ip32_data_reverse(p); 1952 /* Test FIFO, no interrupt, no DMA */ 1953 parport_ip32_set_mode(p, ECR_MODE_TST); 1954 /* Enable interrupts */ 1955 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1956 1957 /* Find out readIntrThreshold: number of PWords we can read if we get 1958 * an interrupt. */ 1959 priv->readIntrThreshold = 0; 1960 for (i = 0; i < priv->fifo_depth; i++) { 1961 writeb(0xaa, priv->regs.fifo); 1962 if (readb(priv->regs.ecr) & ECR_SERVINTR) { 1963 /* readIntrThreshold reached */ 1964 priv->readIntrThreshold = i + 1; 1965 break; 1966 } 1967 } 1968 if (!priv->readIntrThreshold) { 1969 pr_probe(p, "Can't get readIntrThreshold\n"); 1970 goto fail; 1971 } 1972 pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold); 1973 1974 /* Reset ECR */ 1975 parport_ip32_set_mode(p, ECR_MODE_PS2); 1976 parport_ip32_data_forward(p); 1977 parport_ip32_set_mode(p, ECR_MODE_SPP); 1978 return 1; 1979 1980 fail: 1981 priv->fifo_depth = 0; 1982 parport_ip32_set_mode(p, ECR_MODE_SPP); 1983 return 0; 1984 } 1985 1986 /*--- Initialization code ----------------------------------------------*/ 1987 1988 /** 1989 * parport_ip32_make_isa_registers - compute (ISA) register addresses 1990 * @regs: pointer to &struct parport_ip32_regs to fill 1991 * @base: base address of standard and EPP registers 1992 * @base_hi: base address of ECP registers 1993 * @regshift: how much to shift register offset by 1994 * 1995 * Compute register addresses, according to the ISA standard. The addresses 1996 * of the standard and EPP registers are computed from address @base. The 1997 * addresses of the ECP registers are computed from address @base_hi. 1998 */ 1999 static void __init 2000 parport_ip32_make_isa_registers(struct parport_ip32_regs *regs, 2001 void __iomem *base, void __iomem *base_hi, 2002 unsigned int regshift) 2003 { 2004 #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift)) 2005 #define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift)) 2006 *regs = (struct parport_ip32_regs){ 2007 .data = r_base(0), 2008 .dsr = r_base(1), 2009 .dcr = r_base(2), 2010 .eppAddr = r_base(3), 2011 .eppData0 = r_base(4), 2012 .eppData1 = r_base(5), 2013 .eppData2 = r_base(6), 2014 .eppData3 = r_base(7), 2015 .ecpAFifo = r_base(0), 2016 .fifo = r_base_hi(0), 2017 .cnfgA = r_base_hi(0), 2018 .cnfgB = r_base_hi(1), 2019 .ecr = r_base_hi(2) 2020 }; 2021 #undef r_base_hi 2022 #undef r_base 2023 } 2024 2025 /** 2026 * parport_ip32_probe_port - probe and register IP32 built-in parallel port 2027 * 2028 * Returns the new allocated &parport structure. On error, an error code is 2029 * encoded in return value with the ERR_PTR function. 2030 */ 2031 static __init struct parport *parport_ip32_probe_port(void) 2032 { 2033 struct parport_ip32_regs regs; 2034 struct parport_ip32_private *priv = NULL; 2035 struct parport_operations *ops = NULL; 2036 struct parport *p = NULL; 2037 int err; 2038 2039 parport_ip32_make_isa_registers(®s, &mace->isa.parallel, 2040 &mace->isa.ecp1284, 8 /* regshift */); 2041 2042 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); 2043 priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL); 2044 p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops); 2045 if (ops == NULL || priv == NULL || p == NULL) { 2046 err = -ENOMEM; 2047 goto fail; 2048 } 2049 p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel); 2050 p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284); 2051 p->private_data = priv; 2052 2053 *ops = parport_ip32_ops; 2054 *priv = (struct parport_ip32_private){ 2055 .regs = regs, 2056 .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT | 2057 DCR_AUTOFD | DCR_STROBE, 2058 .irq_mode = PARPORT_IP32_IRQ_FWD, 2059 }; 2060 init_completion(&priv->irq_complete); 2061 2062 /* Probe port. */ 2063 if (!parport_ip32_ecp_supported(p)) { 2064 err = -ENODEV; 2065 goto fail; 2066 } 2067 parport_ip32_dump_state(p, "begin init", 0); 2068 2069 /* We found what looks like a working ECR register. Simply assume 2070 * that all modes are correctly supported. Enable basic modes. */ 2071 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2072 p->modes |= PARPORT_MODE_TRISTATE; 2073 2074 if (!parport_ip32_fifo_supported(p)) { 2075 printk(KERN_WARNING PPIP32 2076 "%s: error: FIFO disabled\n", p->name); 2077 /* Disable hardware modes depending on a working FIFO. */ 2078 features &= ~PARPORT_IP32_ENABLE_SPP; 2079 features &= ~PARPORT_IP32_ENABLE_ECP; 2080 /* DMA is not needed if FIFO is not supported. */ 2081 features &= ~PARPORT_IP32_ENABLE_DMA; 2082 } 2083 2084 /* Request IRQ */ 2085 if (features & PARPORT_IP32_ENABLE_IRQ) { 2086 int irq = MACEISA_PARALLEL_IRQ; 2087 if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) { 2088 printk(KERN_WARNING PPIP32 2089 "%s: error: IRQ disabled\n", p->name); 2090 /* DMA cannot work without interrupts. */ 2091 features &= ~PARPORT_IP32_ENABLE_DMA; 2092 } else { 2093 pr_probe(p, "Interrupt support enabled\n"); 2094 p->irq = irq; 2095 priv->dcr_writable |= DCR_IRQ; 2096 } 2097 } 2098 2099 /* Allocate DMA resources */ 2100 if (features & PARPORT_IP32_ENABLE_DMA) { 2101 if (parport_ip32_dma_register()) 2102 printk(KERN_WARNING PPIP32 2103 "%s: error: DMA disabled\n", p->name); 2104 else { 2105 pr_probe(p, "DMA support enabled\n"); 2106 p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */ 2107 p->modes |= PARPORT_MODE_DMA; 2108 } 2109 } 2110 2111 if (features & PARPORT_IP32_ENABLE_SPP) { 2112 /* Enable compatibility FIFO mode */ 2113 p->ops->compat_write_data = parport_ip32_compat_write_data; 2114 p->modes |= PARPORT_MODE_COMPAT; 2115 pr_probe(p, "Hardware support for SPP mode enabled\n"); 2116 } 2117 if (features & PARPORT_IP32_ENABLE_EPP) { 2118 /* Set up access functions to use EPP hardware. */ 2119 p->ops->epp_read_data = parport_ip32_epp_read_data; 2120 p->ops->epp_write_data = parport_ip32_epp_write_data; 2121 p->ops->epp_read_addr = parport_ip32_epp_read_addr; 2122 p->ops->epp_write_addr = parport_ip32_epp_write_addr; 2123 p->modes |= PARPORT_MODE_EPP; 2124 pr_probe(p, "Hardware support for EPP mode enabled\n"); 2125 } 2126 if (features & PARPORT_IP32_ENABLE_ECP) { 2127 /* Enable ECP FIFO mode */ 2128 p->ops->ecp_write_data = parport_ip32_ecp_write_data; 2129 /* FIXME - not implemented */ 2130 /* p->ops->ecp_read_data = parport_ip32_ecp_read_data; */ 2131 /* p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */ 2132 p->modes |= PARPORT_MODE_ECP; 2133 pr_probe(p, "Hardware support for ECP mode enabled\n"); 2134 } 2135 2136 /* Initialize the port with sensible values */ 2137 parport_ip32_set_mode(p, ECR_MODE_PS2); 2138 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 2139 parport_ip32_data_forward(p); 2140 parport_ip32_disable_irq(p); 2141 parport_ip32_write_data(p, 0x00); 2142 parport_ip32_dump_state(p, "end init", 0); 2143 2144 /* Print out what we found */ 2145 printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)", 2146 p->name, p->base, p->base_hi); 2147 if (p->irq != PARPORT_IRQ_NONE) 2148 printk(", irq %d", p->irq); 2149 printk(" ["); 2150 #define printmode(x) if (p->modes & PARPORT_MODE_##x) \ 2151 printk("%s%s", f++ ? "," : "", #x) 2152 { 2153 unsigned int f = 0; 2154 printmode(PCSPP); 2155 printmode(TRISTATE); 2156 printmode(COMPAT); 2157 printmode(EPP); 2158 printmode(ECP); 2159 printmode(DMA); 2160 } 2161 #undef printmode 2162 printk("]\n"); 2163 2164 parport_announce_port(p); 2165 return p; 2166 2167 fail: 2168 if (p) 2169 parport_put_port(p); 2170 kfree(priv); 2171 kfree(ops); 2172 return ERR_PTR(err); 2173 } 2174 2175 /** 2176 * parport_ip32_unregister_port - unregister a parallel port 2177 * @p: pointer to the &struct parport 2178 * 2179 * Unregisters a parallel port and free previously allocated resources 2180 * (memory, IRQ, ...). 2181 */ 2182 static __exit void parport_ip32_unregister_port(struct parport *p) 2183 { 2184 struct parport_ip32_private * const priv = p->physport->private_data; 2185 struct parport_operations *ops = p->ops; 2186 2187 parport_remove_port(p); 2188 if (p->modes & PARPORT_MODE_DMA) 2189 parport_ip32_dma_unregister(); 2190 if (p->irq != PARPORT_IRQ_NONE) 2191 free_irq(p->irq, p); 2192 parport_put_port(p); 2193 kfree(priv); 2194 kfree(ops); 2195 } 2196 2197 /** 2198 * parport_ip32_init - module initialization function 2199 */ 2200 static int __init parport_ip32_init(void) 2201 { 2202 pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n"); 2203 pr_debug1(PPIP32 "Compiled on %s, %s\n", __DATE__, __TIME__); 2204 this_port = parport_ip32_probe_port(); 2205 return IS_ERR(this_port) ? PTR_ERR(this_port) : 0; 2206 } 2207 2208 /** 2209 * parport_ip32_exit - module termination function 2210 */ 2211 static void __exit parport_ip32_exit(void) 2212 { 2213 parport_ip32_unregister_port(this_port); 2214 } 2215 2216 /*--- Module stuff -----------------------------------------------------*/ 2217 2218 MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>"); 2219 MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver"); 2220 MODULE_LICENSE("GPL"); 2221 MODULE_VERSION("0.6"); /* update in parport_ip32_init() too */ 2222 2223 module_init(parport_ip32_init); 2224 module_exit(parport_ip32_exit); 2225 2226 module_param(verbose_probing, bool, S_IRUGO); 2227 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization"); 2228 2229 module_param(features, uint, S_IRUGO); 2230 MODULE_PARM_DESC(features, 2231 "Bit mask of features to enable" 2232 ", bit 0: IRQ support" 2233 ", bit 1: DMA support" 2234 ", bit 2: hardware SPP mode" 2235 ", bit 3: hardware EPP mode" 2236 ", bit 4: hardware ECP mode"); 2237 2238 /*--- Inform (X)Emacs about preferred coding style ---------------------*/ 2239 /* 2240 * Local Variables: 2241 * mode: c 2242 * c-file-style: "linux" 2243 * indent-tabs-mode: t 2244 * tab-width: 8 2245 * fill-column: 78 2246 * ispell-local-dictionary: "american" 2247 * End: 2248 */ 2249