1 /* Low-level parallel port routines for built-in port on SGI IP32 2 * 3 * Author: Arnaud Giersch <arnaud.giersch@free.fr> 4 * 5 * Based on parport_pc.c by 6 * Phil Blundell, Tim Waugh, Jose Renau, David Campbell, 7 * Andrea Arcangeli, et al. 8 * 9 * Thanks to Ilya A. Volynets-Evenbakh for his help. 10 * 11 * Copyright (C) 2005, 2006 Arnaud Giersch. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the Free 15 * Software Foundation; either version 2 of the License, or (at your option) 16 * any later version. 17 * 18 * This program is distributed in the hope that it will be useful, but WITHOUT 19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 21 * more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 59 25 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 26 */ 27 28 /* Current status: 29 * 30 * Basic SPP and PS2 modes are supported. 31 * Support for parallel port IRQ is present. 32 * Hardware SPP (a.k.a. compatibility), EPP, and ECP modes are 33 * supported. 34 * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with 35 * or without interrupt support. 36 * 37 * Hardware ECP mode is not fully implemented (ecp_read_data and 38 * ecp_write_addr are actually missing). 39 * 40 * To do: 41 * 42 * Fully implement ECP mode. 43 * EPP and ECP mode need to be tested. I currently do not own any 44 * peripheral supporting these extended mode, and cannot test them. 45 * If DMA mode works well, decide if support for PIO FIFO modes should be 46 * dropped. 47 * Use the io{read,write} family functions when they become available in 48 * the linux-mips.org tree. Note: the MIPS specific functions readsb() 49 * and writesb() are to be translated by ioread8_rep() and iowrite8_rep() 50 * respectively. 51 */ 52 53 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an 54 * IEEE 1284 parallel port driven by a Texas Instrument TL16PIR552PH chip[1]. 55 * This chip supports SPP, bidirectional, EPP and ECP modes. It has a 16 byte 56 * FIFO buffer and supports DMA transfers. 57 * 58 * [1] http://focus.ti.com/docs/prod/folders/print/tl16pir552.html 59 * 60 * Theoretically, we could simply use the parport_pc module. It is however 61 * not so simple. The parport_pc code assumes that the parallel port 62 * registers are port-mapped. On the O2, they are memory-mapped. 63 * Furthermore, each register is replicated on 256 consecutive addresses (as 64 * it is for the built-in serial ports on the same chip). 65 */ 66 67 /*--- Some configuration defines ---------------------------------------*/ 68 69 /* DEBUG_PARPORT_IP32 70 * 0 disable debug 71 * 1 standard level: pr_debug1 is enabled 72 * 2 parport_ip32_dump_state is enabled 73 * >=3 verbose level: pr_debug is enabled 74 */ 75 #if !defined(DEBUG_PARPORT_IP32) 76 # define DEBUG_PARPORT_IP32 0 /* 0 (disabled) for production */ 77 #endif 78 79 /*----------------------------------------------------------------------*/ 80 81 /* Setup DEBUG macros. This is done before any includes, just in case we 82 * activate pr_debug() with DEBUG_PARPORT_IP32 >= 3. 83 */ 84 #if DEBUG_PARPORT_IP32 == 1 85 # warning DEBUG_PARPORT_IP32 == 1 86 #elif DEBUG_PARPORT_IP32 == 2 87 # warning DEBUG_PARPORT_IP32 == 2 88 #elif DEBUG_PARPORT_IP32 >= 3 89 # warning DEBUG_PARPORT_IP32 >= 3 90 # if !defined(DEBUG) 91 # define DEBUG /* enable pr_debug() in kernel.h */ 92 # endif 93 #endif 94 95 #include <linux/completion.h> 96 #include <linux/delay.h> 97 #include <linux/dma-mapping.h> 98 #include <linux/err.h> 99 #include <linux/init.h> 100 #include <linux/interrupt.h> 101 #include <linux/jiffies.h> 102 #include <linux/kernel.h> 103 #include <linux/module.h> 104 #include <linux/parport.h> 105 #include <linux/sched.h> 106 #include <linux/spinlock.h> 107 #include <linux/stddef.h> 108 #include <linux/types.h> 109 #include <asm/io.h> 110 #include <asm/ip32/ip32_ints.h> 111 #include <asm/ip32/mace.h> 112 113 /*--- Global variables -------------------------------------------------*/ 114 115 /* Verbose probing on by default for debugging. */ 116 #if DEBUG_PARPORT_IP32 >= 1 117 # define DEFAULT_VERBOSE_PROBING 1 118 #else 119 # define DEFAULT_VERBOSE_PROBING 0 120 #endif 121 122 /* Default prefix for printk */ 123 #define PPIP32 "parport_ip32: " 124 125 /* 126 * These are the module parameters: 127 * @features: bit mask of features to enable/disable 128 * (all enabled by default) 129 * @verbose_probing: log chit-chat during initialization 130 */ 131 #define PARPORT_IP32_ENABLE_IRQ (1U << 0) 132 #define PARPORT_IP32_ENABLE_DMA (1U << 1) 133 #define PARPORT_IP32_ENABLE_SPP (1U << 2) 134 #define PARPORT_IP32_ENABLE_EPP (1U << 3) 135 #define PARPORT_IP32_ENABLE_ECP (1U << 4) 136 static unsigned int features = ~0U; 137 static int verbose_probing = DEFAULT_VERBOSE_PROBING; 138 139 /* We do not support more than one port. */ 140 static struct parport *this_port = NULL; 141 142 /* Timing constants for FIFO modes. */ 143 #define FIFO_NFAULT_TIMEOUT 100 /* milliseconds */ 144 #define FIFO_POLLING_INTERVAL 50 /* microseconds */ 145 146 /*--- I/O register definitions -----------------------------------------*/ 147 148 /** 149 * struct parport_ip32_regs - virtual addresses of parallel port registers 150 * @data: Data Register 151 * @dsr: Device Status Register 152 * @dcr: Device Control Register 153 * @eppAddr: EPP Address Register 154 * @eppData0: EPP Data Register 0 155 * @eppData1: EPP Data Register 1 156 * @eppData2: EPP Data Register 2 157 * @eppData3: EPP Data Register 3 158 * @ecpAFifo: ECP Address FIFO 159 * @fifo: General FIFO register. The same address is used for: 160 * - cFifo, the Parallel Port DATA FIFO 161 * - ecpDFifo, the ECP Data FIFO 162 * - tFifo, the ECP Test FIFO 163 * @cnfgA: Configuration Register A 164 * @cnfgB: Configuration Register B 165 * @ecr: Extended Control Register 166 */ 167 struct parport_ip32_regs { 168 void __iomem *data; 169 void __iomem *dsr; 170 void __iomem *dcr; 171 void __iomem *eppAddr; 172 void __iomem *eppData0; 173 void __iomem *eppData1; 174 void __iomem *eppData2; 175 void __iomem *eppData3; 176 void __iomem *ecpAFifo; 177 void __iomem *fifo; 178 void __iomem *cnfgA; 179 void __iomem *cnfgB; 180 void __iomem *ecr; 181 }; 182 183 /* Device Status Register */ 184 #define DSR_nBUSY (1U << 7) /* PARPORT_STATUS_BUSY */ 185 #define DSR_nACK (1U << 6) /* PARPORT_STATUS_ACK */ 186 #define DSR_PERROR (1U << 5) /* PARPORT_STATUS_PAPEROUT */ 187 #define DSR_SELECT (1U << 4) /* PARPORT_STATUS_SELECT */ 188 #define DSR_nFAULT (1U << 3) /* PARPORT_STATUS_ERROR */ 189 #define DSR_nPRINT (1U << 2) /* specific to TL16PIR552 */ 190 /* #define DSR_reserved (1U << 1) */ 191 #define DSR_TIMEOUT (1U << 0) /* EPP timeout */ 192 193 /* Device Control Register */ 194 /* #define DCR_reserved (1U << 7) | (1U << 6) */ 195 #define DCR_DIR (1U << 5) /* direction */ 196 #define DCR_IRQ (1U << 4) /* interrupt on nAck */ 197 #define DCR_SELECT (1U << 3) /* PARPORT_CONTROL_SELECT */ 198 #define DCR_nINIT (1U << 2) /* PARPORT_CONTROL_INIT */ 199 #define DCR_AUTOFD (1U << 1) /* PARPORT_CONTROL_AUTOFD */ 200 #define DCR_STROBE (1U << 0) /* PARPORT_CONTROL_STROBE */ 201 202 /* ECP Configuration Register A */ 203 #define CNFGA_IRQ (1U << 7) 204 #define CNFGA_ID_MASK ((1U << 6) | (1U << 5) | (1U << 4)) 205 #define CNFGA_ID_SHIFT 4 206 #define CNFGA_ID_16 (00U << CNFGA_ID_SHIFT) 207 #define CNFGA_ID_8 (01U << CNFGA_ID_SHIFT) 208 #define CNFGA_ID_32 (02U << CNFGA_ID_SHIFT) 209 /* #define CNFGA_reserved (1U << 3) */ 210 #define CNFGA_nBYTEINTRANS (1U << 2) 211 #define CNFGA_PWORDLEFT ((1U << 1) | (1U << 0)) 212 213 /* ECP Configuration Register B */ 214 #define CNFGB_COMPRESS (1U << 7) 215 #define CNFGB_INTRVAL (1U << 6) 216 #define CNFGB_IRQ_MASK ((1U << 5) | (1U << 4) | (1U << 3)) 217 #define CNFGB_IRQ_SHIFT 3 218 #define CNFGB_DMA_MASK ((1U << 2) | (1U << 1) | (1U << 0)) 219 #define CNFGB_DMA_SHIFT 0 220 221 /* Extended Control Register */ 222 #define ECR_MODE_MASK ((1U << 7) | (1U << 6) | (1U << 5)) 223 #define ECR_MODE_SHIFT 5 224 #define ECR_MODE_SPP (00U << ECR_MODE_SHIFT) 225 #define ECR_MODE_PS2 (01U << ECR_MODE_SHIFT) 226 #define ECR_MODE_PPF (02U << ECR_MODE_SHIFT) 227 #define ECR_MODE_ECP (03U << ECR_MODE_SHIFT) 228 #define ECR_MODE_EPP (04U << ECR_MODE_SHIFT) 229 /* #define ECR_MODE_reserved (05U << ECR_MODE_SHIFT) */ 230 #define ECR_MODE_TST (06U << ECR_MODE_SHIFT) 231 #define ECR_MODE_CFG (07U << ECR_MODE_SHIFT) 232 #define ECR_nERRINTR (1U << 4) 233 #define ECR_DMAEN (1U << 3) 234 #define ECR_SERVINTR (1U << 2) 235 #define ECR_F_FULL (1U << 1) 236 #define ECR_F_EMPTY (1U << 0) 237 238 /*--- Private data -----------------------------------------------------*/ 239 240 /** 241 * enum parport_ip32_irq_mode - operation mode of interrupt handler 242 * @PARPORT_IP32_IRQ_FWD: forward interrupt to the upper parport layer 243 * @PARPORT_IP32_IRQ_HERE: interrupt is handled locally 244 */ 245 enum parport_ip32_irq_mode { PARPORT_IP32_IRQ_FWD, PARPORT_IP32_IRQ_HERE }; 246 247 /** 248 * struct parport_ip32_private - private stuff for &struct parport 249 * @regs: register addresses 250 * @dcr_cache: cached contents of DCR 251 * @dcr_writable: bit mask of writable DCR bits 252 * @pword: number of bytes per PWord 253 * @fifo_depth: number of PWords that FIFO will hold 254 * @readIntrThreshold: minimum number of PWords we can read 255 * if we get an interrupt 256 * @writeIntrThreshold: minimum number of PWords we can write 257 * if we get an interrupt 258 * @irq_mode: operation mode of interrupt handler for this port 259 * @irq_complete: mutex used to wait for an interrupt to occur 260 */ 261 struct parport_ip32_private { 262 struct parport_ip32_regs regs; 263 unsigned int dcr_cache; 264 unsigned int dcr_writable; 265 unsigned int pword; 266 unsigned int fifo_depth; 267 unsigned int readIntrThreshold; 268 unsigned int writeIntrThreshold; 269 enum parport_ip32_irq_mode irq_mode; 270 struct completion irq_complete; 271 }; 272 273 /*--- Debug code -------------------------------------------------------*/ 274 275 /* 276 * pr_debug1 - print debug messages 277 * 278 * This is like pr_debug(), but is defined for %DEBUG_PARPORT_IP32 >= 1 279 */ 280 #if DEBUG_PARPORT_IP32 >= 1 281 # define pr_debug1(...) printk(KERN_DEBUG __VA_ARGS__) 282 #else /* DEBUG_PARPORT_IP32 < 1 */ 283 # define pr_debug1(...) do { } while (0) 284 #endif 285 286 /* 287 * pr_trace, pr_trace1 - trace function calls 288 * @p: pointer to &struct parport 289 * @fmt: printk format string 290 * @...: parameters for format string 291 * 292 * Macros used to trace function calls. The given string is formatted after 293 * function name. pr_trace() uses pr_debug(), and pr_trace1() uses 294 * pr_debug1(). __pr_trace() is the low-level macro and is not to be used 295 * directly. 296 */ 297 #define __pr_trace(pr, p, fmt, ...) \ 298 pr("%s: %s" fmt "\n", \ 299 ({ const struct parport *__p = (p); \ 300 __p ? __p->name : "parport_ip32"; }), \ 301 __func__ , ##__VA_ARGS__) 302 #define pr_trace(p, fmt, ...) __pr_trace(pr_debug, p, fmt , ##__VA_ARGS__) 303 #define pr_trace1(p, fmt, ...) __pr_trace(pr_debug1, p, fmt , ##__VA_ARGS__) 304 305 /* 306 * __pr_probe, pr_probe - print message if @verbose_probing is true 307 * @p: pointer to &struct parport 308 * @fmt: printk format string 309 * @...: parameters for format string 310 * 311 * For new lines, use pr_probe(). Use __pr_probe() for continued lines. 312 */ 313 #define __pr_probe(...) \ 314 do { if (verbose_probing) printk(__VA_ARGS__); } while (0) 315 #define pr_probe(p, fmt, ...) \ 316 __pr_probe(KERN_INFO PPIP32 "0x%lx: " fmt, (p)->base , ##__VA_ARGS__) 317 318 /* 319 * parport_ip32_dump_state - print register status of parport 320 * @p: pointer to &struct parport 321 * @str: string to add in message 322 * @show_ecp_config: shall we dump ECP configuration registers too? 323 * 324 * This function is only here for debugging purpose, and should be used with 325 * care. Reading the parallel port registers may have undesired side effects. 326 * Especially if @show_ecp_config is true, the parallel port is resetted. 327 * This function is only defined if %DEBUG_PARPORT_IP32 >= 2. 328 */ 329 #if DEBUG_PARPORT_IP32 >= 2 330 static void parport_ip32_dump_state(struct parport *p, char *str, 331 unsigned int show_ecp_config) 332 { 333 struct parport_ip32_private * const priv = p->physport->private_data; 334 unsigned int i; 335 336 printk(KERN_DEBUG PPIP32 "%s: state (%s):\n", p->name, str); 337 { 338 static const char ecr_modes[8][4] = {"SPP", "PS2", "PPF", 339 "ECP", "EPP", "???", 340 "TST", "CFG"}; 341 unsigned int ecr = readb(priv->regs.ecr); 342 printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr); 343 printk(" %s", 344 ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); 345 if (ecr & ECR_nERRINTR) 346 printk(",nErrIntrEn"); 347 if (ecr & ECR_DMAEN) 348 printk(",dmaEn"); 349 if (ecr & ECR_SERVINTR) 350 printk(",serviceIntr"); 351 if (ecr & ECR_F_FULL) 352 printk(",f_full"); 353 if (ecr & ECR_F_EMPTY) 354 printk(",f_empty"); 355 printk("\n"); 356 } 357 if (show_ecp_config) { 358 unsigned int oecr, cnfgA, cnfgB; 359 oecr = readb(priv->regs.ecr); 360 writeb(ECR_MODE_PS2, priv->regs.ecr); 361 writeb(ECR_MODE_CFG, priv->regs.ecr); 362 cnfgA = readb(priv->regs.cnfgA); 363 cnfgB = readb(priv->regs.cnfgB); 364 writeb(ECR_MODE_PS2, priv->regs.ecr); 365 writeb(oecr, priv->regs.ecr); 366 printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA); 367 printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); 368 switch (cnfgA & CNFGA_ID_MASK) { 369 case CNFGA_ID_8: 370 printk(",8 bits"); 371 break; 372 case CNFGA_ID_16: 373 printk(",16 bits"); 374 break; 375 case CNFGA_ID_32: 376 printk(",32 bits"); 377 break; 378 default: 379 printk(",unknown ID"); 380 break; 381 } 382 if (!(cnfgA & CNFGA_nBYTEINTRANS)) 383 printk(",ByteInTrans"); 384 if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8) 385 printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT, 386 ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); 387 printk("\n"); 388 printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB); 389 printk(" irq=%u,dma=%u", 390 (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, 391 (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); 392 printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); 393 if (cnfgB & CNFGB_COMPRESS) 394 printk(",compress"); 395 printk("\n"); 396 } 397 for (i = 0; i < 2; i++) { 398 unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr); 399 printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x", 400 i ? "soft" : "hard", dcr); 401 printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); 402 if (dcr & DCR_IRQ) 403 printk(",ackIntEn"); 404 if (!(dcr & DCR_SELECT)) 405 printk(",nSelectIn"); 406 if (dcr & DCR_nINIT) 407 printk(",nInit"); 408 if (!(dcr & DCR_AUTOFD)) 409 printk(",nAutoFD"); 410 if (!(dcr & DCR_STROBE)) 411 printk(",nStrobe"); 412 printk("\n"); 413 } 414 #define sep (f++ ? ',' : ' ') 415 { 416 unsigned int f = 0; 417 unsigned int dsr = readb(priv->regs.dsr); 418 printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr); 419 if (!(dsr & DSR_nBUSY)) 420 printk("%cBusy", sep); 421 if (dsr & DSR_nACK) 422 printk("%cnAck", sep); 423 if (dsr & DSR_PERROR) 424 printk("%cPError", sep); 425 if (dsr & DSR_SELECT) 426 printk("%cSelect", sep); 427 if (dsr & DSR_nFAULT) 428 printk("%cnFault", sep); 429 if (!(dsr & DSR_nPRINT)) 430 printk("%c(Print)", sep); 431 if (dsr & DSR_TIMEOUT) 432 printk("%cTimeout", sep); 433 printk("\n"); 434 } 435 #undef sep 436 } 437 #else /* DEBUG_PARPORT_IP32 < 2 */ 438 #define parport_ip32_dump_state(...) do { } while (0) 439 #endif 440 441 /* 442 * CHECK_EXTRA_BITS - track and log extra bits 443 * @p: pointer to &struct parport 444 * @b: byte to inspect 445 * @m: bit mask of authorized bits 446 * 447 * This is used to track and log extra bits that should not be there in 448 * parport_ip32_write_control() and parport_ip32_frob_control(). It is only 449 * defined if %DEBUG_PARPORT_IP32 >= 1. 450 */ 451 #if DEBUG_PARPORT_IP32 >= 1 452 #define CHECK_EXTRA_BITS(p, b, m) \ 453 do { \ 454 unsigned int __b = (b), __m = (m); \ 455 if (__b & ~__m) \ 456 pr_debug1(PPIP32 "%s: extra bits in %s(%s): " \ 457 "0x%02x/0x%02x\n", \ 458 (p)->name, __func__, #b, __b, __m); \ 459 } while (0) 460 #else /* DEBUG_PARPORT_IP32 < 1 */ 461 #define CHECK_EXTRA_BITS(...) do { } while (0) 462 #endif 463 464 /*--- IP32 parallel port DMA operations --------------------------------*/ 465 466 /** 467 * struct parport_ip32_dma_data - private data needed for DMA operation 468 * @dir: DMA direction (from or to device) 469 * @buf: buffer physical address 470 * @len: buffer length 471 * @next: address of next bytes to DMA transfer 472 * @left: number of bytes remaining 473 * @ctx: next context to write (0: context_a; 1: context_b) 474 * @irq_on: are the DMA IRQs currently enabled? 475 * @lock: spinlock to protect access to the structure 476 */ 477 struct parport_ip32_dma_data { 478 enum dma_data_direction dir; 479 dma_addr_t buf; 480 dma_addr_t next; 481 size_t len; 482 size_t left; 483 unsigned int ctx; 484 unsigned int irq_on; 485 spinlock_t lock; 486 }; 487 static struct parport_ip32_dma_data parport_ip32_dma; 488 489 /** 490 * parport_ip32_dma_setup_context - setup next DMA context 491 * @limit: maximum data size for the context 492 * 493 * The alignment constraints must be verified in caller function, and the 494 * parameter @limit must be set accordingly. 495 */ 496 static void parport_ip32_dma_setup_context(unsigned int limit) 497 { 498 unsigned long flags; 499 500 spin_lock_irqsave(&parport_ip32_dma.lock, flags); 501 if (parport_ip32_dma.left > 0) { 502 /* Note: ctxreg is "volatile" here only because 503 * mace->perif.ctrl.parport.context_a and context_b are 504 * "volatile". */ 505 volatile u64 __iomem *ctxreg = (parport_ip32_dma.ctx == 0) ? 506 &mace->perif.ctrl.parport.context_a : 507 &mace->perif.ctrl.parport.context_b; 508 u64 count; 509 u64 ctxval; 510 if (parport_ip32_dma.left <= limit) { 511 count = parport_ip32_dma.left; 512 ctxval = MACEPAR_CONTEXT_LASTFLAG; 513 } else { 514 count = limit; 515 ctxval = 0; 516 } 517 518 pr_trace(NULL, 519 "(%u): 0x%04x:0x%04x, %u -> %u%s", 520 limit, 521 (unsigned int)parport_ip32_dma.buf, 522 (unsigned int)parport_ip32_dma.next, 523 (unsigned int)count, 524 parport_ip32_dma.ctx, ctxval ? "*" : ""); 525 526 ctxval |= parport_ip32_dma.next & 527 MACEPAR_CONTEXT_BASEADDR_MASK; 528 ctxval |= ((count - 1) << MACEPAR_CONTEXT_DATALEN_SHIFT) & 529 MACEPAR_CONTEXT_DATALEN_MASK; 530 writeq(ctxval, ctxreg); 531 parport_ip32_dma.next += count; 532 parport_ip32_dma.left -= count; 533 parport_ip32_dma.ctx ^= 1U; 534 } 535 /* If there is nothing more to send, disable IRQs to avoid to 536 * face an IRQ storm which can lock the machine. Disable them 537 * only once. */ 538 if (parport_ip32_dma.left == 0 && parport_ip32_dma.irq_on) { 539 pr_debug(PPIP32 "IRQ off (ctx)\n"); 540 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ); 541 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ); 542 parport_ip32_dma.irq_on = 0; 543 } 544 spin_unlock_irqrestore(&parport_ip32_dma.lock, flags); 545 } 546 547 /** 548 * parport_ip32_dma_interrupt - DMA interrupt handler 549 * @irq: interrupt number 550 * @dev_id: unused 551 */ 552 static irqreturn_t parport_ip32_dma_interrupt(int irq, void *dev_id) 553 { 554 if (parport_ip32_dma.left) 555 pr_trace(NULL, "(%d): ctx=%d", irq, parport_ip32_dma.ctx); 556 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND); 557 return IRQ_HANDLED; 558 } 559 560 #if DEBUG_PARPORT_IP32 561 static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id) 562 { 563 pr_trace1(NULL, "(%d)", irq); 564 return IRQ_HANDLED; 565 } 566 #endif 567 568 /** 569 * parport_ip32_dma_start - begins a DMA transfer 570 * @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE 571 * @addr: pointer to data buffer 572 * @count: buffer size 573 * 574 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 575 * correctly balanced. 576 */ 577 static int parport_ip32_dma_start(enum dma_data_direction dir, 578 void *addr, size_t count) 579 { 580 unsigned int limit; 581 u64 ctrl; 582 583 pr_trace(NULL, "(%d, %lu)", dir, (unsigned long)count); 584 585 /* FIXME - add support for DMA_FROM_DEVICE. In this case, buffer must 586 * be 64 bytes aligned. */ 587 BUG_ON(dir != DMA_TO_DEVICE); 588 589 /* Reset DMA controller */ 590 ctrl = MACEPAR_CTLSTAT_RESET; 591 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 592 593 /* DMA IRQs should normally be enabled */ 594 if (!parport_ip32_dma.irq_on) { 595 WARN_ON(1); 596 enable_irq(MACEISA_PAR_CTXA_IRQ); 597 enable_irq(MACEISA_PAR_CTXB_IRQ); 598 parport_ip32_dma.irq_on = 1; 599 } 600 601 /* Prepare DMA pointers */ 602 parport_ip32_dma.dir = dir; 603 parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir); 604 parport_ip32_dma.len = count; 605 parport_ip32_dma.next = parport_ip32_dma.buf; 606 parport_ip32_dma.left = parport_ip32_dma.len; 607 parport_ip32_dma.ctx = 0; 608 609 /* Setup DMA direction and first two contexts */ 610 ctrl = (dir == DMA_TO_DEVICE) ? 0 : MACEPAR_CTLSTAT_DIRECTION; 611 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 612 /* Single transfer should not cross a 4K page boundary */ 613 limit = MACEPAR_CONTEXT_DATA_BOUND - 614 (parport_ip32_dma.next & (MACEPAR_CONTEXT_DATA_BOUND - 1)); 615 parport_ip32_dma_setup_context(limit); 616 parport_ip32_dma_setup_context(MACEPAR_CONTEXT_DATA_BOUND); 617 618 /* Real start of DMA transfer */ 619 ctrl |= MACEPAR_CTLSTAT_ENABLE; 620 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 621 622 return 0; 623 } 624 625 /** 626 * parport_ip32_dma_stop - ends a running DMA transfer 627 * 628 * Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be 629 * correctly balanced. 630 */ 631 static void parport_ip32_dma_stop(void) 632 { 633 u64 ctx_a; 634 u64 ctx_b; 635 u64 ctrl; 636 u64 diag; 637 size_t res[2]; /* {[0] = res_a, [1] = res_b} */ 638 639 pr_trace(NULL, "()"); 640 641 /* Disable IRQs */ 642 spin_lock_irq(&parport_ip32_dma.lock); 643 if (parport_ip32_dma.irq_on) { 644 pr_debug(PPIP32 "IRQ off (stop)\n"); 645 disable_irq_nosync(MACEISA_PAR_CTXA_IRQ); 646 disable_irq_nosync(MACEISA_PAR_CTXB_IRQ); 647 parport_ip32_dma.irq_on = 0; 648 } 649 spin_unlock_irq(&parport_ip32_dma.lock); 650 /* Force IRQ synchronization, even if the IRQs were disabled 651 * elsewhere. */ 652 synchronize_irq(MACEISA_PAR_CTXA_IRQ); 653 synchronize_irq(MACEISA_PAR_CTXB_IRQ); 654 655 /* Stop DMA transfer */ 656 ctrl = readq(&mace->perif.ctrl.parport.cntlstat); 657 ctrl &= ~MACEPAR_CTLSTAT_ENABLE; 658 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 659 660 /* Adjust residue (parport_ip32_dma.left) */ 661 ctx_a = readq(&mace->perif.ctrl.parport.context_a); 662 ctx_b = readq(&mace->perif.ctrl.parport.context_b); 663 ctrl = readq(&mace->perif.ctrl.parport.cntlstat); 664 diag = readq(&mace->perif.ctrl.parport.diagnostic); 665 res[0] = (ctrl & MACEPAR_CTLSTAT_CTXA_VALID) ? 666 1 + ((ctx_a & MACEPAR_CONTEXT_DATALEN_MASK) >> 667 MACEPAR_CONTEXT_DATALEN_SHIFT) : 668 0; 669 res[1] = (ctrl & MACEPAR_CTLSTAT_CTXB_VALID) ? 670 1 + ((ctx_b & MACEPAR_CONTEXT_DATALEN_MASK) >> 671 MACEPAR_CONTEXT_DATALEN_SHIFT) : 672 0; 673 if (diag & MACEPAR_DIAG_DMACTIVE) 674 res[(diag & MACEPAR_DIAG_CTXINUSE) != 0] = 675 1 + ((diag & MACEPAR_DIAG_CTRMASK) >> 676 MACEPAR_DIAG_CTRSHIFT); 677 parport_ip32_dma.left += res[0] + res[1]; 678 679 /* Reset DMA controller, and re-enable IRQs */ 680 ctrl = MACEPAR_CTLSTAT_RESET; 681 writeq(ctrl, &mace->perif.ctrl.parport.cntlstat); 682 pr_debug(PPIP32 "IRQ on (stop)\n"); 683 enable_irq(MACEISA_PAR_CTXA_IRQ); 684 enable_irq(MACEISA_PAR_CTXB_IRQ); 685 parport_ip32_dma.irq_on = 1; 686 687 dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len, 688 parport_ip32_dma.dir); 689 } 690 691 /** 692 * parport_ip32_dma_get_residue - get residue from last DMA transfer 693 * 694 * Returns the number of bytes remaining from last DMA transfer. 695 */ 696 static inline size_t parport_ip32_dma_get_residue(void) 697 { 698 return parport_ip32_dma.left; 699 } 700 701 /** 702 * parport_ip32_dma_register - initialize DMA engine 703 * 704 * Returns zero for success. 705 */ 706 static int parport_ip32_dma_register(void) 707 { 708 int err; 709 710 spin_lock_init(&parport_ip32_dma.lock); 711 parport_ip32_dma.irq_on = 1; 712 713 /* Reset DMA controller */ 714 writeq(MACEPAR_CTLSTAT_RESET, &mace->perif.ctrl.parport.cntlstat); 715 716 /* Request IRQs */ 717 err = request_irq(MACEISA_PAR_CTXA_IRQ, parport_ip32_dma_interrupt, 718 0, "parport_ip32", NULL); 719 if (err) 720 goto fail_a; 721 err = request_irq(MACEISA_PAR_CTXB_IRQ, parport_ip32_dma_interrupt, 722 0, "parport_ip32", NULL); 723 if (err) 724 goto fail_b; 725 #if DEBUG_PARPORT_IP32 726 /* FIXME - what is this IRQ for? */ 727 err = request_irq(MACEISA_PAR_MERR_IRQ, parport_ip32_merr_interrupt, 728 0, "parport_ip32", NULL); 729 if (err) 730 goto fail_merr; 731 #endif 732 return 0; 733 734 #if DEBUG_PARPORT_IP32 735 fail_merr: 736 free_irq(MACEISA_PAR_CTXB_IRQ, NULL); 737 #endif 738 fail_b: 739 free_irq(MACEISA_PAR_CTXA_IRQ, NULL); 740 fail_a: 741 return err; 742 } 743 744 /** 745 * parport_ip32_dma_unregister - release and free resources for DMA engine 746 */ 747 static void parport_ip32_dma_unregister(void) 748 { 749 #if DEBUG_PARPORT_IP32 750 free_irq(MACEISA_PAR_MERR_IRQ, NULL); 751 #endif 752 free_irq(MACEISA_PAR_CTXB_IRQ, NULL); 753 free_irq(MACEISA_PAR_CTXA_IRQ, NULL); 754 } 755 756 /*--- Interrupt handlers and associates --------------------------------*/ 757 758 /** 759 * parport_ip32_wakeup - wakes up code waiting for an interrupt 760 * @p: pointer to &struct parport 761 */ 762 static inline void parport_ip32_wakeup(struct parport *p) 763 { 764 struct parport_ip32_private * const priv = p->physport->private_data; 765 complete(&priv->irq_complete); 766 } 767 768 /** 769 * parport_ip32_interrupt - interrupt handler 770 * @irq: interrupt number 771 * @dev_id: pointer to &struct parport 772 * 773 * Caught interrupts are forwarded to the upper parport layer if IRQ_mode is 774 * %PARPORT_IP32_IRQ_FWD. 775 */ 776 static irqreturn_t parport_ip32_interrupt(int irq, void *dev_id) 777 { 778 struct parport * const p = dev_id; 779 struct parport_ip32_private * const priv = p->physport->private_data; 780 enum parport_ip32_irq_mode irq_mode = priv->irq_mode; 781 782 switch (irq_mode) { 783 case PARPORT_IP32_IRQ_FWD: 784 return parport_irq_handler(irq, dev_id); 785 786 case PARPORT_IP32_IRQ_HERE: 787 parport_ip32_wakeup(p); 788 break; 789 } 790 791 return IRQ_HANDLED; 792 } 793 794 /*--- Some utility function to manipulate ECR register -----------------*/ 795 796 /** 797 * parport_ip32_read_econtrol - read contents of the ECR register 798 * @p: pointer to &struct parport 799 */ 800 static inline unsigned int parport_ip32_read_econtrol(struct parport *p) 801 { 802 struct parport_ip32_private * const priv = p->physport->private_data; 803 return readb(priv->regs.ecr); 804 } 805 806 /** 807 * parport_ip32_write_econtrol - write new contents to the ECR register 808 * @p: pointer to &struct parport 809 * @c: new value to write 810 */ 811 static inline void parport_ip32_write_econtrol(struct parport *p, 812 unsigned int c) 813 { 814 struct parport_ip32_private * const priv = p->physport->private_data; 815 writeb(c, priv->regs.ecr); 816 } 817 818 /** 819 * parport_ip32_frob_econtrol - change bits from the ECR register 820 * @p: pointer to &struct parport 821 * @mask: bit mask of bits to change 822 * @val: new value for changed bits 823 * 824 * Read from the ECR, mask out the bits in @mask, exclusive-or with the bits 825 * in @val, and write the result to the ECR. 826 */ 827 static inline void parport_ip32_frob_econtrol(struct parport *p, 828 unsigned int mask, 829 unsigned int val) 830 { 831 unsigned int c; 832 c = (parport_ip32_read_econtrol(p) & ~mask) ^ val; 833 parport_ip32_write_econtrol(p, c); 834 } 835 836 /** 837 * parport_ip32_set_mode - change mode of ECP port 838 * @p: pointer to &struct parport 839 * @mode: new mode to write in ECR 840 * 841 * ECR is reset in a sane state (interrupts and DMA disabled), and placed in 842 * mode @mode. Go through PS2 mode if needed. 843 */ 844 static void parport_ip32_set_mode(struct parport *p, unsigned int mode) 845 { 846 unsigned int omode; 847 848 mode &= ECR_MODE_MASK; 849 omode = parport_ip32_read_econtrol(p) & ECR_MODE_MASK; 850 851 if (!(mode == ECR_MODE_SPP || mode == ECR_MODE_PS2 852 || omode == ECR_MODE_SPP || omode == ECR_MODE_PS2)) { 853 /* We have to go through PS2 mode */ 854 unsigned int ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 855 parport_ip32_write_econtrol(p, ecr); 856 } 857 parport_ip32_write_econtrol(p, mode | ECR_nERRINTR | ECR_SERVINTR); 858 } 859 860 /*--- Basic functions needed for parport -------------------------------*/ 861 862 /** 863 * parport_ip32_read_data - return current contents of the DATA register 864 * @p: pointer to &struct parport 865 */ 866 static inline unsigned char parport_ip32_read_data(struct parport *p) 867 { 868 struct parport_ip32_private * const priv = p->physport->private_data; 869 return readb(priv->regs.data); 870 } 871 872 /** 873 * parport_ip32_write_data - set new contents for the DATA register 874 * @p: pointer to &struct parport 875 * @d: new value to write 876 */ 877 static inline void parport_ip32_write_data(struct parport *p, unsigned char d) 878 { 879 struct parport_ip32_private * const priv = p->physport->private_data; 880 writeb(d, priv->regs.data); 881 } 882 883 /** 884 * parport_ip32_read_status - return current contents of the DSR register 885 * @p: pointer to &struct parport 886 */ 887 static inline unsigned char parport_ip32_read_status(struct parport *p) 888 { 889 struct parport_ip32_private * const priv = p->physport->private_data; 890 return readb(priv->regs.dsr); 891 } 892 893 /** 894 * __parport_ip32_read_control - return cached contents of the DCR register 895 * @p: pointer to &struct parport 896 */ 897 static inline unsigned int __parport_ip32_read_control(struct parport *p) 898 { 899 struct parport_ip32_private * const priv = p->physport->private_data; 900 return priv->dcr_cache; /* use soft copy */ 901 } 902 903 /** 904 * __parport_ip32_write_control - set new contents for the DCR register 905 * @p: pointer to &struct parport 906 * @c: new value to write 907 */ 908 static inline void __parport_ip32_write_control(struct parport *p, 909 unsigned int c) 910 { 911 struct parport_ip32_private * const priv = p->physport->private_data; 912 CHECK_EXTRA_BITS(p, c, priv->dcr_writable); 913 c &= priv->dcr_writable; /* only writable bits */ 914 writeb(c, priv->regs.dcr); 915 priv->dcr_cache = c; /* update soft copy */ 916 } 917 918 /** 919 * __parport_ip32_frob_control - change bits from the DCR register 920 * @p: pointer to &struct parport 921 * @mask: bit mask of bits to change 922 * @val: new value for changed bits 923 * 924 * This is equivalent to read from the DCR, mask out the bits in @mask, 925 * exclusive-or with the bits in @val, and write the result to the DCR. 926 * Actually, the cached contents of the DCR is used. 927 */ 928 static inline void __parport_ip32_frob_control(struct parport *p, 929 unsigned int mask, 930 unsigned int val) 931 { 932 unsigned int c; 933 c = (__parport_ip32_read_control(p) & ~mask) ^ val; 934 __parport_ip32_write_control(p, c); 935 } 936 937 /** 938 * parport_ip32_read_control - return cached contents of the DCR register 939 * @p: pointer to &struct parport 940 * 941 * The return value is masked so as to only return the value of %DCR_STROBE, 942 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 943 */ 944 static inline unsigned char parport_ip32_read_control(struct parport *p) 945 { 946 const unsigned int rm = 947 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 948 return __parport_ip32_read_control(p) & rm; 949 } 950 951 /** 952 * parport_ip32_write_control - set new contents for the DCR register 953 * @p: pointer to &struct parport 954 * @c: new value to write 955 * 956 * The value is masked so as to only change the value of %DCR_STROBE, 957 * %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 958 */ 959 static inline void parport_ip32_write_control(struct parport *p, 960 unsigned char c) 961 { 962 const unsigned int wm = 963 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 964 CHECK_EXTRA_BITS(p, c, wm); 965 __parport_ip32_frob_control(p, wm, c & wm); 966 } 967 968 /** 969 * parport_ip32_frob_control - change bits from the DCR register 970 * @p: pointer to &struct parport 971 * @mask: bit mask of bits to change 972 * @val: new value for changed bits 973 * 974 * This differs from __parport_ip32_frob_control() in that it only allows to 975 * change the value of %DCR_STROBE, %DCR_AUTOFD, %DCR_nINIT, and %DCR_SELECT. 976 */ 977 static inline unsigned char parport_ip32_frob_control(struct parport *p, 978 unsigned char mask, 979 unsigned char val) 980 { 981 const unsigned int wm = 982 DCR_STROBE | DCR_AUTOFD | DCR_nINIT | DCR_SELECT; 983 CHECK_EXTRA_BITS(p, mask, wm); 984 CHECK_EXTRA_BITS(p, val, wm); 985 __parport_ip32_frob_control(p, mask & wm, val & wm); 986 return parport_ip32_read_control(p); 987 } 988 989 /** 990 * parport_ip32_disable_irq - disable interrupts on the rising edge of nACK 991 * @p: pointer to &struct parport 992 */ 993 static inline void parport_ip32_disable_irq(struct parport *p) 994 { 995 __parport_ip32_frob_control(p, DCR_IRQ, 0); 996 } 997 998 /** 999 * parport_ip32_enable_irq - enable interrupts on the rising edge of nACK 1000 * @p: pointer to &struct parport 1001 */ 1002 static inline void parport_ip32_enable_irq(struct parport *p) 1003 { 1004 __parport_ip32_frob_control(p, DCR_IRQ, DCR_IRQ); 1005 } 1006 1007 /** 1008 * parport_ip32_data_forward - enable host-to-peripheral communications 1009 * @p: pointer to &struct parport 1010 * 1011 * Enable the data line drivers, for 8-bit host-to-peripheral communications. 1012 */ 1013 static inline void parport_ip32_data_forward(struct parport *p) 1014 { 1015 __parport_ip32_frob_control(p, DCR_DIR, 0); 1016 } 1017 1018 /** 1019 * parport_ip32_data_reverse - enable peripheral-to-host communications 1020 * @p: pointer to &struct parport 1021 * 1022 * Place the data bus in a high impedance state, if @p->modes has the 1023 * PARPORT_MODE_TRISTATE bit set. 1024 */ 1025 static inline void parport_ip32_data_reverse(struct parport *p) 1026 { 1027 __parport_ip32_frob_control(p, DCR_DIR, DCR_DIR); 1028 } 1029 1030 /** 1031 * parport_ip32_init_state - for core parport code 1032 * @dev: pointer to &struct pardevice 1033 * @s: pointer to &struct parport_state to initialize 1034 */ 1035 static void parport_ip32_init_state(struct pardevice *dev, 1036 struct parport_state *s) 1037 { 1038 s->u.ip32.dcr = DCR_SELECT | DCR_nINIT; 1039 s->u.ip32.ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 1040 } 1041 1042 /** 1043 * parport_ip32_save_state - for core parport code 1044 * @p: pointer to &struct parport 1045 * @s: pointer to &struct parport_state to save state to 1046 */ 1047 static void parport_ip32_save_state(struct parport *p, 1048 struct parport_state *s) 1049 { 1050 s->u.ip32.dcr = __parport_ip32_read_control(p); 1051 s->u.ip32.ecr = parport_ip32_read_econtrol(p); 1052 } 1053 1054 /** 1055 * parport_ip32_restore_state - for core parport code 1056 * @p: pointer to &struct parport 1057 * @s: pointer to &struct parport_state to restore state from 1058 */ 1059 static void parport_ip32_restore_state(struct parport *p, 1060 struct parport_state *s) 1061 { 1062 parport_ip32_set_mode(p, s->u.ip32.ecr & ECR_MODE_MASK); 1063 parport_ip32_write_econtrol(p, s->u.ip32.ecr); 1064 __parport_ip32_write_control(p, s->u.ip32.dcr); 1065 } 1066 1067 /*--- EPP mode functions -----------------------------------------------*/ 1068 1069 /** 1070 * parport_ip32_clear_epp_timeout - clear Timeout bit in EPP mode 1071 * @p: pointer to &struct parport 1072 * 1073 * Returns 1 if the Timeout bit is clear, and 0 otherwise. 1074 */ 1075 static unsigned int parport_ip32_clear_epp_timeout(struct parport *p) 1076 { 1077 struct parport_ip32_private * const priv = p->physport->private_data; 1078 unsigned int cleared; 1079 1080 if (!(parport_ip32_read_status(p) & DSR_TIMEOUT)) 1081 cleared = 1; 1082 else { 1083 unsigned int r; 1084 /* To clear timeout some chips require double read */ 1085 parport_ip32_read_status(p); 1086 r = parport_ip32_read_status(p); 1087 /* Some reset by writing 1 */ 1088 writeb(r | DSR_TIMEOUT, priv->regs.dsr); 1089 /* Others by writing 0 */ 1090 writeb(r & ~DSR_TIMEOUT, priv->regs.dsr); 1091 1092 r = parport_ip32_read_status(p); 1093 cleared = !(r & DSR_TIMEOUT); 1094 } 1095 1096 pr_trace(p, "(): %s", cleared ? "cleared" : "failed"); 1097 return cleared; 1098 } 1099 1100 /** 1101 * parport_ip32_epp_read - generic EPP read function 1102 * @eppreg: I/O register to read from 1103 * @p: pointer to &struct parport 1104 * @buf: buffer to store read data 1105 * @len: length of buffer @buf 1106 * @flags: may be PARPORT_EPP_FAST 1107 */ 1108 static size_t parport_ip32_epp_read(void __iomem *eppreg, 1109 struct parport *p, void *buf, 1110 size_t len, int flags) 1111 { 1112 struct parport_ip32_private * const priv = p->physport->private_data; 1113 size_t got; 1114 parport_ip32_set_mode(p, ECR_MODE_EPP); 1115 parport_ip32_data_reverse(p); 1116 parport_ip32_write_control(p, DCR_nINIT); 1117 if ((flags & PARPORT_EPP_FAST) && (len > 1)) { 1118 readsb(eppreg, buf, len); 1119 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1120 parport_ip32_clear_epp_timeout(p); 1121 return -EIO; 1122 } 1123 got = len; 1124 } else { 1125 u8 *bufp = buf; 1126 for (got = 0; got < len; got++) { 1127 *bufp++ = readb(eppreg); 1128 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1129 parport_ip32_clear_epp_timeout(p); 1130 break; 1131 } 1132 } 1133 } 1134 parport_ip32_data_forward(p); 1135 parport_ip32_set_mode(p, ECR_MODE_PS2); 1136 return got; 1137 } 1138 1139 /** 1140 * parport_ip32_epp_write - generic EPP write function 1141 * @eppreg: I/O register to write to 1142 * @p: pointer to &struct parport 1143 * @buf: buffer of data to write 1144 * @len: length of buffer @buf 1145 * @flags: may be PARPORT_EPP_FAST 1146 */ 1147 static size_t parport_ip32_epp_write(void __iomem *eppreg, 1148 struct parport *p, const void *buf, 1149 size_t len, int flags) 1150 { 1151 struct parport_ip32_private * const priv = p->physport->private_data; 1152 size_t written; 1153 parport_ip32_set_mode(p, ECR_MODE_EPP); 1154 parport_ip32_data_forward(p); 1155 parport_ip32_write_control(p, DCR_nINIT); 1156 if ((flags & PARPORT_EPP_FAST) && (len > 1)) { 1157 writesb(eppreg, buf, len); 1158 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1159 parport_ip32_clear_epp_timeout(p); 1160 return -EIO; 1161 } 1162 written = len; 1163 } else { 1164 const u8 *bufp = buf; 1165 for (written = 0; written < len; written++) { 1166 writeb(*bufp++, eppreg); 1167 if (readb(priv->regs.dsr) & DSR_TIMEOUT) { 1168 parport_ip32_clear_epp_timeout(p); 1169 break; 1170 } 1171 } 1172 } 1173 parport_ip32_set_mode(p, ECR_MODE_PS2); 1174 return written; 1175 } 1176 1177 /** 1178 * parport_ip32_epp_read_data - read a block of data in EPP mode 1179 * @p: pointer to &struct parport 1180 * @buf: buffer to store read data 1181 * @len: length of buffer @buf 1182 * @flags: may be PARPORT_EPP_FAST 1183 */ 1184 static size_t parport_ip32_epp_read_data(struct parport *p, void *buf, 1185 size_t len, int flags) 1186 { 1187 struct parport_ip32_private * const priv = p->physport->private_data; 1188 return parport_ip32_epp_read(priv->regs.eppData0, p, buf, len, flags); 1189 } 1190 1191 /** 1192 * parport_ip32_epp_write_data - write a block of data in EPP mode 1193 * @p: pointer to &struct parport 1194 * @buf: buffer of data to write 1195 * @len: length of buffer @buf 1196 * @flags: may be PARPORT_EPP_FAST 1197 */ 1198 static size_t parport_ip32_epp_write_data(struct parport *p, const void *buf, 1199 size_t len, int flags) 1200 { 1201 struct parport_ip32_private * const priv = p->physport->private_data; 1202 return parport_ip32_epp_write(priv->regs.eppData0, p, buf, len, flags); 1203 } 1204 1205 /** 1206 * parport_ip32_epp_read_addr - read a block of addresses in EPP mode 1207 * @p: pointer to &struct parport 1208 * @buf: buffer to store read data 1209 * @len: length of buffer @buf 1210 * @flags: may be PARPORT_EPP_FAST 1211 */ 1212 static size_t parport_ip32_epp_read_addr(struct parport *p, void *buf, 1213 size_t len, int flags) 1214 { 1215 struct parport_ip32_private * const priv = p->physport->private_data; 1216 return parport_ip32_epp_read(priv->regs.eppAddr, p, buf, len, flags); 1217 } 1218 1219 /** 1220 * parport_ip32_epp_write_addr - write a block of addresses in EPP mode 1221 * @p: pointer to &struct parport 1222 * @buf: buffer of data to write 1223 * @len: length of buffer @buf 1224 * @flags: may be PARPORT_EPP_FAST 1225 */ 1226 static size_t parport_ip32_epp_write_addr(struct parport *p, const void *buf, 1227 size_t len, int flags) 1228 { 1229 struct parport_ip32_private * const priv = p->physport->private_data; 1230 return parport_ip32_epp_write(priv->regs.eppAddr, p, buf, len, flags); 1231 } 1232 1233 /*--- ECP mode functions (FIFO) ----------------------------------------*/ 1234 1235 /** 1236 * parport_ip32_fifo_wait_break - check if the waiting function should return 1237 * @p: pointer to &struct parport 1238 * @expire: timeout expiring date, in jiffies 1239 * 1240 * parport_ip32_fifo_wait_break() checks if the waiting function should return 1241 * immediately or not. The break conditions are: 1242 * - expired timeout; 1243 * - a pending signal; 1244 * - nFault asserted low. 1245 * This function also calls cond_resched(). 1246 */ 1247 static unsigned int parport_ip32_fifo_wait_break(struct parport *p, 1248 unsigned long expire) 1249 { 1250 cond_resched(); 1251 if (time_after(jiffies, expire)) { 1252 pr_debug1(PPIP32 "%s: FIFO write timed out\n", p->name); 1253 return 1; 1254 } 1255 if (signal_pending(current)) { 1256 pr_debug1(PPIP32 "%s: Signal pending\n", p->name); 1257 return 1; 1258 } 1259 if (!(parport_ip32_read_status(p) & DSR_nFAULT)) { 1260 pr_debug1(PPIP32 "%s: nFault asserted low\n", p->name); 1261 return 1; 1262 } 1263 return 0; 1264 } 1265 1266 /** 1267 * parport_ip32_fwp_wait_polling - wait for FIFO to empty (polling) 1268 * @p: pointer to &struct parport 1269 * 1270 * Returns the number of bytes that can safely be written in the FIFO. A 1271 * return value of zero means that the calling function should terminate as 1272 * fast as possible. 1273 */ 1274 static unsigned int parport_ip32_fwp_wait_polling(struct parport *p) 1275 { 1276 struct parport_ip32_private * const priv = p->physport->private_data; 1277 struct parport * const physport = p->physport; 1278 unsigned long expire; 1279 unsigned int count; 1280 unsigned int ecr; 1281 1282 expire = jiffies + physport->cad->timeout; 1283 count = 0; 1284 while (1) { 1285 if (parport_ip32_fifo_wait_break(p, expire)) 1286 break; 1287 1288 /* Check FIFO state. We do nothing when the FIFO is nor full, 1289 * nor empty. It appears that the FIFO full bit is not always 1290 * reliable, the FIFO state is sometimes wrongly reported, and 1291 * the chip gets confused if we give it another byte. */ 1292 ecr = parport_ip32_read_econtrol(p); 1293 if (ecr & ECR_F_EMPTY) { 1294 /* FIFO is empty, fill it up */ 1295 count = priv->fifo_depth; 1296 break; 1297 } 1298 1299 /* Wait a moment... */ 1300 udelay(FIFO_POLLING_INTERVAL); 1301 } /* while (1) */ 1302 1303 return count; 1304 } 1305 1306 /** 1307 * parport_ip32_fwp_wait_interrupt - wait for FIFO to empty (interrupt-driven) 1308 * @p: pointer to &struct parport 1309 * 1310 * Returns the number of bytes that can safely be written in the FIFO. A 1311 * return value of zero means that the calling function should terminate as 1312 * fast as possible. 1313 */ 1314 static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p) 1315 { 1316 static unsigned int lost_interrupt = 0; 1317 struct parport_ip32_private * const priv = p->physport->private_data; 1318 struct parport * const physport = p->physport; 1319 unsigned long nfault_timeout; 1320 unsigned long expire; 1321 unsigned int count; 1322 unsigned int ecr; 1323 1324 nfault_timeout = min((unsigned long)physport->cad->timeout, 1325 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT)); 1326 expire = jiffies + physport->cad->timeout; 1327 count = 0; 1328 while (1) { 1329 if (parport_ip32_fifo_wait_break(p, expire)) 1330 break; 1331 1332 /* Initialize mutex used to take interrupts into account */ 1333 INIT_COMPLETION(priv->irq_complete); 1334 1335 /* Enable serviceIntr */ 1336 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1337 1338 /* Enabling serviceIntr while the FIFO is empty does not 1339 * always generate an interrupt, so check for emptiness 1340 * now. */ 1341 ecr = parport_ip32_read_econtrol(p); 1342 if (!(ecr & ECR_F_EMPTY)) { 1343 /* FIFO is not empty: wait for an interrupt or a 1344 * timeout to occur */ 1345 wait_for_completion_interruptible_timeout( 1346 &priv->irq_complete, nfault_timeout); 1347 ecr = parport_ip32_read_econtrol(p); 1348 if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR) 1349 && !lost_interrupt) { 1350 printk(KERN_WARNING PPIP32 1351 "%s: lost interrupt in %s\n", 1352 p->name, __func__); 1353 lost_interrupt = 1; 1354 } 1355 } 1356 1357 /* Disable serviceIntr */ 1358 parport_ip32_frob_econtrol(p, ECR_SERVINTR, ECR_SERVINTR); 1359 1360 /* Check FIFO state */ 1361 if (ecr & ECR_F_EMPTY) { 1362 /* FIFO is empty, fill it up */ 1363 count = priv->fifo_depth; 1364 break; 1365 } else if (ecr & ECR_SERVINTR) { 1366 /* FIFO is not empty, but we know that can safely push 1367 * writeIntrThreshold bytes into it */ 1368 count = priv->writeIntrThreshold; 1369 break; 1370 } 1371 /* FIFO is not empty, and we did not get any interrupt. 1372 * Either it's time to check for nFault, or a signal is 1373 * pending. This is verified in 1374 * parport_ip32_fifo_wait_break(), so we continue the loop. */ 1375 } /* while (1) */ 1376 1377 return count; 1378 } 1379 1380 /** 1381 * parport_ip32_fifo_write_block_pio - write a block of data (PIO mode) 1382 * @p: pointer to &struct parport 1383 * @buf: buffer of data to write 1384 * @len: length of buffer @buf 1385 * 1386 * Uses PIO to write the contents of the buffer @buf into the parallel port 1387 * FIFO. Returns the number of bytes that were actually written. It can work 1388 * with or without the help of interrupts. The parallel port must be 1389 * correctly initialized before calling parport_ip32_fifo_write_block_pio(). 1390 */ 1391 static size_t parport_ip32_fifo_write_block_pio(struct parport *p, 1392 const void *buf, size_t len) 1393 { 1394 struct parport_ip32_private * const priv = p->physport->private_data; 1395 const u8 *bufp = buf; 1396 size_t left = len; 1397 1398 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1399 1400 while (left > 0) { 1401 unsigned int count; 1402 1403 count = (p->irq == PARPORT_IRQ_NONE) ? 1404 parport_ip32_fwp_wait_polling(p) : 1405 parport_ip32_fwp_wait_interrupt(p); 1406 if (count == 0) 1407 break; /* Transmission should be stopped */ 1408 if (count > left) 1409 count = left; 1410 if (count == 1) { 1411 writeb(*bufp, priv->regs.fifo); 1412 bufp++, left--; 1413 } else { 1414 writesb(priv->regs.fifo, bufp, count); 1415 bufp += count, left -= count; 1416 } 1417 } 1418 1419 priv->irq_mode = PARPORT_IP32_IRQ_FWD; 1420 1421 return len - left; 1422 } 1423 1424 /** 1425 * parport_ip32_fifo_write_block_dma - write a block of data (DMA mode) 1426 * @p: pointer to &struct parport 1427 * @buf: buffer of data to write 1428 * @len: length of buffer @buf 1429 * 1430 * Uses DMA to write the contents of the buffer @buf into the parallel port 1431 * FIFO. Returns the number of bytes that were actually written. The 1432 * parallel port must be correctly initialized before calling 1433 * parport_ip32_fifo_write_block_dma(). 1434 */ 1435 static size_t parport_ip32_fifo_write_block_dma(struct parport *p, 1436 const void *buf, size_t len) 1437 { 1438 struct parport_ip32_private * const priv = p->physport->private_data; 1439 struct parport * const physport = p->physport; 1440 unsigned long nfault_timeout; 1441 unsigned long expire; 1442 size_t written; 1443 unsigned int ecr; 1444 1445 priv->irq_mode = PARPORT_IP32_IRQ_HERE; 1446 1447 parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len); 1448 INIT_COMPLETION(priv->irq_complete); 1449 parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN); 1450 1451 nfault_timeout = min((unsigned long)physport->cad->timeout, 1452 msecs_to_jiffies(FIFO_NFAULT_TIMEOUT)); 1453 expire = jiffies + physport->cad->timeout; 1454 while (1) { 1455 if (parport_ip32_fifo_wait_break(p, expire)) 1456 break; 1457 wait_for_completion_interruptible_timeout(&priv->irq_complete, 1458 nfault_timeout); 1459 ecr = parport_ip32_read_econtrol(p); 1460 if (ecr & ECR_SERVINTR) 1461 break; /* DMA transfer just finished */ 1462 } 1463 parport_ip32_dma_stop(); 1464 written = len - parport_ip32_dma_get_residue(); 1465 1466 priv->irq_mode = PARPORT_IP32_IRQ_FWD; 1467 1468 return written; 1469 } 1470 1471 /** 1472 * parport_ip32_fifo_write_block - write a block of data 1473 * @p: pointer to &struct parport 1474 * @buf: buffer of data to write 1475 * @len: length of buffer @buf 1476 * 1477 * Uses PIO or DMA to write the contents of the buffer @buf into the parallel 1478 * p FIFO. Returns the number of bytes that were actually written. 1479 */ 1480 static size_t parport_ip32_fifo_write_block(struct parport *p, 1481 const void *buf, size_t len) 1482 { 1483 size_t written = 0; 1484 if (len) 1485 /* FIXME - Maybe some threshold value should be set for @len 1486 * under which we revert to PIO mode? */ 1487 written = (p->modes & PARPORT_MODE_DMA) ? 1488 parport_ip32_fifo_write_block_dma(p, buf, len) : 1489 parport_ip32_fifo_write_block_pio(p, buf, len); 1490 return written; 1491 } 1492 1493 /** 1494 * parport_ip32_drain_fifo - wait for FIFO to empty 1495 * @p: pointer to &struct parport 1496 * @timeout: timeout, in jiffies 1497 * 1498 * This function waits for FIFO to empty. It returns 1 when FIFO is empty, or 1499 * 0 if the timeout @timeout is reached before, or if a signal is pending. 1500 */ 1501 static unsigned int parport_ip32_drain_fifo(struct parport *p, 1502 unsigned long timeout) 1503 { 1504 unsigned long expire = jiffies + timeout; 1505 unsigned int polling_interval; 1506 unsigned int counter; 1507 1508 /* Busy wait for approx. 200us */ 1509 for (counter = 0; counter < 40; counter++) { 1510 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY) 1511 break; 1512 if (time_after(jiffies, expire)) 1513 break; 1514 if (signal_pending(current)) 1515 break; 1516 udelay(5); 1517 } 1518 /* Poll slowly. Polling interval starts with 1 millisecond, and is 1519 * increased exponentially until 128. */ 1520 polling_interval = 1; /* msecs */ 1521 while (!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY)) { 1522 if (time_after_eq(jiffies, expire)) 1523 break; 1524 msleep_interruptible(polling_interval); 1525 if (signal_pending(current)) 1526 break; 1527 if (polling_interval < 128) 1528 polling_interval *= 2; 1529 } 1530 1531 return !!(parport_ip32_read_econtrol(p) & ECR_F_EMPTY); 1532 } 1533 1534 /** 1535 * parport_ip32_get_fifo_residue - reset FIFO 1536 * @p: pointer to &struct parport 1537 * @mode: current operation mode (ECR_MODE_PPF or ECR_MODE_ECP) 1538 * 1539 * This function resets FIFO, and returns the number of bytes remaining in it. 1540 */ 1541 static unsigned int parport_ip32_get_fifo_residue(struct parport *p, 1542 unsigned int mode) 1543 { 1544 struct parport_ip32_private * const priv = p->physport->private_data; 1545 unsigned int residue; 1546 unsigned int cnfga; 1547 1548 /* FIXME - We are missing one byte if the printer is off-line. I 1549 * don't know how to detect this. It looks that the full bit is not 1550 * always reliable. For the moment, the problem is avoided in most 1551 * cases by testing for BUSY in parport_ip32_compat_write_data(). 1552 */ 1553 if (parport_ip32_read_econtrol(p) & ECR_F_EMPTY) 1554 residue = 0; 1555 else { 1556 pr_debug1(PPIP32 "%s: FIFO is stuck\n", p->name); 1557 1558 /* Stop all transfers. 1559 * 1560 * Microsoft's document instructs to drive DCR_STROBE to 0, 1561 * but it doesn't work (at least in Compatibility mode, not 1562 * tested in ECP mode). Switching directly to Test mode (as 1563 * in parport_pc) is not an option: it does confuse the port, 1564 * ECP service interrupts are no more working after that. A 1565 * hard reset is then needed to revert to a sane state. 1566 * 1567 * Let's hope that the FIFO is really stuck and that the 1568 * peripheral doesn't wake up now. 1569 */ 1570 parport_ip32_frob_control(p, DCR_STROBE, 0); 1571 1572 /* Fill up FIFO */ 1573 for (residue = priv->fifo_depth; residue > 0; residue--) { 1574 if (parport_ip32_read_econtrol(p) & ECR_F_FULL) 1575 break; 1576 writeb(0x00, priv->regs.fifo); 1577 } 1578 } 1579 if (residue) 1580 pr_debug1(PPIP32 "%s: %d PWord%s left in FIFO\n", 1581 p->name, residue, 1582 (residue == 1) ? " was" : "s were"); 1583 1584 /* Now reset the FIFO */ 1585 parport_ip32_set_mode(p, ECR_MODE_PS2); 1586 1587 /* Host recovery for ECP mode */ 1588 if (mode == ECR_MODE_ECP) { 1589 parport_ip32_data_reverse(p); 1590 parport_ip32_frob_control(p, DCR_nINIT, 0); 1591 if (parport_wait_peripheral(p, DSR_PERROR, 0)) 1592 pr_debug1(PPIP32 "%s: PEerror timeout 1 in %s\n", 1593 p->name, __func__); 1594 parport_ip32_frob_control(p, DCR_STROBE, DCR_STROBE); 1595 parport_ip32_frob_control(p, DCR_nINIT, DCR_nINIT); 1596 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) 1597 pr_debug1(PPIP32 "%s: PEerror timeout 2 in %s\n", 1598 p->name, __func__); 1599 } 1600 1601 /* Adjust residue if needed */ 1602 parport_ip32_set_mode(p, ECR_MODE_CFG); 1603 cnfga = readb(priv->regs.cnfgA); 1604 if (!(cnfga & CNFGA_nBYTEINTRANS)) { 1605 pr_debug1(PPIP32 "%s: cnfgA contains 0x%02x\n", 1606 p->name, cnfga); 1607 pr_debug1(PPIP32 "%s: Accounting for extra byte\n", 1608 p->name); 1609 residue++; 1610 } 1611 1612 /* Don't care about partial PWords since we do not support 1613 * PWord != 1 byte. */ 1614 1615 /* Back to forward PS2 mode. */ 1616 parport_ip32_set_mode(p, ECR_MODE_PS2); 1617 parport_ip32_data_forward(p); 1618 1619 return residue; 1620 } 1621 1622 /** 1623 * parport_ip32_compat_write_data - write a block of data in SPP mode 1624 * @p: pointer to &struct parport 1625 * @buf: buffer of data to write 1626 * @len: length of buffer @buf 1627 * @flags: ignored 1628 */ 1629 static size_t parport_ip32_compat_write_data(struct parport *p, 1630 const void *buf, size_t len, 1631 int flags) 1632 { 1633 static unsigned int ready_before = 1; 1634 struct parport_ip32_private * const priv = p->physport->private_data; 1635 struct parport * const physport = p->physport; 1636 size_t written = 0; 1637 1638 /* Special case: a timeout of zero means we cannot call schedule(). 1639 * Also if O_NONBLOCK is set then use the default implementation. */ 1640 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 1641 return parport_ieee1284_write_compat(p, buf, len, flags); 1642 1643 /* Reset FIFO, go in forward mode, and disable ackIntEn */ 1644 parport_ip32_set_mode(p, ECR_MODE_PS2); 1645 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1646 parport_ip32_data_forward(p); 1647 parport_ip32_disable_irq(p); 1648 parport_ip32_set_mode(p, ECR_MODE_PPF); 1649 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 1650 1651 /* Wait for peripheral to become ready */ 1652 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT, 1653 DSR_nBUSY | DSR_nFAULT)) { 1654 /* Avoid to flood the logs */ 1655 if (ready_before) 1656 printk(KERN_INFO PPIP32 "%s: not ready in %s\n", 1657 p->name, __func__); 1658 ready_before = 0; 1659 goto stop; 1660 } 1661 ready_before = 1; 1662 1663 written = parport_ip32_fifo_write_block(p, buf, len); 1664 1665 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */ 1666 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth); 1667 1668 /* Check for a potential residue */ 1669 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_PPF); 1670 1671 /* Then, wait for BUSY to get low. */ 1672 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY)) 1673 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n", 1674 p->name, __func__); 1675 1676 stop: 1677 /* Reset FIFO */ 1678 parport_ip32_set_mode(p, ECR_MODE_PS2); 1679 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1680 1681 return written; 1682 } 1683 1684 /* 1685 * FIXME - Insert here parport_ip32_ecp_read_data(). 1686 */ 1687 1688 /** 1689 * parport_ip32_ecp_write_data - write a block of data in ECP mode 1690 * @p: pointer to &struct parport 1691 * @buf: buffer of data to write 1692 * @len: length of buffer @buf 1693 * @flags: ignored 1694 */ 1695 static size_t parport_ip32_ecp_write_data(struct parport *p, 1696 const void *buf, size_t len, 1697 int flags) 1698 { 1699 static unsigned int ready_before = 1; 1700 struct parport_ip32_private * const priv = p->physport->private_data; 1701 struct parport * const physport = p->physport; 1702 size_t written = 0; 1703 1704 /* Special case: a timeout of zero means we cannot call schedule(). 1705 * Also if O_NONBLOCK is set then use the default implementation. */ 1706 if (physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK) 1707 return parport_ieee1284_ecp_write_data(p, buf, len, flags); 1708 1709 /* Negotiate to forward mode if necessary. */ 1710 if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { 1711 /* Event 47: Set nInit high. */ 1712 parport_ip32_frob_control(p, DCR_nINIT | DCR_AUTOFD, 1713 DCR_nINIT | DCR_AUTOFD); 1714 1715 /* Event 49: PError goes high. */ 1716 if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) { 1717 printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s", 1718 p->name, __func__); 1719 physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; 1720 return 0; 1721 } 1722 } 1723 1724 /* Reset FIFO, go in forward mode, and disable ackIntEn */ 1725 parport_ip32_set_mode(p, ECR_MODE_PS2); 1726 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1727 parport_ip32_data_forward(p); 1728 parport_ip32_disable_irq(p); 1729 parport_ip32_set_mode(p, ECR_MODE_ECP); 1730 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; 1731 1732 /* Wait for peripheral to become ready */ 1733 if (parport_wait_peripheral(p, DSR_nBUSY | DSR_nFAULT, 1734 DSR_nBUSY | DSR_nFAULT)) { 1735 /* Avoid to flood the logs */ 1736 if (ready_before) 1737 printk(KERN_INFO PPIP32 "%s: not ready in %s\n", 1738 p->name, __func__); 1739 ready_before = 0; 1740 goto stop; 1741 } 1742 ready_before = 1; 1743 1744 written = parport_ip32_fifo_write_block(p, buf, len); 1745 1746 /* Wait FIFO to empty. Timeout is proportional to FIFO_depth. */ 1747 parport_ip32_drain_fifo(p, physport->cad->timeout * priv->fifo_depth); 1748 1749 /* Check for a potential residue */ 1750 written -= parport_ip32_get_fifo_residue(p, ECR_MODE_ECP); 1751 1752 /* Then, wait for BUSY to get low. */ 1753 if (parport_wait_peripheral(p, DSR_nBUSY, DSR_nBUSY)) 1754 printk(KERN_DEBUG PPIP32 "%s: BUSY timeout in %s\n", 1755 p->name, __func__); 1756 1757 stop: 1758 /* Reset FIFO */ 1759 parport_ip32_set_mode(p, ECR_MODE_PS2); 1760 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; 1761 1762 return written; 1763 } 1764 1765 /* 1766 * FIXME - Insert here parport_ip32_ecp_write_addr(). 1767 */ 1768 1769 /*--- Default parport operations ---------------------------------------*/ 1770 1771 static __initdata struct parport_operations parport_ip32_ops = { 1772 .write_data = parport_ip32_write_data, 1773 .read_data = parport_ip32_read_data, 1774 1775 .write_control = parport_ip32_write_control, 1776 .read_control = parport_ip32_read_control, 1777 .frob_control = parport_ip32_frob_control, 1778 1779 .read_status = parport_ip32_read_status, 1780 1781 .enable_irq = parport_ip32_enable_irq, 1782 .disable_irq = parport_ip32_disable_irq, 1783 1784 .data_forward = parport_ip32_data_forward, 1785 .data_reverse = parport_ip32_data_reverse, 1786 1787 .init_state = parport_ip32_init_state, 1788 .save_state = parport_ip32_save_state, 1789 .restore_state = parport_ip32_restore_state, 1790 1791 .epp_write_data = parport_ieee1284_epp_write_data, 1792 .epp_read_data = parport_ieee1284_epp_read_data, 1793 .epp_write_addr = parport_ieee1284_epp_write_addr, 1794 .epp_read_addr = parport_ieee1284_epp_read_addr, 1795 1796 .ecp_write_data = parport_ieee1284_ecp_write_data, 1797 .ecp_read_data = parport_ieee1284_ecp_read_data, 1798 .ecp_write_addr = parport_ieee1284_ecp_write_addr, 1799 1800 .compat_write_data = parport_ieee1284_write_compat, 1801 .nibble_read_data = parport_ieee1284_read_nibble, 1802 .byte_read_data = parport_ieee1284_read_byte, 1803 1804 .owner = THIS_MODULE, 1805 }; 1806 1807 /*--- Device detection -------------------------------------------------*/ 1808 1809 /** 1810 * parport_ip32_ecp_supported - check for an ECP port 1811 * @p: pointer to the &parport structure 1812 * 1813 * Returns 1 if an ECP port is found, and 0 otherwise. This function actually 1814 * checks if an Extended Control Register seems to be present. On successful 1815 * return, the port is placed in SPP mode. 1816 */ 1817 static __init unsigned int parport_ip32_ecp_supported(struct parport *p) 1818 { 1819 struct parport_ip32_private * const priv = p->physport->private_data; 1820 unsigned int ecr; 1821 1822 ecr = ECR_MODE_PS2 | ECR_nERRINTR | ECR_SERVINTR; 1823 writeb(ecr, priv->regs.ecr); 1824 if (readb(priv->regs.ecr) != (ecr | ECR_F_EMPTY)) 1825 goto fail; 1826 1827 pr_probe(p, "Found working ECR register\n"); 1828 parport_ip32_set_mode(p, ECR_MODE_SPP); 1829 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 1830 return 1; 1831 1832 fail: 1833 pr_probe(p, "ECR register not found\n"); 1834 return 0; 1835 } 1836 1837 /** 1838 * parport_ip32_fifo_supported - check for FIFO parameters 1839 * @p: pointer to the &parport structure 1840 * 1841 * Check for FIFO parameters of an Extended Capabilities Port. Returns 1 on 1842 * success, and 0 otherwise. Adjust FIFO parameters in the parport structure. 1843 * On return, the port is placed in SPP mode. 1844 */ 1845 static __init unsigned int parport_ip32_fifo_supported(struct parport *p) 1846 { 1847 struct parport_ip32_private * const priv = p->physport->private_data; 1848 unsigned int configa, configb; 1849 unsigned int pword; 1850 unsigned int i; 1851 1852 /* Configuration mode */ 1853 parport_ip32_set_mode(p, ECR_MODE_CFG); 1854 configa = readb(priv->regs.cnfgA); 1855 configb = readb(priv->regs.cnfgB); 1856 1857 /* Find out PWord size */ 1858 switch (configa & CNFGA_ID_MASK) { 1859 case CNFGA_ID_8: 1860 pword = 1; 1861 break; 1862 case CNFGA_ID_16: 1863 pword = 2; 1864 break; 1865 case CNFGA_ID_32: 1866 pword = 4; 1867 break; 1868 default: 1869 pr_probe(p, "Unknown implementation ID: 0x%0x\n", 1870 (configa & CNFGA_ID_MASK) >> CNFGA_ID_SHIFT); 1871 goto fail; 1872 break; 1873 } 1874 if (pword != 1) { 1875 pr_probe(p, "Unsupported PWord size: %u\n", pword); 1876 goto fail; 1877 } 1878 priv->pword = pword; 1879 pr_probe(p, "PWord is %u bits\n", 8 * priv->pword); 1880 1881 /* Check for compression support */ 1882 writeb(configb | CNFGB_COMPRESS, priv->regs.cnfgB); 1883 if (readb(priv->regs.cnfgB) & CNFGB_COMPRESS) 1884 pr_probe(p, "Hardware compression detected (unsupported)\n"); 1885 writeb(configb & ~CNFGB_COMPRESS, priv->regs.cnfgB); 1886 1887 /* Reset FIFO and go in test mode (no interrupt, no DMA) */ 1888 parport_ip32_set_mode(p, ECR_MODE_TST); 1889 1890 /* FIFO must be empty now */ 1891 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) { 1892 pr_probe(p, "FIFO not reset\n"); 1893 goto fail; 1894 } 1895 1896 /* Find out FIFO depth. */ 1897 priv->fifo_depth = 0; 1898 for (i = 0; i < 1024; i++) { 1899 if (readb(priv->regs.ecr) & ECR_F_FULL) { 1900 /* FIFO full */ 1901 priv->fifo_depth = i; 1902 break; 1903 } 1904 writeb((u8)i, priv->regs.fifo); 1905 } 1906 if (i >= 1024) { 1907 pr_probe(p, "Can't fill FIFO\n"); 1908 goto fail; 1909 } 1910 if (!priv->fifo_depth) { 1911 pr_probe(p, "Can't get FIFO depth\n"); 1912 goto fail; 1913 } 1914 pr_probe(p, "FIFO is %u PWords deep\n", priv->fifo_depth); 1915 1916 /* Enable interrupts */ 1917 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1918 1919 /* Find out writeIntrThreshold: number of PWords we know we can write 1920 * if we get an interrupt. */ 1921 priv->writeIntrThreshold = 0; 1922 for (i = 0; i < priv->fifo_depth; i++) { 1923 if (readb(priv->regs.fifo) != (u8)i) { 1924 pr_probe(p, "Invalid data in FIFO\n"); 1925 goto fail; 1926 } 1927 if (!priv->writeIntrThreshold 1928 && readb(priv->regs.ecr) & ECR_SERVINTR) 1929 /* writeIntrThreshold reached */ 1930 priv->writeIntrThreshold = i + 1; 1931 if (i + 1 < priv->fifo_depth 1932 && readb(priv->regs.ecr) & ECR_F_EMPTY) { 1933 /* FIFO empty before the last byte? */ 1934 pr_probe(p, "Data lost in FIFO\n"); 1935 goto fail; 1936 } 1937 } 1938 if (!priv->writeIntrThreshold) { 1939 pr_probe(p, "Can't get writeIntrThreshold\n"); 1940 goto fail; 1941 } 1942 pr_probe(p, "writeIntrThreshold is %u\n", priv->writeIntrThreshold); 1943 1944 /* FIFO must be empty now */ 1945 if (!(readb(priv->regs.ecr) & ECR_F_EMPTY)) { 1946 pr_probe(p, "Can't empty FIFO\n"); 1947 goto fail; 1948 } 1949 1950 /* Reset FIFO */ 1951 parport_ip32_set_mode(p, ECR_MODE_PS2); 1952 /* Set reverse direction (must be in PS2 mode) */ 1953 parport_ip32_data_reverse(p); 1954 /* Test FIFO, no interrupt, no DMA */ 1955 parport_ip32_set_mode(p, ECR_MODE_TST); 1956 /* Enable interrupts */ 1957 parport_ip32_frob_econtrol(p, ECR_SERVINTR, 0); 1958 1959 /* Find out readIntrThreshold: number of PWords we can read if we get 1960 * an interrupt. */ 1961 priv->readIntrThreshold = 0; 1962 for (i = 0; i < priv->fifo_depth; i++) { 1963 writeb(0xaa, priv->regs.fifo); 1964 if (readb(priv->regs.ecr) & ECR_SERVINTR) { 1965 /* readIntrThreshold reached */ 1966 priv->readIntrThreshold = i + 1; 1967 break; 1968 } 1969 } 1970 if (!priv->readIntrThreshold) { 1971 pr_probe(p, "Can't get readIntrThreshold\n"); 1972 goto fail; 1973 } 1974 pr_probe(p, "readIntrThreshold is %u\n", priv->readIntrThreshold); 1975 1976 /* Reset ECR */ 1977 parport_ip32_set_mode(p, ECR_MODE_PS2); 1978 parport_ip32_data_forward(p); 1979 parport_ip32_set_mode(p, ECR_MODE_SPP); 1980 return 1; 1981 1982 fail: 1983 priv->fifo_depth = 0; 1984 parport_ip32_set_mode(p, ECR_MODE_SPP); 1985 return 0; 1986 } 1987 1988 /*--- Initialization code ----------------------------------------------*/ 1989 1990 /** 1991 * parport_ip32_make_isa_registers - compute (ISA) register addresses 1992 * @regs: pointer to &struct parport_ip32_regs to fill 1993 * @base: base address of standard and EPP registers 1994 * @base_hi: base address of ECP registers 1995 * @regshift: how much to shift register offset by 1996 * 1997 * Compute register addresses, according to the ISA standard. The addresses 1998 * of the standard and EPP registers are computed from address @base. The 1999 * addresses of the ECP registers are computed from address @base_hi. 2000 */ 2001 static void __init 2002 parport_ip32_make_isa_registers(struct parport_ip32_regs *regs, 2003 void __iomem *base, void __iomem *base_hi, 2004 unsigned int regshift) 2005 { 2006 #define r_base(offset) ((u8 __iomem *)base + ((offset) << regshift)) 2007 #define r_base_hi(offset) ((u8 __iomem *)base_hi + ((offset) << regshift)) 2008 *regs = (struct parport_ip32_regs){ 2009 .data = r_base(0), 2010 .dsr = r_base(1), 2011 .dcr = r_base(2), 2012 .eppAddr = r_base(3), 2013 .eppData0 = r_base(4), 2014 .eppData1 = r_base(5), 2015 .eppData2 = r_base(6), 2016 .eppData3 = r_base(7), 2017 .ecpAFifo = r_base(0), 2018 .fifo = r_base_hi(0), 2019 .cnfgA = r_base_hi(0), 2020 .cnfgB = r_base_hi(1), 2021 .ecr = r_base_hi(2) 2022 }; 2023 #undef r_base_hi 2024 #undef r_base 2025 } 2026 2027 /** 2028 * parport_ip32_probe_port - probe and register IP32 built-in parallel port 2029 * 2030 * Returns the new allocated &parport structure. On error, an error code is 2031 * encoded in return value with the ERR_PTR function. 2032 */ 2033 static __init struct parport *parport_ip32_probe_port(void) 2034 { 2035 struct parport_ip32_regs regs; 2036 struct parport_ip32_private *priv = NULL; 2037 struct parport_operations *ops = NULL; 2038 struct parport *p = NULL; 2039 int err; 2040 2041 parport_ip32_make_isa_registers(®s, &mace->isa.parallel, 2042 &mace->isa.ecp1284, 8 /* regshift */); 2043 2044 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL); 2045 priv = kmalloc(sizeof(struct parport_ip32_private), GFP_KERNEL); 2046 p = parport_register_port(0, PARPORT_IRQ_NONE, PARPORT_DMA_NONE, ops); 2047 if (ops == NULL || priv == NULL || p == NULL) { 2048 err = -ENOMEM; 2049 goto fail; 2050 } 2051 p->base = MACE_BASE + offsetof(struct sgi_mace, isa.parallel); 2052 p->base_hi = MACE_BASE + offsetof(struct sgi_mace, isa.ecp1284); 2053 p->private_data = priv; 2054 2055 *ops = parport_ip32_ops; 2056 *priv = (struct parport_ip32_private){ 2057 .regs = regs, 2058 .dcr_writable = DCR_DIR | DCR_SELECT | DCR_nINIT | 2059 DCR_AUTOFD | DCR_STROBE, 2060 .irq_mode = PARPORT_IP32_IRQ_FWD, 2061 }; 2062 init_completion(&priv->irq_complete); 2063 2064 /* Probe port. */ 2065 if (!parport_ip32_ecp_supported(p)) { 2066 err = -ENODEV; 2067 goto fail; 2068 } 2069 parport_ip32_dump_state(p, "begin init", 0); 2070 2071 /* We found what looks like a working ECR register. Simply assume 2072 * that all modes are correctly supported. Enable basic modes. */ 2073 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT; 2074 p->modes |= PARPORT_MODE_TRISTATE; 2075 2076 if (!parport_ip32_fifo_supported(p)) { 2077 printk(KERN_WARNING PPIP32 2078 "%s: error: FIFO disabled\n", p->name); 2079 /* Disable hardware modes depending on a working FIFO. */ 2080 features &= ~PARPORT_IP32_ENABLE_SPP; 2081 features &= ~PARPORT_IP32_ENABLE_ECP; 2082 /* DMA is not needed if FIFO is not supported. */ 2083 features &= ~PARPORT_IP32_ENABLE_DMA; 2084 } 2085 2086 /* Request IRQ */ 2087 if (features & PARPORT_IP32_ENABLE_IRQ) { 2088 int irq = MACEISA_PARALLEL_IRQ; 2089 if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) { 2090 printk(KERN_WARNING PPIP32 2091 "%s: error: IRQ disabled\n", p->name); 2092 /* DMA cannot work without interrupts. */ 2093 features &= ~PARPORT_IP32_ENABLE_DMA; 2094 } else { 2095 pr_probe(p, "Interrupt support enabled\n"); 2096 p->irq = irq; 2097 priv->dcr_writable |= DCR_IRQ; 2098 } 2099 } 2100 2101 /* Allocate DMA resources */ 2102 if (features & PARPORT_IP32_ENABLE_DMA) { 2103 if (parport_ip32_dma_register()) 2104 printk(KERN_WARNING PPIP32 2105 "%s: error: DMA disabled\n", p->name); 2106 else { 2107 pr_probe(p, "DMA support enabled\n"); 2108 p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */ 2109 p->modes |= PARPORT_MODE_DMA; 2110 } 2111 } 2112 2113 if (features & PARPORT_IP32_ENABLE_SPP) { 2114 /* Enable compatibility FIFO mode */ 2115 p->ops->compat_write_data = parport_ip32_compat_write_data; 2116 p->modes |= PARPORT_MODE_COMPAT; 2117 pr_probe(p, "Hardware support for SPP mode enabled\n"); 2118 } 2119 if (features & PARPORT_IP32_ENABLE_EPP) { 2120 /* Set up access functions to use EPP hardware. */ 2121 p->ops->epp_read_data = parport_ip32_epp_read_data; 2122 p->ops->epp_write_data = parport_ip32_epp_write_data; 2123 p->ops->epp_read_addr = parport_ip32_epp_read_addr; 2124 p->ops->epp_write_addr = parport_ip32_epp_write_addr; 2125 p->modes |= PARPORT_MODE_EPP; 2126 pr_probe(p, "Hardware support for EPP mode enabled\n"); 2127 } 2128 if (features & PARPORT_IP32_ENABLE_ECP) { 2129 /* Enable ECP FIFO mode */ 2130 p->ops->ecp_write_data = parport_ip32_ecp_write_data; 2131 /* FIXME - not implemented */ 2132 /* p->ops->ecp_read_data = parport_ip32_ecp_read_data; */ 2133 /* p->ops->ecp_write_addr = parport_ip32_ecp_write_addr; */ 2134 p->modes |= PARPORT_MODE_ECP; 2135 pr_probe(p, "Hardware support for ECP mode enabled\n"); 2136 } 2137 2138 /* Initialize the port with sensible values */ 2139 parport_ip32_set_mode(p, ECR_MODE_PS2); 2140 parport_ip32_write_control(p, DCR_SELECT | DCR_nINIT); 2141 parport_ip32_data_forward(p); 2142 parport_ip32_disable_irq(p); 2143 parport_ip32_write_data(p, 0x00); 2144 parport_ip32_dump_state(p, "end init", 0); 2145 2146 /* Print out what we found */ 2147 printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)", 2148 p->name, p->base, p->base_hi); 2149 if (p->irq != PARPORT_IRQ_NONE) 2150 printk(", irq %d", p->irq); 2151 printk(" ["); 2152 #define printmode(x) if (p->modes & PARPORT_MODE_##x) \ 2153 printk("%s%s", f++ ? "," : "", #x) 2154 { 2155 unsigned int f = 0; 2156 printmode(PCSPP); 2157 printmode(TRISTATE); 2158 printmode(COMPAT); 2159 printmode(EPP); 2160 printmode(ECP); 2161 printmode(DMA); 2162 } 2163 #undef printmode 2164 printk("]\n"); 2165 2166 parport_announce_port(p); 2167 return p; 2168 2169 fail: 2170 if (p) 2171 parport_put_port(p); 2172 kfree(priv); 2173 kfree(ops); 2174 return ERR_PTR(err); 2175 } 2176 2177 /** 2178 * parport_ip32_unregister_port - unregister a parallel port 2179 * @p: pointer to the &struct parport 2180 * 2181 * Unregisters a parallel port and free previously allocated resources 2182 * (memory, IRQ, ...). 2183 */ 2184 static __exit void parport_ip32_unregister_port(struct parport *p) 2185 { 2186 struct parport_ip32_private * const priv = p->physport->private_data; 2187 struct parport_operations *ops = p->ops; 2188 2189 parport_remove_port(p); 2190 if (p->modes & PARPORT_MODE_DMA) 2191 parport_ip32_dma_unregister(); 2192 if (p->irq != PARPORT_IRQ_NONE) 2193 free_irq(p->irq, p); 2194 parport_put_port(p); 2195 kfree(priv); 2196 kfree(ops); 2197 } 2198 2199 /** 2200 * parport_ip32_init - module initialization function 2201 */ 2202 static int __init parport_ip32_init(void) 2203 { 2204 pr_info(PPIP32 "SGI IP32 built-in parallel port driver v0.6\n"); 2205 pr_debug1(PPIP32 "Compiled on %s, %s\n", __DATE__, __TIME__); 2206 this_port = parport_ip32_probe_port(); 2207 return IS_ERR(this_port) ? PTR_ERR(this_port) : 0; 2208 } 2209 2210 /** 2211 * parport_ip32_exit - module termination function 2212 */ 2213 static void __exit parport_ip32_exit(void) 2214 { 2215 parport_ip32_unregister_port(this_port); 2216 } 2217 2218 /*--- Module stuff -----------------------------------------------------*/ 2219 2220 MODULE_AUTHOR("Arnaud Giersch <arnaud.giersch@free.fr>"); 2221 MODULE_DESCRIPTION("SGI IP32 built-in parallel port driver"); 2222 MODULE_LICENSE("GPL"); 2223 MODULE_VERSION("0.6"); /* update in parport_ip32_init() too */ 2224 2225 module_init(parport_ip32_init); 2226 module_exit(parport_ip32_exit); 2227 2228 module_param(verbose_probing, bool, S_IRUGO); 2229 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialization"); 2230 2231 module_param(features, uint, S_IRUGO); 2232 MODULE_PARM_DESC(features, 2233 "Bit mask of features to enable" 2234 ", bit 0: IRQ support" 2235 ", bit 1: DMA support" 2236 ", bit 2: hardware SPP mode" 2237 ", bit 3: hardware EPP mode" 2238 ", bit 4: hardware ECP mode"); 2239 2240 /*--- Inform (X)Emacs about preferred coding style ---------------------*/ 2241 /* 2242 * Local Variables: 2243 * mode: c 2244 * c-file-style: "linux" 2245 * indent-tabs-mode: t 2246 * tab-width: 8 2247 * fill-column: 78 2248 * ispell-local-dictionary: "american" 2249 * End: 2250 */ 2251