1 /* 2 ** System Bus Adapter (SBA) I/O MMU manager 3 ** 4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 6 ** (c) Copyright 2000-2004 Hewlett-Packard Company 7 ** 8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 17 ** J5000/J7000/N-class/L-class machines and their successors. 18 ** 19 ** FIXME: add DMA hint support programming in both sba and lba modules. 20 */ 21 22 #include <linux/types.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/slab.h> 26 #include <linux/init.h> 27 28 #include <linux/mm.h> 29 #include <linux/string.h> 30 #include <linux/pci.h> 31 #include <linux/scatterlist.h> 32 #include <linux/iommu-helper.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/io.h> 36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 37 38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 39 40 #include <linux/proc_fs.h> 41 #include <linux/seq_file.h> 42 #include <linux/module.h> 43 44 #include <asm/ropes.h> 45 #include <asm/mckinley.h> /* for proc_mckinley_root */ 46 #include <asm/runway.h> /* for proc_runway_root */ 47 #include <asm/page.h> /* for PAGE0 */ 48 #include <asm/pdc.h> /* for PDC_MODEL_* */ 49 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 50 #include <asm/parisc-device.h> 51 52 #define MODULE_NAME "SBA" 53 54 /* 55 ** The number of debug flags is a clue - this code is fragile. 56 ** Don't even think about messing with it unless you have 57 ** plenty of 710's to sacrifice to the computer gods. :^) 58 */ 59 #undef DEBUG_SBA_INIT 60 #undef DEBUG_SBA_RUN 61 #undef DEBUG_SBA_RUN_SG 62 #undef DEBUG_SBA_RESOURCE 63 #undef ASSERT_PDIR_SANITY 64 #undef DEBUG_LARGE_SG_ENTRIES 65 #undef DEBUG_DMB_TRAP 66 67 #ifdef DEBUG_SBA_INIT 68 #define DBG_INIT(x...) printk(x) 69 #else 70 #define DBG_INIT(x...) 71 #endif 72 73 #ifdef DEBUG_SBA_RUN 74 #define DBG_RUN(x...) printk(x) 75 #else 76 #define DBG_RUN(x...) 77 #endif 78 79 #ifdef DEBUG_SBA_RUN_SG 80 #define DBG_RUN_SG(x...) printk(x) 81 #else 82 #define DBG_RUN_SG(x...) 83 #endif 84 85 86 #ifdef DEBUG_SBA_RESOURCE 87 #define DBG_RES(x...) printk(x) 88 #else 89 #define DBG_RES(x...) 90 #endif 91 92 #define SBA_INLINE __inline__ 93 94 #define DEFAULT_DMA_HINT_REG 0 95 96 struct sba_device *sba_list; 97 EXPORT_SYMBOL_GPL(sba_list); 98 99 static unsigned long ioc_needs_fdc = 0; 100 101 /* global count of IOMMUs in the system */ 102 static unsigned int global_ioc_cnt = 0; 103 104 /* PA8700 (Piranha 2.2) bug workaround */ 105 static unsigned long piranha_bad_128k = 0; 106 107 /* Looks nice and keeps the compiler happy */ 108 #define SBA_DEV(d) ((struct sba_device *) (d)) 109 110 #ifdef CONFIG_AGP_PARISC 111 #define SBA_AGP_SUPPORT 112 #endif /*CONFIG_AGP_PARISC*/ 113 114 #ifdef SBA_AGP_SUPPORT 115 static int sba_reserve_agpgart = 1; 116 module_param(sba_reserve_agpgart, int, 0444); 117 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); 118 #endif 119 120 121 /************************************ 122 ** SBA register read and write support 123 ** 124 ** BE WARNED: register writes are posted. 125 ** (ie follow writes which must reach HW with a read) 126 ** 127 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 128 */ 129 #define READ_REG32(addr) readl(addr) 130 #define READ_REG64(addr) readq(addr) 131 #define WRITE_REG32(val, addr) writel((val), (addr)) 132 #define WRITE_REG64(val, addr) writeq((val), (addr)) 133 134 #ifdef CONFIG_64BIT 135 #define READ_REG(addr) READ_REG64(addr) 136 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 137 #else 138 #define READ_REG(addr) READ_REG32(addr) 139 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 140 #endif 141 142 #ifdef DEBUG_SBA_INIT 143 144 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 145 146 /** 147 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 148 * @hpa: base address of the sba 149 * 150 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 151 * IO Adapter (aka Bus Converter). 152 */ 153 static void 154 sba_dump_ranges(void __iomem *hpa) 155 { 156 DBG_INIT("SBA at 0x%p\n", hpa); 157 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 158 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 159 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 160 DBG_INIT("\n"); 161 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 162 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 163 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 164 } 165 166 /** 167 * sba_dump_tlb - debugging only - print IOMMU operating parameters 168 * @hpa: base address of the IOMMU 169 * 170 * Print the size/location of the IO MMU PDIR. 171 */ 172 static void sba_dump_tlb(void __iomem *hpa) 173 { 174 DBG_INIT("IO TLB at 0x%p\n", hpa); 175 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 176 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 177 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 178 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 179 DBG_INIT("\n"); 180 } 181 #else 182 #define sba_dump_ranges(x) 183 #define sba_dump_tlb(x) 184 #endif /* DEBUG_SBA_INIT */ 185 186 187 #ifdef ASSERT_PDIR_SANITY 188 189 /** 190 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 191 * @ioc: IO MMU structure which owns the pdir we are interested in. 192 * @msg: text to print ont the output line. 193 * @pide: pdir index. 194 * 195 * Print one entry of the IO MMU PDIR in human readable form. 196 */ 197 static void 198 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 199 { 200 /* start printing from lowest pde in rval */ 201 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 202 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 203 uint rcnt; 204 205 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 206 msg, 207 rptr, pide & (BITS_PER_LONG - 1), *rptr); 208 209 rcnt = 0; 210 while (rcnt < BITS_PER_LONG) { 211 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 212 (rcnt == (pide & (BITS_PER_LONG - 1))) 213 ? " -->" : " ", 214 rcnt, ptr, *ptr ); 215 rcnt++; 216 ptr++; 217 } 218 printk(KERN_DEBUG "%s", msg); 219 } 220 221 222 /** 223 * sba_check_pdir - debugging only - consistency checker 224 * @ioc: IO MMU structure which owns the pdir we are interested in. 225 * @msg: text to print ont the output line. 226 * 227 * Verify the resource map and pdir state is consistent 228 */ 229 static int 230 sba_check_pdir(struct ioc *ioc, char *msg) 231 { 232 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 233 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 234 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 235 uint pide = 0; 236 237 while (rptr < rptr_end) { 238 u32 rval = *rptr; 239 int rcnt = 32; /* number of bits we might check */ 240 241 while (rcnt) { 242 /* Get last byte and highest bit from that */ 243 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 244 if ((rval ^ pde) & 0x80000000) 245 { 246 /* 247 ** BUMMER! -- res_map != pdir -- 248 ** Dump rval and matching pdir entries 249 */ 250 sba_dump_pdir_entry(ioc, msg, pide); 251 return(1); 252 } 253 rcnt--; 254 rval <<= 1; /* try the next bit */ 255 pptr++; 256 pide++; 257 } 258 rptr++; /* look at next word of res_map */ 259 } 260 /* It'd be nice if we always got here :^) */ 261 return 0; 262 } 263 264 265 /** 266 * sba_dump_sg - debugging only - print Scatter-Gather list 267 * @ioc: IO MMU structure which owns the pdir we are interested in. 268 * @startsg: head of the SG list 269 * @nents: number of entries in SG list 270 * 271 * print the SG list so we can verify it's correct by hand. 272 */ 273 static void 274 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 275 { 276 while (nents-- > 0) { 277 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 278 nents, 279 (unsigned long) sg_dma_address(startsg), 280 sg_dma_len(startsg), 281 sg_virt_addr(startsg), startsg->length); 282 startsg++; 283 } 284 } 285 286 #endif /* ASSERT_PDIR_SANITY */ 287 288 289 290 291 /************************************************************** 292 * 293 * I/O Pdir Resource Management 294 * 295 * Bits set in the resource map are in use. 296 * Each bit can represent a number of pages. 297 * LSbs represent lower addresses (IOVA's). 298 * 299 ***************************************************************/ 300 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 301 302 /* Convert from IOVP to IOVA and vice versa. */ 303 304 #ifdef ZX1_SUPPORT 305 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 306 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 307 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 308 #else 309 /* only support Astro and ancestors. Saves a few cycles in key places */ 310 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 311 #define SBA_IOVP(ioc,iova) (iova) 312 #endif 313 314 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 315 316 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 317 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 318 319 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, 320 unsigned int bitshiftcnt) 321 { 322 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) 323 + bitshiftcnt; 324 } 325 326 /** 327 * sba_search_bitmap - find free space in IO PDIR resource bitmap 328 * @ioc: IO MMU structure which owns the pdir we are interested in. 329 * @bits_wanted: number of entries we need. 330 * 331 * Find consecutive free bits in resource bitmap. 332 * Each bit represents one entry in the IO Pdir. 333 * Cool perf optimization: search for log2(size) bits at a time. 334 */ 335 static SBA_INLINE unsigned long 336 sba_search_bitmap(struct ioc *ioc, struct device *dev, 337 unsigned long bits_wanted) 338 { 339 unsigned long *res_ptr = ioc->res_hint; 340 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 341 unsigned long pide = ~0UL, tpide; 342 unsigned long boundary_size; 343 unsigned long shift; 344 int ret; 345 346 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, 347 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; 348 349 #if defined(ZX1_SUPPORT) 350 BUG_ON(ioc->ibase & ~IOVP_MASK); 351 shift = ioc->ibase >> IOVP_SHIFT; 352 #else 353 shift = 0; 354 #endif 355 356 if (bits_wanted > (BITS_PER_LONG/2)) { 357 /* Search word at a time - no mask needed */ 358 for(; res_ptr < res_end; ++res_ptr) { 359 tpide = ptr_to_pide(ioc, res_ptr, 0); 360 ret = iommu_is_span_boundary(tpide, bits_wanted, 361 shift, 362 boundary_size); 363 if ((*res_ptr == 0) && !ret) { 364 *res_ptr = RESMAP_MASK(bits_wanted); 365 pide = tpide; 366 break; 367 } 368 } 369 /* point to the next word on next pass */ 370 res_ptr++; 371 ioc->res_bitshift = 0; 372 } else { 373 /* 374 ** Search the resource bit map on well-aligned values. 375 ** "o" is the alignment. 376 ** We need the alignment to invalidate I/O TLB using 377 ** SBA HW features in the unmap path. 378 */ 379 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 380 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); 381 unsigned long mask; 382 383 if (bitshiftcnt >= BITS_PER_LONG) { 384 bitshiftcnt = 0; 385 res_ptr++; 386 } 387 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 388 389 DBG_RES("%s() o %ld %p", __func__, o, res_ptr); 390 while(res_ptr < res_end) 391 { 392 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 393 WARN_ON(mask == 0); 394 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); 395 ret = iommu_is_span_boundary(tpide, bits_wanted, 396 shift, 397 boundary_size); 398 if ((((*res_ptr) & mask) == 0) && !ret) { 399 *res_ptr |= mask; /* mark resources busy! */ 400 pide = tpide; 401 break; 402 } 403 mask >>= o; 404 bitshiftcnt += o; 405 if (mask == 0) { 406 mask = RESMAP_MASK(bits_wanted); 407 bitshiftcnt=0; 408 res_ptr++; 409 } 410 } 411 /* look in the same word on the next pass */ 412 ioc->res_bitshift = bitshiftcnt + bits_wanted; 413 } 414 415 /* wrapped ? */ 416 if (res_end <= res_ptr) { 417 ioc->res_hint = (unsigned long *) ioc->res_map; 418 ioc->res_bitshift = 0; 419 } else { 420 ioc->res_hint = res_ptr; 421 } 422 return (pide); 423 } 424 425 426 /** 427 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 428 * @ioc: IO MMU structure which owns the pdir we are interested in. 429 * @size: number of bytes to create a mapping for 430 * 431 * Given a size, find consecutive unmarked and then mark those bits in the 432 * resource bit map. 433 */ 434 static int 435 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 436 { 437 unsigned int pages_needed = size >> IOVP_SHIFT; 438 #ifdef SBA_COLLECT_STATS 439 unsigned long cr_start = mfctl(16); 440 #endif 441 unsigned long pide; 442 443 pide = sba_search_bitmap(ioc, dev, pages_needed); 444 if (pide >= (ioc->res_size << 3)) { 445 pide = sba_search_bitmap(ioc, dev, pages_needed); 446 if (pide >= (ioc->res_size << 3)) 447 panic("%s: I/O MMU @ %p is out of mapping resources\n", 448 __FILE__, ioc->ioc_hpa); 449 } 450 451 #ifdef ASSERT_PDIR_SANITY 452 /* verify the first enable bit is clear */ 453 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 454 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 455 } 456 #endif 457 458 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 459 __func__, size, pages_needed, pide, 460 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 461 ioc->res_bitshift ); 462 463 #ifdef SBA_COLLECT_STATS 464 { 465 unsigned long cr_end = mfctl(16); 466 unsigned long tmp = cr_end - cr_start; 467 /* check for roll over */ 468 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 469 } 470 ioc->avg_search[ioc->avg_idx++] = cr_start; 471 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 472 473 ioc->used_pages += pages_needed; 474 #endif 475 476 return (pide); 477 } 478 479 480 /** 481 * sba_free_range - unmark bits in IO PDIR resource bitmap 482 * @ioc: IO MMU structure which owns the pdir we are interested in. 483 * @iova: IO virtual address which was previously allocated. 484 * @size: number of bytes to create a mapping for 485 * 486 * clear bits in the ioc's resource map 487 */ 488 static SBA_INLINE void 489 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 490 { 491 unsigned long iovp = SBA_IOVP(ioc, iova); 492 unsigned int pide = PDIR_INDEX(iovp); 493 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 494 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 495 496 int bits_not_wanted = size >> IOVP_SHIFT; 497 498 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 499 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 500 501 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 502 __func__, (uint) iova, size, 503 bits_not_wanted, m, pide, res_ptr, *res_ptr); 504 505 #ifdef SBA_COLLECT_STATS 506 ioc->used_pages -= bits_not_wanted; 507 #endif 508 509 *res_ptr &= ~m; 510 } 511 512 513 /************************************************************** 514 * 515 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 516 * 517 ***************************************************************/ 518 519 #ifdef SBA_HINT_SUPPORT 520 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 521 #endif 522 523 typedef unsigned long space_t; 524 #define KERNEL_SPACE 0 525 526 /** 527 * sba_io_pdir_entry - fill in one IO PDIR entry 528 * @pdir_ptr: pointer to IO PDIR entry 529 * @sid: process Space ID - currently only support KERNEL_SPACE 530 * @vba: Virtual CPU address of buffer to map 531 * @hint: DMA hint set to use for this mapping 532 * 533 * SBA Mapping Routine 534 * 535 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 536 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 537 * pdir_ptr (arg0). 538 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 539 * for Astro/Ike looks like: 540 * 541 * 542 * 0 19 51 55 63 543 * +-+---------------------+----------------------------------+----+--------+ 544 * |V| U | PPN[43:12] | U | VI | 545 * +-+---------------------+----------------------------------+----+--------+ 546 * 547 * Pluto is basically identical, supports fewer physical address bits: 548 * 549 * 0 23 51 55 63 550 * +-+------------------------+-------------------------------+----+--------+ 551 * |V| U | PPN[39:12] | U | VI | 552 * +-+------------------------+-------------------------------+----+--------+ 553 * 554 * V == Valid Bit (Most Significant Bit is bit 0) 555 * U == Unused 556 * PPN == Physical Page Number 557 * VI == Virtual Index (aka Coherent Index) 558 * 559 * LPA instruction output is put into PPN field. 560 * LCI (Load Coherence Index) instruction provides the "VI" bits. 561 * 562 * We pre-swap the bytes since PCX-W is Big Endian and the 563 * IOMMU uses little endian for the pdir. 564 */ 565 566 static void SBA_INLINE 567 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 568 unsigned long hint) 569 { 570 u64 pa; /* physical address */ 571 register unsigned ci; /* coherent index */ 572 573 pa = virt_to_phys(vba); 574 pa &= IOVP_MASK; 575 576 mtsp(sid,1); 577 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 578 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */ 579 580 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 581 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 582 583 /* 584 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 585 * (bit #61, big endian), we have to flush and sync every time 586 * IO-PDIR is changed in Ike/Astro. 587 */ 588 if (ioc_needs_fdc) 589 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 590 } 591 592 593 /** 594 * sba_mark_invalid - invalidate one or more IO PDIR entries 595 * @ioc: IO MMU structure which owns the pdir we are interested in. 596 * @iova: IO Virtual Address mapped earlier 597 * @byte_cnt: number of bytes this mapping covers. 598 * 599 * Marking the IO PDIR entry(ies) as Invalid and invalidate 600 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 601 * is to purge stale entries in the IO TLB when unmapping entries. 602 * 603 * The PCOM register supports purging of multiple pages, with a minium 604 * of 1 page and a maximum of 2GB. Hardware requires the address be 605 * aligned to the size of the range being purged. The size of the range 606 * must be a power of 2. The "Cool perf optimization" in the 607 * allocation routine helps keep that true. 608 */ 609 static SBA_INLINE void 610 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 611 { 612 u32 iovp = (u32) SBA_IOVP(ioc,iova); 613 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 614 615 #ifdef ASSERT_PDIR_SANITY 616 /* Assert first pdir entry is set. 617 ** 618 ** Even though this is a big-endian machine, the entries 619 ** in the iopdir are little endian. That's why we look at 620 ** the byte at +7 instead of at +0. 621 */ 622 if (0x80 != (((u8 *) pdir_ptr)[7])) { 623 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 624 } 625 #endif 626 627 if (byte_cnt > IOVP_SIZE) 628 { 629 #if 0 630 unsigned long entries_per_cacheline = ioc_needs_fdc ? 631 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 632 - (unsigned long) pdir_ptr; 633 : 262144; 634 #endif 635 636 /* set "size" field for PCOM */ 637 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 638 639 do { 640 /* clear I/O Pdir entry "valid" bit first */ 641 ((u8 *) pdir_ptr)[7] = 0; 642 if (ioc_needs_fdc) { 643 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 644 #if 0 645 entries_per_cacheline = L1_CACHE_SHIFT - 3; 646 #endif 647 } 648 pdir_ptr++; 649 byte_cnt -= IOVP_SIZE; 650 } while (byte_cnt > IOVP_SIZE); 651 } else 652 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 653 654 /* 655 ** clear I/O PDIR entry "valid" bit. 656 ** We have to R/M/W the cacheline regardless how much of the 657 ** pdir entry that we clobber. 658 ** The rest of the entry would be useful for debugging if we 659 ** could dump core on HPMC. 660 */ 661 ((u8 *) pdir_ptr)[7] = 0; 662 if (ioc_needs_fdc) 663 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 664 665 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 666 } 667 668 /** 669 * sba_dma_supported - PCI driver can query DMA support 670 * @dev: instance of PCI owned by the driver that's asking 671 * @mask: number of address bits this PCI device can handle 672 * 673 * See Documentation/DMA-API-HOWTO.txt 674 */ 675 static int sba_dma_supported( struct device *dev, u64 mask) 676 { 677 struct ioc *ioc; 678 679 if (dev == NULL) { 680 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 681 BUG(); 682 return(0); 683 } 684 685 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit 686 * first, then fall back to 32-bit if that fails. 687 * We are just "encouraging" 32-bit DMA masks here since we can 688 * never allow IOMMU bypass unless we add special support for ZX1. 689 */ 690 if (mask > ~0U) 691 return 0; 692 693 ioc = GET_IOC(dev); 694 695 /* 696 * check if mask is >= than the current max IO Virt Address 697 * The max IO Virt address will *always* < 30 bits. 698 */ 699 return((int)(mask >= (ioc->ibase - 1 + 700 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 701 } 702 703 704 /** 705 * sba_map_single - map one buffer and return IOVA for DMA 706 * @dev: instance of PCI owned by the driver that's asking. 707 * @addr: driver buffer to map. 708 * @size: number of bytes to map in driver buffer. 709 * @direction: R/W or both. 710 * 711 * See Documentation/DMA-API-HOWTO.txt 712 */ 713 static dma_addr_t 714 sba_map_single(struct device *dev, void *addr, size_t size, 715 enum dma_data_direction direction) 716 { 717 struct ioc *ioc; 718 unsigned long flags; 719 dma_addr_t iovp; 720 dma_addr_t offset; 721 u64 *pdir_start; 722 int pide; 723 724 ioc = GET_IOC(dev); 725 726 /* save offset bits */ 727 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; 728 729 /* round up to nearest IOVP_SIZE */ 730 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 731 732 spin_lock_irqsave(&ioc->res_lock, flags); 733 #ifdef ASSERT_PDIR_SANITY 734 sba_check_pdir(ioc,"Check before sba_map_single()"); 735 #endif 736 737 #ifdef SBA_COLLECT_STATS 738 ioc->msingle_calls++; 739 ioc->msingle_pages += size >> IOVP_SHIFT; 740 #endif 741 pide = sba_alloc_range(ioc, dev, size); 742 iovp = (dma_addr_t) pide << IOVP_SHIFT; 743 744 DBG_RUN("%s() 0x%p -> 0x%lx\n", 745 __func__, addr, (long) iovp | offset); 746 747 pdir_start = &(ioc->pdir_base[pide]); 748 749 while (size > 0) { 750 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); 751 752 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 753 pdir_start, 754 (u8) (((u8 *) pdir_start)[7]), 755 (u8) (((u8 *) pdir_start)[6]), 756 (u8) (((u8 *) pdir_start)[5]), 757 (u8) (((u8 *) pdir_start)[4]), 758 (u8) (((u8 *) pdir_start)[3]), 759 (u8) (((u8 *) pdir_start)[2]), 760 (u8) (((u8 *) pdir_start)[1]), 761 (u8) (((u8 *) pdir_start)[0]) 762 ); 763 764 addr += IOVP_SIZE; 765 size -= IOVP_SIZE; 766 pdir_start++; 767 } 768 769 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 770 if (ioc_needs_fdc) 771 asm volatile("sync" : : ); 772 773 #ifdef ASSERT_PDIR_SANITY 774 sba_check_pdir(ioc,"Check after sba_map_single()"); 775 #endif 776 spin_unlock_irqrestore(&ioc->res_lock, flags); 777 778 /* form complete address */ 779 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 780 } 781 782 783 /** 784 * sba_unmap_single - unmap one IOVA and free resources 785 * @dev: instance of PCI owned by the driver that's asking. 786 * @iova: IOVA of driver buffer previously mapped. 787 * @size: number of bytes mapped in driver buffer. 788 * @direction: R/W or both. 789 * 790 * See Documentation/DMA-API-HOWTO.txt 791 */ 792 static void 793 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 794 enum dma_data_direction direction) 795 { 796 struct ioc *ioc; 797 #if DELAYED_RESOURCE_CNT > 0 798 struct sba_dma_pair *d; 799 #endif 800 unsigned long flags; 801 dma_addr_t offset; 802 803 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); 804 805 ioc = GET_IOC(dev); 806 offset = iova & ~IOVP_MASK; 807 iova ^= offset; /* clear offset bits */ 808 size += offset; 809 size = ALIGN(size, IOVP_SIZE); 810 811 spin_lock_irqsave(&ioc->res_lock, flags); 812 813 #ifdef SBA_COLLECT_STATS 814 ioc->usingle_calls++; 815 ioc->usingle_pages += size >> IOVP_SHIFT; 816 #endif 817 818 sba_mark_invalid(ioc, iova, size); 819 820 #if DELAYED_RESOURCE_CNT > 0 821 /* Delaying when we re-use a IO Pdir entry reduces the number 822 * of MMIO reads needed to flush writes to the PCOM register. 823 */ 824 d = &(ioc->saved[ioc->saved_cnt]); 825 d->iova = iova; 826 d->size = size; 827 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 828 int cnt = ioc->saved_cnt; 829 while (cnt--) { 830 sba_free_range(ioc, d->iova, d->size); 831 d--; 832 } 833 ioc->saved_cnt = 0; 834 835 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 836 } 837 #else /* DELAYED_RESOURCE_CNT == 0 */ 838 sba_free_range(ioc, iova, size); 839 840 /* If fdc's were issued, force fdc's to be visible now */ 841 if (ioc_needs_fdc) 842 asm volatile("sync" : : ); 843 844 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 845 #endif /* DELAYED_RESOURCE_CNT == 0 */ 846 847 spin_unlock_irqrestore(&ioc->res_lock, flags); 848 849 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 850 ** For Astro based systems this isn't a big deal WRT performance. 851 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 852 ** we don't need the syncdma. The issue here is I/O MMU cachelines 853 ** are *not* coherent in all cases. May be hwrev dependent. 854 ** Need to investigate more. 855 asm volatile("syncdma"); 856 */ 857 } 858 859 860 /** 861 * sba_alloc_consistent - allocate/map shared mem for DMA 862 * @hwdev: instance of PCI owned by the driver that's asking. 863 * @size: number of bytes mapped in driver buffer. 864 * @dma_handle: IOVA of new buffer. 865 * 866 * See Documentation/DMA-API-HOWTO.txt 867 */ 868 static void *sba_alloc_consistent(struct device *hwdev, size_t size, 869 dma_addr_t *dma_handle, gfp_t gfp) 870 { 871 void *ret; 872 873 if (!hwdev) { 874 /* only support PCI */ 875 *dma_handle = 0; 876 return NULL; 877 } 878 879 ret = (void *) __get_free_pages(gfp, get_order(size)); 880 881 if (ret) { 882 memset(ret, 0, size); 883 *dma_handle = sba_map_single(hwdev, ret, size, 0); 884 } 885 886 return ret; 887 } 888 889 890 /** 891 * sba_free_consistent - free/unmap shared mem for DMA 892 * @hwdev: instance of PCI owned by the driver that's asking. 893 * @size: number of bytes mapped in driver buffer. 894 * @vaddr: virtual address IOVA of "consistent" buffer. 895 * @dma_handler: IO virtual address of "consistent" buffer. 896 * 897 * See Documentation/DMA-API-HOWTO.txt 898 */ 899 static void 900 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr, 901 dma_addr_t dma_handle) 902 { 903 sba_unmap_single(hwdev, dma_handle, size, 0); 904 free_pages((unsigned long) vaddr, get_order(size)); 905 } 906 907 908 /* 909 ** Since 0 is a valid pdir_base index value, can't use that 910 ** to determine if a value is valid or not. Use a flag to indicate 911 ** the SG list entry contains a valid pdir index. 912 */ 913 #define PIDE_FLAG 0x80000000UL 914 915 #ifdef SBA_COLLECT_STATS 916 #define IOMMU_MAP_STATS 917 #endif 918 #include "iommu-helpers.h" 919 920 #ifdef DEBUG_LARGE_SG_ENTRIES 921 int dump_run_sg = 0; 922 #endif 923 924 925 /** 926 * sba_map_sg - map Scatter/Gather list 927 * @dev: instance of PCI owned by the driver that's asking. 928 * @sglist: array of buffer/length pairs 929 * @nents: number of entries in list 930 * @direction: R/W or both. 931 * 932 * See Documentation/DMA-API-HOWTO.txt 933 */ 934 static int 935 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 936 enum dma_data_direction direction) 937 { 938 struct ioc *ioc; 939 int coalesced, filled = 0; 940 unsigned long flags; 941 942 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 943 944 ioc = GET_IOC(dev); 945 946 /* Fast path single entry scatterlists. */ 947 if (nents == 1) { 948 sg_dma_address(sglist) = sba_map_single(dev, 949 (void *)sg_virt_addr(sglist), 950 sglist->length, direction); 951 sg_dma_len(sglist) = sglist->length; 952 return 1; 953 } 954 955 spin_lock_irqsave(&ioc->res_lock, flags); 956 957 #ifdef ASSERT_PDIR_SANITY 958 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 959 { 960 sba_dump_sg(ioc, sglist, nents); 961 panic("Check before sba_map_sg()"); 962 } 963 #endif 964 965 #ifdef SBA_COLLECT_STATS 966 ioc->msg_calls++; 967 #endif 968 969 /* 970 ** First coalesce the chunks and allocate I/O pdir space 971 ** 972 ** If this is one DMA stream, we can properly map using the 973 ** correct virtual address associated with each DMA page. 974 ** w/o this association, we wouldn't have coherent DMA! 975 ** Access to the virtual address is what forces a two pass algorithm. 976 */ 977 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range); 978 979 /* 980 ** Program the I/O Pdir 981 ** 982 ** map the virtual addresses to the I/O Pdir 983 ** o dma_address will contain the pdir index 984 ** o dma_len will contain the number of bytes to map 985 ** o address contains the virtual address. 986 */ 987 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 988 989 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 990 if (ioc_needs_fdc) 991 asm volatile("sync" : : ); 992 993 #ifdef ASSERT_PDIR_SANITY 994 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 995 { 996 sba_dump_sg(ioc, sglist, nents); 997 panic("Check after sba_map_sg()\n"); 998 } 999 #endif 1000 1001 spin_unlock_irqrestore(&ioc->res_lock, flags); 1002 1003 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 1004 1005 return filled; 1006 } 1007 1008 1009 /** 1010 * sba_unmap_sg - unmap Scatter/Gather list 1011 * @dev: instance of PCI owned by the driver that's asking. 1012 * @sglist: array of buffer/length pairs 1013 * @nents: number of entries in list 1014 * @direction: R/W or both. 1015 * 1016 * See Documentation/DMA-API-HOWTO.txt 1017 */ 1018 static void 1019 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 1020 enum dma_data_direction direction) 1021 { 1022 struct ioc *ioc; 1023 #ifdef ASSERT_PDIR_SANITY 1024 unsigned long flags; 1025 #endif 1026 1027 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1028 __func__, nents, sg_virt_addr(sglist), sglist->length); 1029 1030 ioc = GET_IOC(dev); 1031 1032 #ifdef SBA_COLLECT_STATS 1033 ioc->usg_calls++; 1034 #endif 1035 1036 #ifdef ASSERT_PDIR_SANITY 1037 spin_lock_irqsave(&ioc->res_lock, flags); 1038 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1039 spin_unlock_irqrestore(&ioc->res_lock, flags); 1040 #endif 1041 1042 while (sg_dma_len(sglist) && nents--) { 1043 1044 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction); 1045 #ifdef SBA_COLLECT_STATS 1046 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1047 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1048 #endif 1049 ++sglist; 1050 } 1051 1052 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1053 1054 #ifdef ASSERT_PDIR_SANITY 1055 spin_lock_irqsave(&ioc->res_lock, flags); 1056 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1057 spin_unlock_irqrestore(&ioc->res_lock, flags); 1058 #endif 1059 1060 } 1061 1062 static struct hppa_dma_ops sba_ops = { 1063 .dma_supported = sba_dma_supported, 1064 .alloc_consistent = sba_alloc_consistent, 1065 .alloc_noncoherent = sba_alloc_consistent, 1066 .free_consistent = sba_free_consistent, 1067 .map_single = sba_map_single, 1068 .unmap_single = sba_unmap_single, 1069 .map_sg = sba_map_sg, 1070 .unmap_sg = sba_unmap_sg, 1071 .dma_sync_single_for_cpu = NULL, 1072 .dma_sync_single_for_device = NULL, 1073 .dma_sync_sg_for_cpu = NULL, 1074 .dma_sync_sg_for_device = NULL, 1075 }; 1076 1077 1078 /************************************************************************** 1079 ** 1080 ** SBA PAT PDC support 1081 ** 1082 ** o call pdc_pat_cell_module() 1083 ** o store ranges in PCI "resource" structures 1084 ** 1085 **************************************************************************/ 1086 1087 static void 1088 sba_get_pat_resources(struct sba_device *sba_dev) 1089 { 1090 #if 0 1091 /* 1092 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1093 ** PAT PDC to program the SBA/LBA directed range registers...this 1094 ** burden may fall on the LBA code since it directly supports the 1095 ** PCI subsystem. It's not clear yet. - ggg 1096 */ 1097 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1098 FIXME : ??? 1099 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1100 Tells where the dvi bits are located in the address. 1101 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1102 FIXME : ??? 1103 #endif 1104 } 1105 1106 1107 /************************************************************** 1108 * 1109 * Initialization and claim 1110 * 1111 ***************************************************************/ 1112 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1113 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1114 static void * 1115 sba_alloc_pdir(unsigned int pdir_size) 1116 { 1117 unsigned long pdir_base; 1118 unsigned long pdir_order = get_order(pdir_size); 1119 1120 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1121 if (NULL == (void *) pdir_base) { 1122 panic("%s() could not allocate I/O Page Table\n", 1123 __func__); 1124 } 1125 1126 /* If this is not PA8700 (PCX-W2) 1127 ** OR newer than ver 2.2 1128 ** OR in a system that doesn't need VINDEX bits from SBA, 1129 ** 1130 ** then we aren't exposed to the HW bug. 1131 */ 1132 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1133 || (boot_cpu_data.pdc.versions > 0x202) 1134 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1135 return (void *) pdir_base; 1136 1137 /* 1138 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1139 * 1140 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1141 * Ike/Astro can cause silent data corruption. This is only 1142 * a problem if the I/O PDIR is located in memory such that 1143 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1144 * 1145 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1146 * right physical address, we can either avoid (IOPDIR <= 1MB) 1147 * or minimize (2MB IO Pdir) the problem if we restrict the 1148 * IO Pdir to a maximum size of 2MB-128K (1902K). 1149 * 1150 * Because we always allocate 2^N sized IO pdirs, either of the 1151 * "bad" regions will be the last 128K if at all. That's easy 1152 * to test for. 1153 * 1154 */ 1155 if (pdir_order <= (19-12)) { 1156 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1157 /* allocate a new one on 512k alignment */ 1158 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1159 /* release original */ 1160 free_pages(pdir_base, pdir_order); 1161 1162 pdir_base = new_pdir; 1163 1164 /* release excess */ 1165 while (pdir_order < (19-12)) { 1166 new_pdir += pdir_size; 1167 free_pages(new_pdir, pdir_order); 1168 pdir_order +=1; 1169 pdir_size <<=1; 1170 } 1171 } 1172 } else { 1173 /* 1174 ** 1MB or 2MB Pdir 1175 ** Needs to be aligned on an "odd" 1MB boundary. 1176 */ 1177 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1178 1179 /* release original */ 1180 free_pages( pdir_base, pdir_order); 1181 1182 /* release first 1MB */ 1183 free_pages(new_pdir, 20-12); 1184 1185 pdir_base = new_pdir + 1024*1024; 1186 1187 if (pdir_order > (20-12)) { 1188 /* 1189 ** 2MB Pdir. 1190 ** 1191 ** Flag tells init_bitmap() to mark bad 128k as used 1192 ** and to reduce the size by 128k. 1193 */ 1194 piranha_bad_128k = 1; 1195 1196 new_pdir += 3*1024*1024; 1197 /* release last 1MB */ 1198 free_pages(new_pdir, 20-12); 1199 1200 /* release unusable 128KB */ 1201 free_pages(new_pdir - 128*1024 , 17-12); 1202 1203 pdir_size -= 128*1024; 1204 } 1205 } 1206 1207 memset((void *) pdir_base, 0, pdir_size); 1208 return (void *) pdir_base; 1209 } 1210 1211 struct ibase_data_struct { 1212 struct ioc *ioc; 1213 int ioc_num; 1214 }; 1215 1216 static int setup_ibase_imask_callback(struct device *dev, void *data) 1217 { 1218 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ 1219 extern void lba_set_iregs(struct parisc_device *, u32, u32); 1220 struct parisc_device *lba = to_parisc_device(dev); 1221 struct ibase_data_struct *ibd = data; 1222 int rope_num = (lba->hpa.start >> 13) & 0xf; 1223 if (rope_num >> 3 == ibd->ioc_num) 1224 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); 1225 return 0; 1226 } 1227 1228 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1229 static void 1230 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1231 { 1232 struct ibase_data_struct ibase_data = { 1233 .ioc = ioc, 1234 .ioc_num = ioc_num, 1235 }; 1236 1237 device_for_each_child(&sba->dev, &ibase_data, 1238 setup_ibase_imask_callback); 1239 } 1240 1241 #ifdef SBA_AGP_SUPPORT 1242 static int 1243 sba_ioc_find_quicksilver(struct device *dev, void *data) 1244 { 1245 int *agp_found = data; 1246 struct parisc_device *lba = to_parisc_device(dev); 1247 1248 if (IS_QUICKSILVER(lba)) 1249 *agp_found = 1; 1250 return 0; 1251 } 1252 #endif 1253 1254 static void 1255 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1256 { 1257 u32 iova_space_mask; 1258 u32 iova_space_size; 1259 int iov_order, tcnfg; 1260 #ifdef SBA_AGP_SUPPORT 1261 int agp_found = 0; 1262 #endif 1263 /* 1264 ** Firmware programs the base and size of a "safe IOVA space" 1265 ** (one that doesn't overlap memory or LMMIO space) in the 1266 ** IBASE and IMASK registers. 1267 */ 1268 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE); 1269 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1270 1271 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1272 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1273 iova_space_size /= 2; 1274 } 1275 1276 /* 1277 ** iov_order is always based on a 1GB IOVA space since we want to 1278 ** turn on the other half for AGP GART. 1279 */ 1280 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1281 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1282 1283 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1284 __func__, ioc->ioc_hpa, iova_space_size >> 20, 1285 iov_order + PAGE_SHIFT); 1286 1287 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1288 get_order(ioc->pdir_size)); 1289 if (!ioc->pdir_base) 1290 panic("Couldn't allocate I/O Page Table\n"); 1291 1292 memset(ioc->pdir_base, 0, ioc->pdir_size); 1293 1294 DBG_INIT("%s() pdir %p size %x\n", 1295 __func__, ioc->pdir_base, ioc->pdir_size); 1296 1297 #ifdef SBA_HINT_SUPPORT 1298 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1299 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1300 1301 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1302 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1303 #endif 1304 1305 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1306 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1307 1308 /* build IMASK for IOC and Elroy */ 1309 iova_space_mask = 0xffffffff; 1310 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1311 ioc->imask = iova_space_mask; 1312 #ifdef ZX1_SUPPORT 1313 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1314 #endif 1315 sba_dump_tlb(ioc->ioc_hpa); 1316 1317 setup_ibase_imask(sba, ioc, ioc_num); 1318 1319 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1320 1321 #ifdef CONFIG_64BIT 1322 /* 1323 ** Setting the upper bits makes checking for bypass addresses 1324 ** a little faster later on. 1325 */ 1326 ioc->imask |= 0xFFFFFFFF00000000UL; 1327 #endif 1328 1329 /* Set I/O PDIR Page size to system page size */ 1330 switch (PAGE_SHIFT) { 1331 case 12: tcnfg = 0; break; /* 4K */ 1332 case 13: tcnfg = 1; break; /* 8K */ 1333 case 14: tcnfg = 2; break; /* 16K */ 1334 case 16: tcnfg = 3; break; /* 64K */ 1335 default: 1336 panic(__FILE__ "Unsupported system page size %d", 1337 1 << PAGE_SHIFT); 1338 break; 1339 } 1340 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1341 1342 /* 1343 ** Program the IOC's ibase and enable IOVA translation 1344 ** Bit zero == enable bit. 1345 */ 1346 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1347 1348 /* 1349 ** Clear I/O TLB of any possible entries. 1350 ** (Yes. This is a bit paranoid...but so what) 1351 */ 1352 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1353 1354 #ifdef SBA_AGP_SUPPORT 1355 1356 /* 1357 ** If an AGP device is present, only use half of the IOV space 1358 ** for PCI DMA. Unfortunately we can't know ahead of time 1359 ** whether GART support will actually be used, for now we 1360 ** can just key on any AGP device found in the system. 1361 ** We program the next pdir index after we stop w/ a key for 1362 ** the GART code to handshake on. 1363 */ 1364 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); 1365 1366 if (agp_found && sba_reserve_agpgart) { 1367 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", 1368 __func__, (iova_space_size/2) >> 20); 1369 ioc->pdir_size /= 2; 1370 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; 1371 } 1372 #endif /*SBA_AGP_SUPPORT*/ 1373 } 1374 1375 static void 1376 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1377 { 1378 u32 iova_space_size, iova_space_mask; 1379 unsigned int pdir_size, iov_order; 1380 1381 /* 1382 ** Determine IOVA Space size from memory size. 1383 ** 1384 ** Ideally, PCI drivers would register the maximum number 1385 ** of DMA they can have outstanding for each device they 1386 ** own. Next best thing would be to guess how much DMA 1387 ** can be outstanding based on PCI Class/sub-class. Both 1388 ** methods still require some "extra" to support PCI 1389 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1390 ** 1391 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1392 ** for DMA hints - ergo only 30 bits max. 1393 */ 1394 1395 iova_space_size = (u32) (totalram_pages/global_ioc_cnt); 1396 1397 /* limit IOVA space size to 1MB-1GB */ 1398 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1399 iova_space_size = 1 << (20 - PAGE_SHIFT); 1400 } 1401 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1402 iova_space_size = 1 << (30 - PAGE_SHIFT); 1403 } 1404 1405 /* 1406 ** iova space must be log2() in size. 1407 ** thus, pdir/res_map will also be log2(). 1408 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1409 */ 1410 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1411 1412 /* iova_space_size is now bytes, not pages */ 1413 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1414 1415 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1416 1417 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", 1418 __func__, 1419 ioc->ioc_hpa, 1420 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT), 1421 iova_space_size>>20, 1422 iov_order + PAGE_SHIFT); 1423 1424 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1425 1426 DBG_INIT("%s() pdir %p size %x\n", 1427 __func__, ioc->pdir_base, pdir_size); 1428 1429 #ifdef SBA_HINT_SUPPORT 1430 /* FIXME : DMA HINTs not used */ 1431 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1432 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1433 1434 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1435 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1436 #endif 1437 1438 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1439 1440 /* build IMASK for IOC and Elroy */ 1441 iova_space_mask = 0xffffffff; 1442 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1443 1444 /* 1445 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1446 ** ibase=0, imask=0xFE000000, size=0x2000000. 1447 */ 1448 ioc->ibase = 0; 1449 ioc->imask = iova_space_mask; /* save it */ 1450 #ifdef ZX1_SUPPORT 1451 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1452 #endif 1453 1454 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", 1455 __func__, ioc->ibase, ioc->imask); 1456 1457 /* 1458 ** FIXME: Hint registers are programmed with default hint 1459 ** values during boot, so hints should be sane even if we 1460 ** can't reprogram them the way drivers want. 1461 */ 1462 1463 setup_ibase_imask(sba, ioc, ioc_num); 1464 1465 /* 1466 ** Program the IOC's ibase and enable IOVA translation 1467 */ 1468 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1469 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1470 1471 /* Set I/O PDIR Page size to 4K */ 1472 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG); 1473 1474 /* 1475 ** Clear I/O TLB of any possible entries. 1476 ** (Yes. This is a bit paranoid...but so what) 1477 */ 1478 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1479 1480 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1481 1482 DBG_INIT("%s() DONE\n", __func__); 1483 } 1484 1485 1486 1487 /************************************************************************** 1488 ** 1489 ** SBA initialization code (HW and SW) 1490 ** 1491 ** o identify SBA chip itself 1492 ** o initialize SBA chip modes (HardFail) 1493 ** o initialize SBA chip modes (HardFail) 1494 ** o FIXME: initialize DMA hints for reasonable defaults 1495 ** 1496 **************************************************************************/ 1497 1498 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1499 { 1500 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1501 } 1502 1503 static void sba_hw_init(struct sba_device *sba_dev) 1504 { 1505 int i; 1506 int num_ioc; 1507 u64 ioc_ctl; 1508 1509 if (!is_pdc_pat()) { 1510 /* Shutdown the USB controller on Astro-based workstations. 1511 ** Once we reprogram the IOMMU, the next DMA performed by 1512 ** USB will HPMC the box. USB is only enabled if a 1513 ** keyboard is present and found. 1514 ** 1515 ** With serial console, j6k v5.0 firmware says: 1516 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1517 ** 1518 ** FIXME: Using GFX+USB console at power up but direct 1519 ** linux to serial console is still broken. 1520 ** USB could generate DMA so we must reset USB. 1521 ** The proper sequence would be: 1522 ** o block console output 1523 ** o reset USB device 1524 ** o reprogram serial port 1525 ** o unblock console output 1526 */ 1527 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1528 pdc_io_reset_devices(); 1529 } 1530 1531 } 1532 1533 1534 #if 0 1535 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1536 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1537 1538 /* 1539 ** Need to deal with DMA from LAN. 1540 ** Maybe use page zero boot device as a handle to talk 1541 ** to PDC about which device to shutdown. 1542 ** 1543 ** Netbooting, j6k v5.0 firmware says: 1544 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1545 ** ARGH! invalid class. 1546 */ 1547 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1548 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1549 pdc_io_reset(); 1550 } 1551 #endif 1552 1553 if (!IS_PLUTO(sba_dev->dev)) { 1554 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1555 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", 1556 __func__, sba_dev->sba_hpa, ioc_ctl); 1557 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1558 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1559 /* j6700 v1.6 firmware sets 0x294f */ 1560 /* A500 firmware sets 0x4d */ 1561 1562 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1563 1564 #ifdef DEBUG_SBA_INIT 1565 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1566 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1567 #endif 1568 } /* if !PLUTO */ 1569 1570 if (IS_ASTRO(sba_dev->dev)) { 1571 int err; 1572 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1573 num_ioc = 1; 1574 1575 sba_dev->chip_resv.name = "Astro Intr Ack"; 1576 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1577 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1578 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1579 BUG_ON(err < 0); 1580 1581 } else if (IS_PLUTO(sba_dev->dev)) { 1582 int err; 1583 1584 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1585 num_ioc = 1; 1586 1587 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1588 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1589 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1590 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1591 WARN_ON(err < 0); 1592 1593 sba_dev->iommu_resv.name = "IOVA Space"; 1594 sba_dev->iommu_resv.start = 0x40000000UL; 1595 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1596 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1597 WARN_ON(err < 0); 1598 } else { 1599 /* IKE, REO */ 1600 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1601 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1602 num_ioc = 2; 1603 1604 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1605 } 1606 /* XXX: What about Reo Grande? */ 1607 1608 sba_dev->num_ioc = num_ioc; 1609 for (i = 0; i < num_ioc; i++) { 1610 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1611 unsigned int j; 1612 1613 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1614 1615 /* 1616 * Clear ROPE(N)_CONFIG AO bit. 1617 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1618 * Overrides bit 1 in DMA Hint Sets. 1619 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1620 */ 1621 if (IS_PLUTO(sba_dev->dev)) { 1622 void __iomem *rope_cfg; 1623 unsigned long cfg_val; 1624 1625 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1626 cfg_val = READ_REG(rope_cfg); 1627 cfg_val &= ~IOC_ROPE_AO; 1628 WRITE_REG(cfg_val, rope_cfg); 1629 } 1630 1631 /* 1632 ** Make sure the box crashes on rope errors. 1633 */ 1634 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1635 } 1636 1637 /* flush out the last writes */ 1638 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1639 1640 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", 1641 i, 1642 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1643 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1644 ); 1645 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", 1646 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1647 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1648 ); 1649 1650 if (IS_PLUTO(sba_dev->dev)) { 1651 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1652 } else { 1653 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1654 } 1655 } 1656 } 1657 1658 static void 1659 sba_common_init(struct sba_device *sba_dev) 1660 { 1661 int i; 1662 1663 /* add this one to the head of the list (order doesn't matter) 1664 ** This will be useful for debugging - especially if we get coredumps 1665 */ 1666 sba_dev->next = sba_list; 1667 sba_list = sba_dev; 1668 1669 for(i=0; i< sba_dev->num_ioc; i++) { 1670 int res_size; 1671 #ifdef DEBUG_DMB_TRAP 1672 extern void iterate_pages(unsigned long , unsigned long , 1673 void (*)(pte_t * , unsigned long), 1674 unsigned long ); 1675 void set_data_memory_break(pte_t * , unsigned long); 1676 #endif 1677 /* resource map size dictated by pdir_size */ 1678 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1679 1680 /* Second part of PIRANHA BUG */ 1681 if (piranha_bad_128k) { 1682 res_size -= (128*1024)/sizeof(u64); 1683 } 1684 1685 res_size >>= 3; /* convert bit count to byte count */ 1686 DBG_INIT("%s() res_size 0x%x\n", 1687 __func__, res_size); 1688 1689 sba_dev->ioc[i].res_size = res_size; 1690 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1691 1692 #ifdef DEBUG_DMB_TRAP 1693 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1694 set_data_memory_break, 0); 1695 #endif 1696 1697 if (NULL == sba_dev->ioc[i].res_map) 1698 { 1699 panic("%s:%s() could not allocate resource map\n", 1700 __FILE__, __func__ ); 1701 } 1702 1703 memset(sba_dev->ioc[i].res_map, 0, res_size); 1704 /* next available IOVP - circular search */ 1705 sba_dev->ioc[i].res_hint = (unsigned long *) 1706 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1707 1708 #ifdef ASSERT_PDIR_SANITY 1709 /* Mark first bit busy - ie no IOVA 0 */ 1710 sba_dev->ioc[i].res_map[0] = 0x80; 1711 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; 1712 #endif 1713 1714 /* Third (and last) part of PIRANHA BUG */ 1715 if (piranha_bad_128k) { 1716 /* region from +1408K to +1536 is un-usable. */ 1717 1718 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1719 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1720 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1721 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1722 1723 /* mark that part of the io pdir busy */ 1724 while (p_start < p_end) 1725 *p_start++ = -1; 1726 1727 } 1728 1729 #ifdef DEBUG_DMB_TRAP 1730 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1731 set_data_memory_break, 0); 1732 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1733 set_data_memory_break, 0); 1734 #endif 1735 1736 DBG_INIT("%s() %d res_map %x %p\n", 1737 __func__, i, res_size, sba_dev->ioc[i].res_map); 1738 } 1739 1740 spin_lock_init(&sba_dev->sba_lock); 1741 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1742 1743 #ifdef DEBUG_SBA_INIT 1744 /* 1745 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1746 * (bit #61, big endian), we have to flush and sync every time 1747 * IO-PDIR is changed in Ike/Astro. 1748 */ 1749 if (ioc_needs_fdc) { 1750 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1751 } else { 1752 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1753 } 1754 #endif 1755 } 1756 1757 #ifdef CONFIG_PROC_FS 1758 static int sba_proc_info(struct seq_file *m, void *p) 1759 { 1760 struct sba_device *sba_dev = sba_list; 1761 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1762 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1763 #ifdef SBA_COLLECT_STATS 1764 unsigned long avg = 0, min, max; 1765 #endif 1766 int i, len = 0; 1767 1768 len += seq_printf(m, "%s rev %d.%d\n", 1769 sba_dev->name, 1770 (sba_dev->hw_rev & 0x7) + 1, 1771 (sba_dev->hw_rev & 0x18) >> 3 1772 ); 1773 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1774 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1775 total_pages); 1776 1777 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1778 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1779 1780 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1781 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1782 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1783 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE) 1784 ); 1785 1786 for (i=0; i<4; i++) 1787 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i, 1788 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1789 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1790 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18) 1791 ); 1792 1793 #ifdef SBA_COLLECT_STATS 1794 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1795 total_pages - ioc->used_pages, ioc->used_pages, 1796 (int) (ioc->used_pages * 100 / total_pages)); 1797 1798 min = max = ioc->avg_search[0]; 1799 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1800 avg += ioc->avg_search[i]; 1801 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1802 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1803 } 1804 avg /= SBA_SEARCH_SAMPLE; 1805 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1806 min, avg, max); 1807 1808 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1809 ioc->msingle_calls, ioc->msingle_pages, 1810 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1811 1812 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1813 min = ioc->usingle_calls; 1814 max = ioc->usingle_pages - ioc->usg_pages; 1815 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1816 min, max, (int) ((max * 1000)/min)); 1817 1818 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1819 ioc->msg_calls, ioc->msg_pages, 1820 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls)); 1821 1822 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1823 ioc->usg_calls, ioc->usg_pages, 1824 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls)); 1825 #endif 1826 1827 return 0; 1828 } 1829 1830 static int 1831 sba_proc_open(struct inode *i, struct file *f) 1832 { 1833 return single_open(f, &sba_proc_info, NULL); 1834 } 1835 1836 static const struct file_operations sba_proc_fops = { 1837 .owner = THIS_MODULE, 1838 .open = sba_proc_open, 1839 .read = seq_read, 1840 .llseek = seq_lseek, 1841 .release = single_release, 1842 }; 1843 1844 static int 1845 sba_proc_bitmap_info(struct seq_file *m, void *p) 1846 { 1847 struct sba_device *sba_dev = sba_list; 1848 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1849 unsigned int *res_ptr = (unsigned int *)ioc->res_map; 1850 int i, len = 0; 1851 1852 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) { 1853 if ((i & 7) == 0) 1854 len += seq_printf(m, "\n "); 1855 len += seq_printf(m, " %08x", *res_ptr); 1856 } 1857 len += seq_printf(m, "\n"); 1858 1859 return 0; 1860 } 1861 1862 static int 1863 sba_proc_bitmap_open(struct inode *i, struct file *f) 1864 { 1865 return single_open(f, &sba_proc_bitmap_info, NULL); 1866 } 1867 1868 static const struct file_operations sba_proc_bitmap_fops = { 1869 .owner = THIS_MODULE, 1870 .open = sba_proc_bitmap_open, 1871 .read = seq_read, 1872 .llseek = seq_lseek, 1873 .release = single_release, 1874 }; 1875 #endif /* CONFIG_PROC_FS */ 1876 1877 static struct parisc_device_id sba_tbl[] = { 1878 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1879 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1880 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1881 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1882 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1883 { 0, } 1884 }; 1885 1886 static int sba_driver_callback(struct parisc_device *); 1887 1888 static struct parisc_driver sba_driver = { 1889 .name = MODULE_NAME, 1890 .id_table = sba_tbl, 1891 .probe = sba_driver_callback, 1892 }; 1893 1894 /* 1895 ** Determine if sba should claim this chip (return 0) or not (return 1). 1896 ** If so, initialize the chip and tell other partners in crime they 1897 ** have work to do. 1898 */ 1899 static int sba_driver_callback(struct parisc_device *dev) 1900 { 1901 struct sba_device *sba_dev; 1902 u32 func_class; 1903 int i; 1904 char *version; 1905 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE); 1906 #ifdef CONFIG_PROC_FS 1907 struct proc_dir_entry *root; 1908 #endif 1909 1910 sba_dump_ranges(sba_addr); 1911 1912 /* Read HW Rev First */ 1913 func_class = READ_REG(sba_addr + SBA_FCLASS); 1914 1915 if (IS_ASTRO(dev)) { 1916 unsigned long fclass; 1917 static char astro_rev[]="Astro ?.?"; 1918 1919 /* Astro is broken...Read HW Rev First */ 1920 fclass = READ_REG(sba_addr); 1921 1922 astro_rev[6] = '1' + (char) (fclass & 0x7); 1923 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1924 version = astro_rev; 1925 1926 } else if (IS_IKE(dev)) { 1927 static char ike_rev[] = "Ike rev ?"; 1928 ike_rev[8] = '0' + (char) (func_class & 0xff); 1929 version = ike_rev; 1930 } else if (IS_PLUTO(dev)) { 1931 static char pluto_rev[]="Pluto ?.?"; 1932 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1933 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1934 version = pluto_rev; 1935 } else { 1936 static char reo_rev[] = "REO rev ?"; 1937 reo_rev[8] = '0' + (char) (func_class & 0xff); 1938 version = reo_rev; 1939 } 1940 1941 if (!global_ioc_cnt) { 1942 global_ioc_cnt = count_parisc_driver(&sba_driver); 1943 1944 /* Astro and Pluto have one IOC per SBA */ 1945 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1946 global_ioc_cnt *= 2; 1947 } 1948 1949 printk(KERN_INFO "%s found %s at 0x%llx\n", 1950 MODULE_NAME, version, (unsigned long long)dev->hpa.start); 1951 1952 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 1953 if (!sba_dev) { 1954 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1955 return -ENOMEM; 1956 } 1957 1958 parisc_set_drvdata(dev, sba_dev); 1959 1960 for(i=0; i<MAX_IOC; i++) 1961 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1962 1963 sba_dev->dev = dev; 1964 sba_dev->hw_rev = func_class; 1965 sba_dev->name = dev->name; 1966 sba_dev->sba_hpa = sba_addr; 1967 1968 sba_get_pat_resources(sba_dev); 1969 sba_hw_init(sba_dev); 1970 sba_common_init(sba_dev); 1971 1972 hppa_dma_ops = &sba_ops; 1973 1974 #ifdef CONFIG_PROC_FS 1975 switch (dev->id.hversion) { 1976 case PLUTO_MCKINLEY_PORT: 1977 root = proc_mckinley_root; 1978 break; 1979 case ASTRO_RUNWAY_PORT: 1980 case IKE_MERCED_PORT: 1981 default: 1982 root = proc_runway_root; 1983 break; 1984 } 1985 1986 proc_create("sba_iommu", 0, root, &sba_proc_fops); 1987 proc_create("sba_iommu-bitmap", 0, root, &sba_proc_bitmap_fops); 1988 #endif 1989 1990 parisc_has_iommu(); 1991 return 0; 1992 } 1993 1994 /* 1995 ** One time initialization to let the world know the SBA was found. 1996 ** This is the only routine which is NOT static. 1997 ** Must be called exactly once before pci_init(). 1998 */ 1999 void __init sba_init(void) 2000 { 2001 register_parisc_driver(&sba_driver); 2002 } 2003 2004 2005 /** 2006 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 2007 * @dev: The parisc device. 2008 * 2009 * Returns the appropriate IOMMU data for the given parisc PCI controller. 2010 * This is cached and used later for PCI DMA Mapping. 2011 */ 2012 void * sba_get_iommu(struct parisc_device *pci_hba) 2013 { 2014 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2015 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2016 char t = sba_dev->id.hw_type; 2017 int iocnum = (pci_hba->hw_path >> 3); /* rope # */ 2018 2019 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 2020 2021 return &(sba->ioc[iocnum]); 2022 } 2023 2024 2025 /** 2026 * sba_directed_lmmio - return first directed LMMIO range routed to rope 2027 * @pa_dev: The parisc device. 2028 * @r: resource PCI host controller wants start/end fields assigned. 2029 * 2030 * For the given parisc PCI controller, determine if any direct ranges 2031 * are routed down the corresponding rope. 2032 */ 2033 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2034 { 2035 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2036 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2037 char t = sba_dev->id.hw_type; 2038 int i; 2039 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2040 2041 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2042 2043 r->start = r->end = 0; 2044 2045 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2046 for (i=0; i<4; i++) { 2047 int base, size; 2048 void __iomem *reg = sba->sba_hpa + i*0x18; 2049 2050 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2051 if ((base & 1) == 0) 2052 continue; /* not enabled */ 2053 2054 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2055 2056 if ((size & (ROPES_PER_IOC-1)) != rope) 2057 continue; /* directed down different rope */ 2058 2059 r->start = (base & ~1UL) | PCI_F_EXTEND; 2060 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2061 r->end = r->start + size; 2062 r->flags = IORESOURCE_MEM; 2063 } 2064 } 2065 2066 2067 /** 2068 * sba_distributed_lmmio - return portion of distributed LMMIO range 2069 * @pa_dev: The parisc device. 2070 * @r: resource PCI host controller wants start/end fields assigned. 2071 * 2072 * For the given parisc PCI controller, return portion of distributed LMMIO 2073 * range. The distributed LMMIO is always present and it's just a question 2074 * of the base address and size of the range. 2075 */ 2076 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2077 { 2078 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2079 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2080 char t = sba_dev->id.hw_type; 2081 int base, size; 2082 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2083 2084 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2085 2086 r->start = r->end = 0; 2087 2088 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2089 if ((base & 1) == 0) { 2090 BUG(); /* Gah! Distr Range wasn't enabled! */ 2091 return; 2092 } 2093 2094 r->start = (base & ~1UL) | PCI_F_EXTEND; 2095 2096 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2097 r->start += rope * (size + 1); /* adjust base for this rope */ 2098 r->end = r->start + size; 2099 r->flags = IORESOURCE_MEM; 2100 } 2101