1 /* 2 ** System Bus Adapter (SBA) I/O MMU manager 3 ** 4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 6 ** (c) Copyright 2000-2004 Hewlett-Packard Company 7 ** 8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 17 ** J5000/J7000/N-class/L-class machines and their successors. 18 ** 19 ** FIXME: add DMA hint support programming in both sba and lba modules. 20 */ 21 22 #include <linux/types.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/slab.h> 26 #include <linux/init.h> 27 28 #include <linux/mm.h> 29 #include <linux/string.h> 30 #include <linux/pci.h> 31 32 #include <asm/byteorder.h> 33 #include <asm/io.h> 34 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 35 36 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 37 38 #include <linux/proc_fs.h> 39 #include <linux/seq_file.h> 40 41 #include <asm/ropes.h> 42 #include <asm/mckinley.h> /* for proc_mckinley_root */ 43 #include <asm/runway.h> /* for proc_runway_root */ 44 #include <asm/pdc.h> /* for PDC_MODEL_* */ 45 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 46 #include <asm/parisc-device.h> 47 48 #define MODULE_NAME "SBA" 49 50 /* 51 ** The number of debug flags is a clue - this code is fragile. 52 ** Don't even think about messing with it unless you have 53 ** plenty of 710's to sacrifice to the computer gods. :^) 54 */ 55 #undef DEBUG_SBA_INIT 56 #undef DEBUG_SBA_RUN 57 #undef DEBUG_SBA_RUN_SG 58 #undef DEBUG_SBA_RESOURCE 59 #undef ASSERT_PDIR_SANITY 60 #undef DEBUG_LARGE_SG_ENTRIES 61 #undef DEBUG_DMB_TRAP 62 63 #ifdef DEBUG_SBA_INIT 64 #define DBG_INIT(x...) printk(x) 65 #else 66 #define DBG_INIT(x...) 67 #endif 68 69 #ifdef DEBUG_SBA_RUN 70 #define DBG_RUN(x...) printk(x) 71 #else 72 #define DBG_RUN(x...) 73 #endif 74 75 #ifdef DEBUG_SBA_RUN_SG 76 #define DBG_RUN_SG(x...) printk(x) 77 #else 78 #define DBG_RUN_SG(x...) 79 #endif 80 81 82 #ifdef DEBUG_SBA_RESOURCE 83 #define DBG_RES(x...) printk(x) 84 #else 85 #define DBG_RES(x...) 86 #endif 87 88 #define SBA_INLINE __inline__ 89 90 #define DEFAULT_DMA_HINT_REG 0 91 92 struct sba_device *sba_list; 93 EXPORT_SYMBOL_GPL(sba_list); 94 95 static unsigned long ioc_needs_fdc = 0; 96 97 /* global count of IOMMUs in the system */ 98 static unsigned int global_ioc_cnt = 0; 99 100 /* PA8700 (Piranha 2.2) bug workaround */ 101 static unsigned long piranha_bad_128k = 0; 102 103 /* Looks nice and keeps the compiler happy */ 104 #define SBA_DEV(d) ((struct sba_device *) (d)) 105 106 #ifdef CONFIG_AGP_PARISC 107 #define SBA_AGP_SUPPORT 108 #endif /*CONFIG_AGP_PARISC*/ 109 110 #ifdef SBA_AGP_SUPPORT 111 static int sba_reserve_agpgart = 1; 112 module_param(sba_reserve_agpgart, int, 0444); 113 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); 114 #endif 115 116 117 /************************************ 118 ** SBA register read and write support 119 ** 120 ** BE WARNED: register writes are posted. 121 ** (ie follow writes which must reach HW with a read) 122 ** 123 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 124 */ 125 #define READ_REG32(addr) readl(addr) 126 #define READ_REG64(addr) readq(addr) 127 #define WRITE_REG32(val, addr) writel((val), (addr)) 128 #define WRITE_REG64(val, addr) writeq((val), (addr)) 129 130 #ifdef CONFIG_64BIT 131 #define READ_REG(addr) READ_REG64(addr) 132 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 133 #else 134 #define READ_REG(addr) READ_REG32(addr) 135 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 136 #endif 137 138 #ifdef DEBUG_SBA_INIT 139 140 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 141 142 /** 143 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 144 * @hpa: base address of the sba 145 * 146 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 147 * IO Adapter (aka Bus Converter). 148 */ 149 static void 150 sba_dump_ranges(void __iomem *hpa) 151 { 152 DBG_INIT("SBA at 0x%p\n", hpa); 153 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 154 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 155 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 156 DBG_INIT("\n"); 157 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 158 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 159 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 160 } 161 162 /** 163 * sba_dump_tlb - debugging only - print IOMMU operating parameters 164 * @hpa: base address of the IOMMU 165 * 166 * Print the size/location of the IO MMU PDIR. 167 */ 168 static void sba_dump_tlb(void __iomem *hpa) 169 { 170 DBG_INIT("IO TLB at 0x%p\n", hpa); 171 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 172 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 173 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 174 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 175 DBG_INIT("\n"); 176 } 177 #else 178 #define sba_dump_ranges(x) 179 #define sba_dump_tlb(x) 180 #endif /* DEBUG_SBA_INIT */ 181 182 183 #ifdef ASSERT_PDIR_SANITY 184 185 /** 186 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 187 * @ioc: IO MMU structure which owns the pdir we are interested in. 188 * @msg: text to print ont the output line. 189 * @pide: pdir index. 190 * 191 * Print one entry of the IO MMU PDIR in human readable form. 192 */ 193 static void 194 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 195 { 196 /* start printing from lowest pde in rval */ 197 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 198 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 199 uint rcnt; 200 201 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 202 msg, 203 rptr, pide & (BITS_PER_LONG - 1), *rptr); 204 205 rcnt = 0; 206 while (rcnt < BITS_PER_LONG) { 207 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 208 (rcnt == (pide & (BITS_PER_LONG - 1))) 209 ? " -->" : " ", 210 rcnt, ptr, *ptr ); 211 rcnt++; 212 ptr++; 213 } 214 printk(KERN_DEBUG "%s", msg); 215 } 216 217 218 /** 219 * sba_check_pdir - debugging only - consistency checker 220 * @ioc: IO MMU structure which owns the pdir we are interested in. 221 * @msg: text to print ont the output line. 222 * 223 * Verify the resource map and pdir state is consistent 224 */ 225 static int 226 sba_check_pdir(struct ioc *ioc, char *msg) 227 { 228 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 229 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 230 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 231 uint pide = 0; 232 233 while (rptr < rptr_end) { 234 u32 rval = *rptr; 235 int rcnt = 32; /* number of bits we might check */ 236 237 while (rcnt) { 238 /* Get last byte and highest bit from that */ 239 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 240 if ((rval ^ pde) & 0x80000000) 241 { 242 /* 243 ** BUMMER! -- res_map != pdir -- 244 ** Dump rval and matching pdir entries 245 */ 246 sba_dump_pdir_entry(ioc, msg, pide); 247 return(1); 248 } 249 rcnt--; 250 rval <<= 1; /* try the next bit */ 251 pptr++; 252 pide++; 253 } 254 rptr++; /* look at next word of res_map */ 255 } 256 /* It'd be nice if we always got here :^) */ 257 return 0; 258 } 259 260 261 /** 262 * sba_dump_sg - debugging only - print Scatter-Gather list 263 * @ioc: IO MMU structure which owns the pdir we are interested in. 264 * @startsg: head of the SG list 265 * @nents: number of entries in SG list 266 * 267 * print the SG list so we can verify it's correct by hand. 268 */ 269 static void 270 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 271 { 272 while (nents-- > 0) { 273 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 274 nents, 275 (unsigned long) sg_dma_address(startsg), 276 sg_dma_len(startsg), 277 sg_virt_addr(startsg), startsg->length); 278 startsg++; 279 } 280 } 281 282 #endif /* ASSERT_PDIR_SANITY */ 283 284 285 286 287 /************************************************************** 288 * 289 * I/O Pdir Resource Management 290 * 291 * Bits set in the resource map are in use. 292 * Each bit can represent a number of pages. 293 * LSbs represent lower addresses (IOVA's). 294 * 295 ***************************************************************/ 296 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 297 298 /* Convert from IOVP to IOVA and vice versa. */ 299 300 #ifdef ZX1_SUPPORT 301 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 302 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 303 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 304 #else 305 /* only support Astro and ancestors. Saves a few cycles in key places */ 306 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 307 #define SBA_IOVP(ioc,iova) (iova) 308 #endif 309 310 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 311 312 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 313 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 314 315 316 /** 317 * sba_search_bitmap - find free space in IO PDIR resource bitmap 318 * @ioc: IO MMU structure which owns the pdir we are interested in. 319 * @bits_wanted: number of entries we need. 320 * 321 * Find consecutive free bits in resource bitmap. 322 * Each bit represents one entry in the IO Pdir. 323 * Cool perf optimization: search for log2(size) bits at a time. 324 */ 325 static SBA_INLINE unsigned long 326 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted) 327 { 328 unsigned long *res_ptr = ioc->res_hint; 329 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 330 unsigned long pide = ~0UL; 331 332 if (bits_wanted > (BITS_PER_LONG/2)) { 333 /* Search word at a time - no mask needed */ 334 for(; res_ptr < res_end; ++res_ptr) { 335 if (*res_ptr == 0) { 336 *res_ptr = RESMAP_MASK(bits_wanted); 337 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map); 338 pide <<= 3; /* convert to bit address */ 339 break; 340 } 341 } 342 /* point to the next word on next pass */ 343 res_ptr++; 344 ioc->res_bitshift = 0; 345 } else { 346 /* 347 ** Search the resource bit map on well-aligned values. 348 ** "o" is the alignment. 349 ** We need the alignment to invalidate I/O TLB using 350 ** SBA HW features in the unmap path. 351 */ 352 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 353 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); 354 unsigned long mask; 355 356 if (bitshiftcnt >= BITS_PER_LONG) { 357 bitshiftcnt = 0; 358 res_ptr++; 359 } 360 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 361 362 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr); 363 while(res_ptr < res_end) 364 { 365 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 366 WARN_ON(mask == 0); 367 if(((*res_ptr) & mask) == 0) { 368 *res_ptr |= mask; /* mark resources busy! */ 369 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map); 370 pide <<= 3; /* convert to bit address */ 371 pide += bitshiftcnt; 372 break; 373 } 374 mask >>= o; 375 bitshiftcnt += o; 376 if (mask == 0) { 377 mask = RESMAP_MASK(bits_wanted); 378 bitshiftcnt=0; 379 res_ptr++; 380 } 381 } 382 /* look in the same word on the next pass */ 383 ioc->res_bitshift = bitshiftcnt + bits_wanted; 384 } 385 386 /* wrapped ? */ 387 if (res_end <= res_ptr) { 388 ioc->res_hint = (unsigned long *) ioc->res_map; 389 ioc->res_bitshift = 0; 390 } else { 391 ioc->res_hint = res_ptr; 392 } 393 return (pide); 394 } 395 396 397 /** 398 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 399 * @ioc: IO MMU structure which owns the pdir we are interested in. 400 * @size: number of bytes to create a mapping for 401 * 402 * Given a size, find consecutive unmarked and then mark those bits in the 403 * resource bit map. 404 */ 405 static int 406 sba_alloc_range(struct ioc *ioc, size_t size) 407 { 408 unsigned int pages_needed = size >> IOVP_SHIFT; 409 #ifdef SBA_COLLECT_STATS 410 unsigned long cr_start = mfctl(16); 411 #endif 412 unsigned long pide; 413 414 pide = sba_search_bitmap(ioc, pages_needed); 415 if (pide >= (ioc->res_size << 3)) { 416 pide = sba_search_bitmap(ioc, pages_needed); 417 if (pide >= (ioc->res_size << 3)) 418 panic("%s: I/O MMU @ %p is out of mapping resources\n", 419 __FILE__, ioc->ioc_hpa); 420 } 421 422 #ifdef ASSERT_PDIR_SANITY 423 /* verify the first enable bit is clear */ 424 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 425 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 426 } 427 #endif 428 429 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 430 __FUNCTION__, size, pages_needed, pide, 431 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 432 ioc->res_bitshift ); 433 434 #ifdef SBA_COLLECT_STATS 435 { 436 unsigned long cr_end = mfctl(16); 437 unsigned long tmp = cr_end - cr_start; 438 /* check for roll over */ 439 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 440 } 441 ioc->avg_search[ioc->avg_idx++] = cr_start; 442 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 443 444 ioc->used_pages += pages_needed; 445 #endif 446 447 return (pide); 448 } 449 450 451 /** 452 * sba_free_range - unmark bits in IO PDIR resource bitmap 453 * @ioc: IO MMU structure which owns the pdir we are interested in. 454 * @iova: IO virtual address which was previously allocated. 455 * @size: number of bytes to create a mapping for 456 * 457 * clear bits in the ioc's resource map 458 */ 459 static SBA_INLINE void 460 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 461 { 462 unsigned long iovp = SBA_IOVP(ioc, iova); 463 unsigned int pide = PDIR_INDEX(iovp); 464 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 465 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 466 467 int bits_not_wanted = size >> IOVP_SHIFT; 468 469 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 470 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 471 472 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 473 __FUNCTION__, (uint) iova, size, 474 bits_not_wanted, m, pide, res_ptr, *res_ptr); 475 476 #ifdef SBA_COLLECT_STATS 477 ioc->used_pages -= bits_not_wanted; 478 #endif 479 480 *res_ptr &= ~m; 481 } 482 483 484 /************************************************************** 485 * 486 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 487 * 488 ***************************************************************/ 489 490 #ifdef SBA_HINT_SUPPORT 491 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 492 #endif 493 494 typedef unsigned long space_t; 495 #define KERNEL_SPACE 0 496 497 /** 498 * sba_io_pdir_entry - fill in one IO PDIR entry 499 * @pdir_ptr: pointer to IO PDIR entry 500 * @sid: process Space ID - currently only support KERNEL_SPACE 501 * @vba: Virtual CPU address of buffer to map 502 * @hint: DMA hint set to use for this mapping 503 * 504 * SBA Mapping Routine 505 * 506 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 507 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 508 * pdir_ptr (arg0). 509 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 510 * for Astro/Ike looks like: 511 * 512 * 513 * 0 19 51 55 63 514 * +-+---------------------+----------------------------------+----+--------+ 515 * |V| U | PPN[43:12] | U | VI | 516 * +-+---------------------+----------------------------------+----+--------+ 517 * 518 * Pluto is basically identical, supports fewer physical address bits: 519 * 520 * 0 23 51 55 63 521 * +-+------------------------+-------------------------------+----+--------+ 522 * |V| U | PPN[39:12] | U | VI | 523 * +-+------------------------+-------------------------------+----+--------+ 524 * 525 * V == Valid Bit (Most Significant Bit is bit 0) 526 * U == Unused 527 * PPN == Physical Page Number 528 * VI == Virtual Index (aka Coherent Index) 529 * 530 * LPA instruction output is put into PPN field. 531 * LCI (Load Coherence Index) instruction provides the "VI" bits. 532 * 533 * We pre-swap the bytes since PCX-W is Big Endian and the 534 * IOMMU uses little endian for the pdir. 535 */ 536 537 void SBA_INLINE 538 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 539 unsigned long hint) 540 { 541 u64 pa; /* physical address */ 542 register unsigned ci; /* coherent index */ 543 544 pa = virt_to_phys(vba); 545 pa &= IOVP_MASK; 546 547 mtsp(sid,1); 548 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 549 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */ 550 551 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 552 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 553 554 /* 555 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 556 * (bit #61, big endian), we have to flush and sync every time 557 * IO-PDIR is changed in Ike/Astro. 558 */ 559 if (ioc_needs_fdc) 560 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 561 } 562 563 564 /** 565 * sba_mark_invalid - invalidate one or more IO PDIR entries 566 * @ioc: IO MMU structure which owns the pdir we are interested in. 567 * @iova: IO Virtual Address mapped earlier 568 * @byte_cnt: number of bytes this mapping covers. 569 * 570 * Marking the IO PDIR entry(ies) as Invalid and invalidate 571 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 572 * is to purge stale entries in the IO TLB when unmapping entries. 573 * 574 * The PCOM register supports purging of multiple pages, with a minium 575 * of 1 page and a maximum of 2GB. Hardware requires the address be 576 * aligned to the size of the range being purged. The size of the range 577 * must be a power of 2. The "Cool perf optimization" in the 578 * allocation routine helps keep that true. 579 */ 580 static SBA_INLINE void 581 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 582 { 583 u32 iovp = (u32) SBA_IOVP(ioc,iova); 584 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 585 586 #ifdef ASSERT_PDIR_SANITY 587 /* Assert first pdir entry is set. 588 ** 589 ** Even though this is a big-endian machine, the entries 590 ** in the iopdir are little endian. That's why we look at 591 ** the byte at +7 instead of at +0. 592 */ 593 if (0x80 != (((u8 *) pdir_ptr)[7])) { 594 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 595 } 596 #endif 597 598 if (byte_cnt > IOVP_SIZE) 599 { 600 #if 0 601 unsigned long entries_per_cacheline = ioc_needs_fdc ? 602 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 603 - (unsigned long) pdir_ptr; 604 : 262144; 605 #endif 606 607 /* set "size" field for PCOM */ 608 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 609 610 do { 611 /* clear I/O Pdir entry "valid" bit first */ 612 ((u8 *) pdir_ptr)[7] = 0; 613 if (ioc_needs_fdc) { 614 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 615 #if 0 616 entries_per_cacheline = L1_CACHE_SHIFT - 3; 617 #endif 618 } 619 pdir_ptr++; 620 byte_cnt -= IOVP_SIZE; 621 } while (byte_cnt > IOVP_SIZE); 622 } else 623 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 624 625 /* 626 ** clear I/O PDIR entry "valid" bit. 627 ** We have to R/M/W the cacheline regardless how much of the 628 ** pdir entry that we clobber. 629 ** The rest of the entry would be useful for debugging if we 630 ** could dump core on HPMC. 631 */ 632 ((u8 *) pdir_ptr)[7] = 0; 633 if (ioc_needs_fdc) 634 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 635 636 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 637 } 638 639 /** 640 * sba_dma_supported - PCI driver can query DMA support 641 * @dev: instance of PCI owned by the driver that's asking 642 * @mask: number of address bits this PCI device can handle 643 * 644 * See Documentation/DMA-mapping.txt 645 */ 646 static int sba_dma_supported( struct device *dev, u64 mask) 647 { 648 struct ioc *ioc; 649 650 if (dev == NULL) { 651 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 652 BUG(); 653 return(0); 654 } 655 656 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first, 657 * then fall back to 32-bit if that fails. 658 * We are just "encouraging" 32-bit DMA masks here since we can 659 * never allow IOMMU bypass unless we add special support for ZX1. 660 */ 661 if (mask > ~0U) 662 return 0; 663 664 ioc = GET_IOC(dev); 665 666 /* 667 * check if mask is >= than the current max IO Virt Address 668 * The max IO Virt address will *always* < 30 bits. 669 */ 670 return((int)(mask >= (ioc->ibase - 1 + 671 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 672 } 673 674 675 /** 676 * sba_map_single - map one buffer and return IOVA for DMA 677 * @dev: instance of PCI owned by the driver that's asking. 678 * @addr: driver buffer to map. 679 * @size: number of bytes to map in driver buffer. 680 * @direction: R/W or both. 681 * 682 * See Documentation/DMA-mapping.txt 683 */ 684 static dma_addr_t 685 sba_map_single(struct device *dev, void *addr, size_t size, 686 enum dma_data_direction direction) 687 { 688 struct ioc *ioc; 689 unsigned long flags; 690 dma_addr_t iovp; 691 dma_addr_t offset; 692 u64 *pdir_start; 693 int pide; 694 695 ioc = GET_IOC(dev); 696 697 /* save offset bits */ 698 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; 699 700 /* round up to nearest IOVP_SIZE */ 701 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 702 703 spin_lock_irqsave(&ioc->res_lock, flags); 704 #ifdef ASSERT_PDIR_SANITY 705 sba_check_pdir(ioc,"Check before sba_map_single()"); 706 #endif 707 708 #ifdef SBA_COLLECT_STATS 709 ioc->msingle_calls++; 710 ioc->msingle_pages += size >> IOVP_SHIFT; 711 #endif 712 pide = sba_alloc_range(ioc, size); 713 iovp = (dma_addr_t) pide << IOVP_SHIFT; 714 715 DBG_RUN("%s() 0x%p -> 0x%lx\n", 716 __FUNCTION__, addr, (long) iovp | offset); 717 718 pdir_start = &(ioc->pdir_base[pide]); 719 720 while (size > 0) { 721 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); 722 723 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 724 pdir_start, 725 (u8) (((u8 *) pdir_start)[7]), 726 (u8) (((u8 *) pdir_start)[6]), 727 (u8) (((u8 *) pdir_start)[5]), 728 (u8) (((u8 *) pdir_start)[4]), 729 (u8) (((u8 *) pdir_start)[3]), 730 (u8) (((u8 *) pdir_start)[2]), 731 (u8) (((u8 *) pdir_start)[1]), 732 (u8) (((u8 *) pdir_start)[0]) 733 ); 734 735 addr += IOVP_SIZE; 736 size -= IOVP_SIZE; 737 pdir_start++; 738 } 739 740 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 741 if (ioc_needs_fdc) 742 asm volatile("sync" : : ); 743 744 #ifdef ASSERT_PDIR_SANITY 745 sba_check_pdir(ioc,"Check after sba_map_single()"); 746 #endif 747 spin_unlock_irqrestore(&ioc->res_lock, flags); 748 749 /* form complete address */ 750 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 751 } 752 753 754 /** 755 * sba_unmap_single - unmap one IOVA and free resources 756 * @dev: instance of PCI owned by the driver that's asking. 757 * @iova: IOVA of driver buffer previously mapped. 758 * @size: number of bytes mapped in driver buffer. 759 * @direction: R/W or both. 760 * 761 * See Documentation/DMA-mapping.txt 762 */ 763 static void 764 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 765 enum dma_data_direction direction) 766 { 767 struct ioc *ioc; 768 #if DELAYED_RESOURCE_CNT > 0 769 struct sba_dma_pair *d; 770 #endif 771 unsigned long flags; 772 dma_addr_t offset; 773 774 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size); 775 776 ioc = GET_IOC(dev); 777 offset = iova & ~IOVP_MASK; 778 iova ^= offset; /* clear offset bits */ 779 size += offset; 780 size = ALIGN(size, IOVP_SIZE); 781 782 spin_lock_irqsave(&ioc->res_lock, flags); 783 784 #ifdef SBA_COLLECT_STATS 785 ioc->usingle_calls++; 786 ioc->usingle_pages += size >> IOVP_SHIFT; 787 #endif 788 789 sba_mark_invalid(ioc, iova, size); 790 791 #if DELAYED_RESOURCE_CNT > 0 792 /* Delaying when we re-use a IO Pdir entry reduces the number 793 * of MMIO reads needed to flush writes to the PCOM register. 794 */ 795 d = &(ioc->saved[ioc->saved_cnt]); 796 d->iova = iova; 797 d->size = size; 798 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 799 int cnt = ioc->saved_cnt; 800 while (cnt--) { 801 sba_free_range(ioc, d->iova, d->size); 802 d--; 803 } 804 ioc->saved_cnt = 0; 805 806 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 807 } 808 #else /* DELAYED_RESOURCE_CNT == 0 */ 809 sba_free_range(ioc, iova, size); 810 811 /* If fdc's were issued, force fdc's to be visible now */ 812 if (ioc_needs_fdc) 813 asm volatile("sync" : : ); 814 815 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 816 #endif /* DELAYED_RESOURCE_CNT == 0 */ 817 818 spin_unlock_irqrestore(&ioc->res_lock, flags); 819 820 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 821 ** For Astro based systems this isn't a big deal WRT performance. 822 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 823 ** we don't need the syncdma. The issue here is I/O MMU cachelines 824 ** are *not* coherent in all cases. May be hwrev dependent. 825 ** Need to investigate more. 826 asm volatile("syncdma"); 827 */ 828 } 829 830 831 /** 832 * sba_alloc_consistent - allocate/map shared mem for DMA 833 * @hwdev: instance of PCI owned by the driver that's asking. 834 * @size: number of bytes mapped in driver buffer. 835 * @dma_handle: IOVA of new buffer. 836 * 837 * See Documentation/DMA-mapping.txt 838 */ 839 static void *sba_alloc_consistent(struct device *hwdev, size_t size, 840 dma_addr_t *dma_handle, gfp_t gfp) 841 { 842 void *ret; 843 844 if (!hwdev) { 845 /* only support PCI */ 846 *dma_handle = 0; 847 return NULL; 848 } 849 850 ret = (void *) __get_free_pages(gfp, get_order(size)); 851 852 if (ret) { 853 memset(ret, 0, size); 854 *dma_handle = sba_map_single(hwdev, ret, size, 0); 855 } 856 857 return ret; 858 } 859 860 861 /** 862 * sba_free_consistent - free/unmap shared mem for DMA 863 * @hwdev: instance of PCI owned by the driver that's asking. 864 * @size: number of bytes mapped in driver buffer. 865 * @vaddr: virtual address IOVA of "consistent" buffer. 866 * @dma_handler: IO virtual address of "consistent" buffer. 867 * 868 * See Documentation/DMA-mapping.txt 869 */ 870 static void 871 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr, 872 dma_addr_t dma_handle) 873 { 874 sba_unmap_single(hwdev, dma_handle, size, 0); 875 free_pages((unsigned long) vaddr, get_order(size)); 876 } 877 878 879 /* 880 ** Since 0 is a valid pdir_base index value, can't use that 881 ** to determine if a value is valid or not. Use a flag to indicate 882 ** the SG list entry contains a valid pdir index. 883 */ 884 #define PIDE_FLAG 0x80000000UL 885 886 #ifdef SBA_COLLECT_STATS 887 #define IOMMU_MAP_STATS 888 #endif 889 #include "iommu-helpers.h" 890 891 #ifdef DEBUG_LARGE_SG_ENTRIES 892 int dump_run_sg = 0; 893 #endif 894 895 896 /** 897 * sba_map_sg - map Scatter/Gather list 898 * @dev: instance of PCI owned by the driver that's asking. 899 * @sglist: array of buffer/length pairs 900 * @nents: number of entries in list 901 * @direction: R/W or both. 902 * 903 * See Documentation/DMA-mapping.txt 904 */ 905 static int 906 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 907 enum dma_data_direction direction) 908 { 909 struct ioc *ioc; 910 int coalesced, filled = 0; 911 unsigned long flags; 912 913 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents); 914 915 ioc = GET_IOC(dev); 916 917 /* Fast path single entry scatterlists. */ 918 if (nents == 1) { 919 sg_dma_address(sglist) = sba_map_single(dev, 920 (void *)sg_virt_addr(sglist), 921 sglist->length, direction); 922 sg_dma_len(sglist) = sglist->length; 923 return 1; 924 } 925 926 spin_lock_irqsave(&ioc->res_lock, flags); 927 928 #ifdef ASSERT_PDIR_SANITY 929 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 930 { 931 sba_dump_sg(ioc, sglist, nents); 932 panic("Check before sba_map_sg()"); 933 } 934 #endif 935 936 #ifdef SBA_COLLECT_STATS 937 ioc->msg_calls++; 938 #endif 939 940 /* 941 ** First coalesce the chunks and allocate I/O pdir space 942 ** 943 ** If this is one DMA stream, we can properly map using the 944 ** correct virtual address associated with each DMA page. 945 ** w/o this association, we wouldn't have coherent DMA! 946 ** Access to the virtual address is what forces a two pass algorithm. 947 */ 948 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range); 949 950 /* 951 ** Program the I/O Pdir 952 ** 953 ** map the virtual addresses to the I/O Pdir 954 ** o dma_address will contain the pdir index 955 ** o dma_len will contain the number of bytes to map 956 ** o address contains the virtual address. 957 */ 958 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 959 960 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 961 if (ioc_needs_fdc) 962 asm volatile("sync" : : ); 963 964 #ifdef ASSERT_PDIR_SANITY 965 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 966 { 967 sba_dump_sg(ioc, sglist, nents); 968 panic("Check after sba_map_sg()\n"); 969 } 970 #endif 971 972 spin_unlock_irqrestore(&ioc->res_lock, flags); 973 974 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled); 975 976 return filled; 977 } 978 979 980 /** 981 * sba_unmap_sg - unmap Scatter/Gather list 982 * @dev: instance of PCI owned by the driver that's asking. 983 * @sglist: array of buffer/length pairs 984 * @nents: number of entries in list 985 * @direction: R/W or both. 986 * 987 * See Documentation/DMA-mapping.txt 988 */ 989 static void 990 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 991 enum dma_data_direction direction) 992 { 993 struct ioc *ioc; 994 #ifdef ASSERT_PDIR_SANITY 995 unsigned long flags; 996 #endif 997 998 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 999 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length); 1000 1001 ioc = GET_IOC(dev); 1002 1003 #ifdef SBA_COLLECT_STATS 1004 ioc->usg_calls++; 1005 #endif 1006 1007 #ifdef ASSERT_PDIR_SANITY 1008 spin_lock_irqsave(&ioc->res_lock, flags); 1009 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1010 spin_unlock_irqrestore(&ioc->res_lock, flags); 1011 #endif 1012 1013 while (sg_dma_len(sglist) && nents--) { 1014 1015 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction); 1016 #ifdef SBA_COLLECT_STATS 1017 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1018 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1019 #endif 1020 ++sglist; 1021 } 1022 1023 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents); 1024 1025 #ifdef ASSERT_PDIR_SANITY 1026 spin_lock_irqsave(&ioc->res_lock, flags); 1027 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1028 spin_unlock_irqrestore(&ioc->res_lock, flags); 1029 #endif 1030 1031 } 1032 1033 static struct hppa_dma_ops sba_ops = { 1034 .dma_supported = sba_dma_supported, 1035 .alloc_consistent = sba_alloc_consistent, 1036 .alloc_noncoherent = sba_alloc_consistent, 1037 .free_consistent = sba_free_consistent, 1038 .map_single = sba_map_single, 1039 .unmap_single = sba_unmap_single, 1040 .map_sg = sba_map_sg, 1041 .unmap_sg = sba_unmap_sg, 1042 .dma_sync_single_for_cpu = NULL, 1043 .dma_sync_single_for_device = NULL, 1044 .dma_sync_sg_for_cpu = NULL, 1045 .dma_sync_sg_for_device = NULL, 1046 }; 1047 1048 1049 /************************************************************************** 1050 ** 1051 ** SBA PAT PDC support 1052 ** 1053 ** o call pdc_pat_cell_module() 1054 ** o store ranges in PCI "resource" structures 1055 ** 1056 **************************************************************************/ 1057 1058 static void 1059 sba_get_pat_resources(struct sba_device *sba_dev) 1060 { 1061 #if 0 1062 /* 1063 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1064 ** PAT PDC to program the SBA/LBA directed range registers...this 1065 ** burden may fall on the LBA code since it directly supports the 1066 ** PCI subsystem. It's not clear yet. - ggg 1067 */ 1068 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1069 FIXME : ??? 1070 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1071 Tells where the dvi bits are located in the address. 1072 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1073 FIXME : ??? 1074 #endif 1075 } 1076 1077 1078 /************************************************************** 1079 * 1080 * Initialization and claim 1081 * 1082 ***************************************************************/ 1083 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1084 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1085 static void * 1086 sba_alloc_pdir(unsigned int pdir_size) 1087 { 1088 unsigned long pdir_base; 1089 unsigned long pdir_order = get_order(pdir_size); 1090 1091 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1092 if (NULL == (void *) pdir_base) { 1093 panic("%s() could not allocate I/O Page Table\n", 1094 __FUNCTION__); 1095 } 1096 1097 /* If this is not PA8700 (PCX-W2) 1098 ** OR newer than ver 2.2 1099 ** OR in a system that doesn't need VINDEX bits from SBA, 1100 ** 1101 ** then we aren't exposed to the HW bug. 1102 */ 1103 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1104 || (boot_cpu_data.pdc.versions > 0x202) 1105 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1106 return (void *) pdir_base; 1107 1108 /* 1109 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1110 * 1111 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1112 * Ike/Astro can cause silent data corruption. This is only 1113 * a problem if the I/O PDIR is located in memory such that 1114 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1115 * 1116 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1117 * right physical address, we can either avoid (IOPDIR <= 1MB) 1118 * or minimize (2MB IO Pdir) the problem if we restrict the 1119 * IO Pdir to a maximum size of 2MB-128K (1902K). 1120 * 1121 * Because we always allocate 2^N sized IO pdirs, either of the 1122 * "bad" regions will be the last 128K if at all. That's easy 1123 * to test for. 1124 * 1125 */ 1126 if (pdir_order <= (19-12)) { 1127 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1128 /* allocate a new one on 512k alignment */ 1129 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1130 /* release original */ 1131 free_pages(pdir_base, pdir_order); 1132 1133 pdir_base = new_pdir; 1134 1135 /* release excess */ 1136 while (pdir_order < (19-12)) { 1137 new_pdir += pdir_size; 1138 free_pages(new_pdir, pdir_order); 1139 pdir_order +=1; 1140 pdir_size <<=1; 1141 } 1142 } 1143 } else { 1144 /* 1145 ** 1MB or 2MB Pdir 1146 ** Needs to be aligned on an "odd" 1MB boundary. 1147 */ 1148 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1149 1150 /* release original */ 1151 free_pages( pdir_base, pdir_order); 1152 1153 /* release first 1MB */ 1154 free_pages(new_pdir, 20-12); 1155 1156 pdir_base = new_pdir + 1024*1024; 1157 1158 if (pdir_order > (20-12)) { 1159 /* 1160 ** 2MB Pdir. 1161 ** 1162 ** Flag tells init_bitmap() to mark bad 128k as used 1163 ** and to reduce the size by 128k. 1164 */ 1165 piranha_bad_128k = 1; 1166 1167 new_pdir += 3*1024*1024; 1168 /* release last 1MB */ 1169 free_pages(new_pdir, 20-12); 1170 1171 /* release unusable 128KB */ 1172 free_pages(new_pdir - 128*1024 , 17-12); 1173 1174 pdir_size -= 128*1024; 1175 } 1176 } 1177 1178 memset((void *) pdir_base, 0, pdir_size); 1179 return (void *) pdir_base; 1180 } 1181 1182 static struct device *next_device(struct klist_iter *i) 1183 { 1184 struct klist_node * n = klist_next(i); 1185 return n ? container_of(n, struct device, knode_parent) : NULL; 1186 } 1187 1188 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1189 static void 1190 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1191 { 1192 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ 1193 extern void lba_set_iregs(struct parisc_device *, u32, u32); 1194 struct device *dev; 1195 struct klist_iter i; 1196 1197 klist_iter_init(&sba->dev.klist_children, &i); 1198 while ((dev = next_device(&i))) { 1199 struct parisc_device *lba = to_parisc_device(dev); 1200 int rope_num = (lba->hpa.start >> 13) & 0xf; 1201 if (rope_num >> 3 == ioc_num) 1202 lba_set_iregs(lba, ioc->ibase, ioc->imask); 1203 } 1204 klist_iter_exit(&i); 1205 } 1206 1207 static void 1208 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1209 { 1210 u32 iova_space_mask; 1211 u32 iova_space_size; 1212 int iov_order, tcnfg; 1213 #ifdef SBA_AGP_SUPPORT 1214 int agp_found = 0; 1215 #endif 1216 /* 1217 ** Firmware programs the base and size of a "safe IOVA space" 1218 ** (one that doesn't overlap memory or LMMIO space) in the 1219 ** IBASE and IMASK registers. 1220 */ 1221 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE); 1222 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1223 1224 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1225 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1226 iova_space_size /= 2; 1227 } 1228 1229 /* 1230 ** iov_order is always based on a 1GB IOVA space since we want to 1231 ** turn on the other half for AGP GART. 1232 */ 1233 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1234 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1235 1236 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1237 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20, 1238 iov_order + PAGE_SHIFT); 1239 1240 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1241 get_order(ioc->pdir_size)); 1242 if (!ioc->pdir_base) 1243 panic("Couldn't allocate I/O Page Table\n"); 1244 1245 memset(ioc->pdir_base, 0, ioc->pdir_size); 1246 1247 DBG_INIT("%s() pdir %p size %x\n", 1248 __FUNCTION__, ioc->pdir_base, ioc->pdir_size); 1249 1250 #ifdef SBA_HINT_SUPPORT 1251 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1252 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1253 1254 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1255 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1256 #endif 1257 1258 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1259 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1260 1261 /* build IMASK for IOC and Elroy */ 1262 iova_space_mask = 0xffffffff; 1263 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1264 ioc->imask = iova_space_mask; 1265 #ifdef ZX1_SUPPORT 1266 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1267 #endif 1268 sba_dump_tlb(ioc->ioc_hpa); 1269 1270 setup_ibase_imask(sba, ioc, ioc_num); 1271 1272 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1273 1274 #ifdef CONFIG_64BIT 1275 /* 1276 ** Setting the upper bits makes checking for bypass addresses 1277 ** a little faster later on. 1278 */ 1279 ioc->imask |= 0xFFFFFFFF00000000UL; 1280 #endif 1281 1282 /* Set I/O PDIR Page size to system page size */ 1283 switch (PAGE_SHIFT) { 1284 case 12: tcnfg = 0; break; /* 4K */ 1285 case 13: tcnfg = 1; break; /* 8K */ 1286 case 14: tcnfg = 2; break; /* 16K */ 1287 case 16: tcnfg = 3; break; /* 64K */ 1288 default: 1289 panic(__FILE__ "Unsupported system page size %d", 1290 1 << PAGE_SHIFT); 1291 break; 1292 } 1293 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1294 1295 /* 1296 ** Program the IOC's ibase and enable IOVA translation 1297 ** Bit zero == enable bit. 1298 */ 1299 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1300 1301 /* 1302 ** Clear I/O TLB of any possible entries. 1303 ** (Yes. This is a bit paranoid...but so what) 1304 */ 1305 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1306 1307 #ifdef SBA_AGP_SUPPORT 1308 { 1309 struct klist_iter i; 1310 struct device *dev = NULL; 1311 1312 /* 1313 ** If an AGP device is present, only use half of the IOV space 1314 ** for PCI DMA. Unfortunately we can't know ahead of time 1315 ** whether GART support will actually be used, for now we 1316 ** can just key on any AGP device found in the system. 1317 ** We program the next pdir index after we stop w/ a key for 1318 ** the GART code to handshake on. 1319 */ 1320 klist_iter_init(&sba->dev.klist_children, &i); 1321 while ((dev = next_device(&i))) { 1322 struct parisc_device *lba = to_parisc_device(dev); 1323 if (IS_QUICKSILVER(lba)) 1324 agp_found = 1; 1325 } 1326 klist_iter_exit(&i); 1327 1328 if (agp_found && sba_reserve_agpgart) { 1329 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", 1330 __FUNCTION__, (iova_space_size/2) >> 20); 1331 ioc->pdir_size /= 2; 1332 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; 1333 } 1334 } 1335 #endif /*SBA_AGP_SUPPORT*/ 1336 1337 } 1338 1339 static void 1340 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1341 { 1342 u32 iova_space_size, iova_space_mask; 1343 unsigned int pdir_size, iov_order; 1344 1345 /* 1346 ** Determine IOVA Space size from memory size. 1347 ** 1348 ** Ideally, PCI drivers would register the maximum number 1349 ** of DMA they can have outstanding for each device they 1350 ** own. Next best thing would be to guess how much DMA 1351 ** can be outstanding based on PCI Class/sub-class. Both 1352 ** methods still require some "extra" to support PCI 1353 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1354 ** 1355 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1356 ** for DMA hints - ergo only 30 bits max. 1357 */ 1358 1359 iova_space_size = (u32) (num_physpages/global_ioc_cnt); 1360 1361 /* limit IOVA space size to 1MB-1GB */ 1362 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1363 iova_space_size = 1 << (20 - PAGE_SHIFT); 1364 } 1365 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1366 iova_space_size = 1 << (30 - PAGE_SHIFT); 1367 } 1368 1369 /* 1370 ** iova space must be log2() in size. 1371 ** thus, pdir/res_map will also be log2(). 1372 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1373 */ 1374 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1375 1376 /* iova_space_size is now bytes, not pages */ 1377 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1378 1379 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1380 1381 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", 1382 __FUNCTION__, 1383 ioc->ioc_hpa, 1384 (unsigned long) num_physpages >> (20 - PAGE_SHIFT), 1385 iova_space_size>>20, 1386 iov_order + PAGE_SHIFT); 1387 1388 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1389 1390 DBG_INIT("%s() pdir %p size %x\n", 1391 __FUNCTION__, ioc->pdir_base, pdir_size); 1392 1393 #ifdef SBA_HINT_SUPPORT 1394 /* FIXME : DMA HINTs not used */ 1395 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1396 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1397 1398 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1399 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1400 #endif 1401 1402 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1403 1404 /* build IMASK for IOC and Elroy */ 1405 iova_space_mask = 0xffffffff; 1406 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1407 1408 /* 1409 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1410 ** ibase=0, imask=0xFE000000, size=0x2000000. 1411 */ 1412 ioc->ibase = 0; 1413 ioc->imask = iova_space_mask; /* save it */ 1414 #ifdef ZX1_SUPPORT 1415 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1416 #endif 1417 1418 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", 1419 __FUNCTION__, ioc->ibase, ioc->imask); 1420 1421 /* 1422 ** FIXME: Hint registers are programmed with default hint 1423 ** values during boot, so hints should be sane even if we 1424 ** can't reprogram them the way drivers want. 1425 */ 1426 1427 setup_ibase_imask(sba, ioc, ioc_num); 1428 1429 /* 1430 ** Program the IOC's ibase and enable IOVA translation 1431 */ 1432 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1433 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1434 1435 /* Set I/O PDIR Page size to 4K */ 1436 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG); 1437 1438 /* 1439 ** Clear I/O TLB of any possible entries. 1440 ** (Yes. This is a bit paranoid...but so what) 1441 */ 1442 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1443 1444 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1445 1446 DBG_INIT("%s() DONE\n", __FUNCTION__); 1447 } 1448 1449 1450 1451 /************************************************************************** 1452 ** 1453 ** SBA initialization code (HW and SW) 1454 ** 1455 ** o identify SBA chip itself 1456 ** o initialize SBA chip modes (HardFail) 1457 ** o initialize SBA chip modes (HardFail) 1458 ** o FIXME: initialize DMA hints for reasonable defaults 1459 ** 1460 **************************************************************************/ 1461 1462 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1463 { 1464 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1465 } 1466 1467 static void sba_hw_init(struct sba_device *sba_dev) 1468 { 1469 int i; 1470 int num_ioc; 1471 u64 ioc_ctl; 1472 1473 if (!is_pdc_pat()) { 1474 /* Shutdown the USB controller on Astro-based workstations. 1475 ** Once we reprogram the IOMMU, the next DMA performed by 1476 ** USB will HPMC the box. USB is only enabled if a 1477 ** keyboard is present and found. 1478 ** 1479 ** With serial console, j6k v5.0 firmware says: 1480 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1481 ** 1482 ** FIXME: Using GFX+USB console at power up but direct 1483 ** linux to serial console is still broken. 1484 ** USB could generate DMA so we must reset USB. 1485 ** The proper sequence would be: 1486 ** o block console output 1487 ** o reset USB device 1488 ** o reprogram serial port 1489 ** o unblock console output 1490 */ 1491 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1492 pdc_io_reset_devices(); 1493 } 1494 1495 } 1496 1497 1498 #if 0 1499 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1500 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1501 1502 /* 1503 ** Need to deal with DMA from LAN. 1504 ** Maybe use page zero boot device as a handle to talk 1505 ** to PDC about which device to shutdown. 1506 ** 1507 ** Netbooting, j6k v5.0 firmware says: 1508 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1509 ** ARGH! invalid class. 1510 */ 1511 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1512 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1513 pdc_io_reset(); 1514 } 1515 #endif 1516 1517 if (!IS_PLUTO(sba_dev->dev)) { 1518 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1519 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", 1520 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl); 1521 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1522 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1523 /* j6700 v1.6 firmware sets 0x294f */ 1524 /* A500 firmware sets 0x4d */ 1525 1526 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1527 1528 #ifdef DEBUG_SBA_INIT 1529 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1530 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1531 #endif 1532 } /* if !PLUTO */ 1533 1534 if (IS_ASTRO(sba_dev->dev)) { 1535 int err; 1536 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1537 num_ioc = 1; 1538 1539 sba_dev->chip_resv.name = "Astro Intr Ack"; 1540 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1541 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1542 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1543 BUG_ON(err < 0); 1544 1545 } else if (IS_PLUTO(sba_dev->dev)) { 1546 int err; 1547 1548 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1549 num_ioc = 1; 1550 1551 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1552 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1553 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1554 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1555 WARN_ON(err < 0); 1556 1557 sba_dev->iommu_resv.name = "IOVA Space"; 1558 sba_dev->iommu_resv.start = 0x40000000UL; 1559 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1560 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1561 WARN_ON(err < 0); 1562 } else { 1563 /* IKE, REO */ 1564 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1565 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1566 num_ioc = 2; 1567 1568 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1569 } 1570 /* XXX: What about Reo Grande? */ 1571 1572 sba_dev->num_ioc = num_ioc; 1573 for (i = 0; i < num_ioc; i++) { 1574 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1575 unsigned int j; 1576 1577 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1578 1579 /* 1580 * Clear ROPE(N)_CONFIG AO bit. 1581 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1582 * Overrides bit 1 in DMA Hint Sets. 1583 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1584 */ 1585 if (IS_PLUTO(sba_dev->dev)) { 1586 void __iomem *rope_cfg; 1587 unsigned long cfg_val; 1588 1589 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1590 cfg_val = READ_REG(rope_cfg); 1591 cfg_val &= ~IOC_ROPE_AO; 1592 WRITE_REG(cfg_val, rope_cfg); 1593 } 1594 1595 /* 1596 ** Make sure the box crashes on rope errors. 1597 */ 1598 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1599 } 1600 1601 /* flush out the last writes */ 1602 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1603 1604 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", 1605 i, 1606 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1607 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1608 ); 1609 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", 1610 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1611 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1612 ); 1613 1614 if (IS_PLUTO(sba_dev->dev)) { 1615 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1616 } else { 1617 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1618 } 1619 } 1620 } 1621 1622 static void 1623 sba_common_init(struct sba_device *sba_dev) 1624 { 1625 int i; 1626 1627 /* add this one to the head of the list (order doesn't matter) 1628 ** This will be useful for debugging - especially if we get coredumps 1629 */ 1630 sba_dev->next = sba_list; 1631 sba_list = sba_dev; 1632 1633 for(i=0; i< sba_dev->num_ioc; i++) { 1634 int res_size; 1635 #ifdef DEBUG_DMB_TRAP 1636 extern void iterate_pages(unsigned long , unsigned long , 1637 void (*)(pte_t * , unsigned long), 1638 unsigned long ); 1639 void set_data_memory_break(pte_t * , unsigned long); 1640 #endif 1641 /* resource map size dictated by pdir_size */ 1642 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1643 1644 /* Second part of PIRANHA BUG */ 1645 if (piranha_bad_128k) { 1646 res_size -= (128*1024)/sizeof(u64); 1647 } 1648 1649 res_size >>= 3; /* convert bit count to byte count */ 1650 DBG_INIT("%s() res_size 0x%x\n", 1651 __FUNCTION__, res_size); 1652 1653 sba_dev->ioc[i].res_size = res_size; 1654 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1655 1656 #ifdef DEBUG_DMB_TRAP 1657 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1658 set_data_memory_break, 0); 1659 #endif 1660 1661 if (NULL == sba_dev->ioc[i].res_map) 1662 { 1663 panic("%s:%s() could not allocate resource map\n", 1664 __FILE__, __FUNCTION__ ); 1665 } 1666 1667 memset(sba_dev->ioc[i].res_map, 0, res_size); 1668 /* next available IOVP - circular search */ 1669 sba_dev->ioc[i].res_hint = (unsigned long *) 1670 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1671 1672 #ifdef ASSERT_PDIR_SANITY 1673 /* Mark first bit busy - ie no IOVA 0 */ 1674 sba_dev->ioc[i].res_map[0] = 0x80; 1675 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; 1676 #endif 1677 1678 /* Third (and last) part of PIRANHA BUG */ 1679 if (piranha_bad_128k) { 1680 /* region from +1408K to +1536 is un-usable. */ 1681 1682 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1683 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1684 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1685 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1686 1687 /* mark that part of the io pdir busy */ 1688 while (p_start < p_end) 1689 *p_start++ = -1; 1690 1691 } 1692 1693 #ifdef DEBUG_DMB_TRAP 1694 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1695 set_data_memory_break, 0); 1696 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1697 set_data_memory_break, 0); 1698 #endif 1699 1700 DBG_INIT("%s() %d res_map %x %p\n", 1701 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map); 1702 } 1703 1704 spin_lock_init(&sba_dev->sba_lock); 1705 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1706 1707 #ifdef DEBUG_SBA_INIT 1708 /* 1709 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1710 * (bit #61, big endian), we have to flush and sync every time 1711 * IO-PDIR is changed in Ike/Astro. 1712 */ 1713 if (ioc_needs_fdc) { 1714 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1715 } else { 1716 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1717 } 1718 #endif 1719 } 1720 1721 #ifdef CONFIG_PROC_FS 1722 static int sba_proc_info(struct seq_file *m, void *p) 1723 { 1724 struct sba_device *sba_dev = sba_list; 1725 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1726 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1727 #ifdef SBA_COLLECT_STATS 1728 unsigned long avg = 0, min, max; 1729 #endif 1730 int i, len = 0; 1731 1732 len += seq_printf(m, "%s rev %d.%d\n", 1733 sba_dev->name, 1734 (sba_dev->hw_rev & 0x7) + 1, 1735 (sba_dev->hw_rev & 0x18) >> 3 1736 ); 1737 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1738 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1739 total_pages); 1740 1741 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1742 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1743 1744 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1745 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1746 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1747 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE) 1748 ); 1749 1750 for (i=0; i<4; i++) 1751 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i, 1752 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1753 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1754 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18) 1755 ); 1756 1757 #ifdef SBA_COLLECT_STATS 1758 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1759 total_pages - ioc->used_pages, ioc->used_pages, 1760 (int) (ioc->used_pages * 100 / total_pages)); 1761 1762 min = max = ioc->avg_search[0]; 1763 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1764 avg += ioc->avg_search[i]; 1765 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1766 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1767 } 1768 avg /= SBA_SEARCH_SAMPLE; 1769 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1770 min, avg, max); 1771 1772 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1773 ioc->msingle_calls, ioc->msingle_pages, 1774 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1775 1776 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1777 min = ioc->usingle_calls; 1778 max = ioc->usingle_pages - ioc->usg_pages; 1779 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1780 min, max, (int) ((max * 1000)/min)); 1781 1782 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1783 ioc->msg_calls, ioc->msg_pages, 1784 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls)); 1785 1786 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1787 ioc->usg_calls, ioc->usg_pages, 1788 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls)); 1789 #endif 1790 1791 return 0; 1792 } 1793 1794 static int 1795 sba_proc_open(struct inode *i, struct file *f) 1796 { 1797 return single_open(f, &sba_proc_info, NULL); 1798 } 1799 1800 static const struct file_operations sba_proc_fops = { 1801 .owner = THIS_MODULE, 1802 .open = sba_proc_open, 1803 .read = seq_read, 1804 .llseek = seq_lseek, 1805 .release = single_release, 1806 }; 1807 1808 static int 1809 sba_proc_bitmap_info(struct seq_file *m, void *p) 1810 { 1811 struct sba_device *sba_dev = sba_list; 1812 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1813 unsigned int *res_ptr = (unsigned int *)ioc->res_map; 1814 int i, len = 0; 1815 1816 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) { 1817 if ((i & 7) == 0) 1818 len += seq_printf(m, "\n "); 1819 len += seq_printf(m, " %08x", *res_ptr); 1820 } 1821 len += seq_printf(m, "\n"); 1822 1823 return 0; 1824 } 1825 1826 static int 1827 sba_proc_bitmap_open(struct inode *i, struct file *f) 1828 { 1829 return single_open(f, &sba_proc_bitmap_info, NULL); 1830 } 1831 1832 static const struct file_operations sba_proc_bitmap_fops = { 1833 .owner = THIS_MODULE, 1834 .open = sba_proc_bitmap_open, 1835 .read = seq_read, 1836 .llseek = seq_lseek, 1837 .release = single_release, 1838 }; 1839 #endif /* CONFIG_PROC_FS */ 1840 1841 static struct parisc_device_id sba_tbl[] = { 1842 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1843 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1844 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1845 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1846 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1847 { 0, } 1848 }; 1849 1850 int sba_driver_callback(struct parisc_device *); 1851 1852 static struct parisc_driver sba_driver = { 1853 .name = MODULE_NAME, 1854 .id_table = sba_tbl, 1855 .probe = sba_driver_callback, 1856 }; 1857 1858 /* 1859 ** Determine if sba should claim this chip (return 0) or not (return 1). 1860 ** If so, initialize the chip and tell other partners in crime they 1861 ** have work to do. 1862 */ 1863 int 1864 sba_driver_callback(struct parisc_device *dev) 1865 { 1866 struct sba_device *sba_dev; 1867 u32 func_class; 1868 int i; 1869 char *version; 1870 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE); 1871 struct proc_dir_entry *info_entry, *bitmap_entry, *root; 1872 1873 sba_dump_ranges(sba_addr); 1874 1875 /* Read HW Rev First */ 1876 func_class = READ_REG(sba_addr + SBA_FCLASS); 1877 1878 if (IS_ASTRO(dev)) { 1879 unsigned long fclass; 1880 static char astro_rev[]="Astro ?.?"; 1881 1882 /* Astro is broken...Read HW Rev First */ 1883 fclass = READ_REG(sba_addr); 1884 1885 astro_rev[6] = '1' + (char) (fclass & 0x7); 1886 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1887 version = astro_rev; 1888 1889 } else if (IS_IKE(dev)) { 1890 static char ike_rev[] = "Ike rev ?"; 1891 ike_rev[8] = '0' + (char) (func_class & 0xff); 1892 version = ike_rev; 1893 } else if (IS_PLUTO(dev)) { 1894 static char pluto_rev[]="Pluto ?.?"; 1895 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1896 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1897 version = pluto_rev; 1898 } else { 1899 static char reo_rev[] = "REO rev ?"; 1900 reo_rev[8] = '0' + (char) (func_class & 0xff); 1901 version = reo_rev; 1902 } 1903 1904 if (!global_ioc_cnt) { 1905 global_ioc_cnt = count_parisc_driver(&sba_driver); 1906 1907 /* Astro and Pluto have one IOC per SBA */ 1908 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1909 global_ioc_cnt *= 2; 1910 } 1911 1912 printk(KERN_INFO "%s found %s at 0x%lx\n", 1913 MODULE_NAME, version, dev->hpa.start); 1914 1915 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 1916 if (!sba_dev) { 1917 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1918 return -ENOMEM; 1919 } 1920 1921 parisc_set_drvdata(dev, sba_dev); 1922 1923 for(i=0; i<MAX_IOC; i++) 1924 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1925 1926 sba_dev->dev = dev; 1927 sba_dev->hw_rev = func_class; 1928 sba_dev->name = dev->name; 1929 sba_dev->sba_hpa = sba_addr; 1930 1931 sba_get_pat_resources(sba_dev); 1932 sba_hw_init(sba_dev); 1933 sba_common_init(sba_dev); 1934 1935 hppa_dma_ops = &sba_ops; 1936 1937 #ifdef CONFIG_PROC_FS 1938 switch (dev->id.hversion) { 1939 case PLUTO_MCKINLEY_PORT: 1940 root = proc_mckinley_root; 1941 break; 1942 case ASTRO_RUNWAY_PORT: 1943 case IKE_MERCED_PORT: 1944 default: 1945 root = proc_runway_root; 1946 break; 1947 } 1948 1949 info_entry = create_proc_entry("sba_iommu", 0, root); 1950 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root); 1951 1952 if (info_entry) 1953 info_entry->proc_fops = &sba_proc_fops; 1954 1955 if (bitmap_entry) 1956 bitmap_entry->proc_fops = &sba_proc_bitmap_fops; 1957 #endif 1958 1959 parisc_vmerge_boundary = IOVP_SIZE; 1960 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG; 1961 parisc_has_iommu(); 1962 return 0; 1963 } 1964 1965 /* 1966 ** One time initialization to let the world know the SBA was found. 1967 ** This is the only routine which is NOT static. 1968 ** Must be called exactly once before pci_init(). 1969 */ 1970 void __init sba_init(void) 1971 { 1972 register_parisc_driver(&sba_driver); 1973 } 1974 1975 1976 /** 1977 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 1978 * @dev: The parisc device. 1979 * 1980 * Returns the appropriate IOMMU data for the given parisc PCI controller. 1981 * This is cached and used later for PCI DMA Mapping. 1982 */ 1983 void * sba_get_iommu(struct parisc_device *pci_hba) 1984 { 1985 struct parisc_device *sba_dev = parisc_parent(pci_hba); 1986 struct sba_device *sba = sba_dev->dev.driver_data; 1987 char t = sba_dev->id.hw_type; 1988 int iocnum = (pci_hba->hw_path >> 3); /* rope # */ 1989 1990 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 1991 1992 return &(sba->ioc[iocnum]); 1993 } 1994 1995 1996 /** 1997 * sba_directed_lmmio - return first directed LMMIO range routed to rope 1998 * @pa_dev: The parisc device. 1999 * @r: resource PCI host controller wants start/end fields assigned. 2000 * 2001 * For the given parisc PCI controller, determine if any direct ranges 2002 * are routed down the corresponding rope. 2003 */ 2004 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2005 { 2006 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2007 struct sba_device *sba = sba_dev->dev.driver_data; 2008 char t = sba_dev->id.hw_type; 2009 int i; 2010 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2011 2012 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2013 2014 r->start = r->end = 0; 2015 2016 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2017 for (i=0; i<4; i++) { 2018 int base, size; 2019 void __iomem *reg = sba->sba_hpa + i*0x18; 2020 2021 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2022 if ((base & 1) == 0) 2023 continue; /* not enabled */ 2024 2025 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2026 2027 if ((size & (ROPES_PER_IOC-1)) != rope) 2028 continue; /* directed down different rope */ 2029 2030 r->start = (base & ~1UL) | PCI_F_EXTEND; 2031 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2032 r->end = r->start + size; 2033 } 2034 } 2035 2036 2037 /** 2038 * sba_distributed_lmmio - return portion of distributed LMMIO range 2039 * @pa_dev: The parisc device. 2040 * @r: resource PCI host controller wants start/end fields assigned. 2041 * 2042 * For the given parisc PCI controller, return portion of distributed LMMIO 2043 * range. The distributed LMMIO is always present and it's just a question 2044 * of the base address and size of the range. 2045 */ 2046 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2047 { 2048 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2049 struct sba_device *sba = sba_dev->dev.driver_data; 2050 char t = sba_dev->id.hw_type; 2051 int base, size; 2052 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2053 2054 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2055 2056 r->start = r->end = 0; 2057 2058 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2059 if ((base & 1) == 0) { 2060 BUG(); /* Gah! Distr Range wasn't enabled! */ 2061 return; 2062 } 2063 2064 r->start = (base & ~1UL) | PCI_F_EXTEND; 2065 2066 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2067 r->start += rope * (size + 1); /* adjust base for this rope */ 2068 r->end = r->start + size; 2069 } 2070