1 /* 2 ** System Bus Adapter (SBA) I/O MMU manager 3 ** 4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 6 ** (c) Copyright 2000-2004 Hewlett-Packard Company 7 ** 8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 17 ** J5000/J7000/N-class/L-class machines and their successors. 18 ** 19 ** FIXME: add DMA hint support programming in both sba and lba modules. 20 */ 21 22 #include <linux/types.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/slab.h> 26 #include <linux/init.h> 27 28 #include <linux/mm.h> 29 #include <linux/string.h> 30 #include <linux/pci.h> 31 #include <linux/scatterlist.h> 32 #include <linux/iommu-helper.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/io.h> 36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 37 38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 39 40 #include <linux/proc_fs.h> 41 #include <linux/seq_file.h> 42 #include <linux/module.h> 43 44 #include <asm/ropes.h> 45 #include <asm/mckinley.h> /* for proc_mckinley_root */ 46 #include <asm/runway.h> /* for proc_runway_root */ 47 #include <asm/page.h> /* for PAGE0 */ 48 #include <asm/pdc.h> /* for PDC_MODEL_* */ 49 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 50 #include <asm/parisc-device.h> 51 52 #define MODULE_NAME "SBA" 53 54 /* 55 ** The number of debug flags is a clue - this code is fragile. 56 ** Don't even think about messing with it unless you have 57 ** plenty of 710's to sacrifice to the computer gods. :^) 58 */ 59 #undef DEBUG_SBA_INIT 60 #undef DEBUG_SBA_RUN 61 #undef DEBUG_SBA_RUN_SG 62 #undef DEBUG_SBA_RESOURCE 63 #undef ASSERT_PDIR_SANITY 64 #undef DEBUG_LARGE_SG_ENTRIES 65 #undef DEBUG_DMB_TRAP 66 67 #ifdef DEBUG_SBA_INIT 68 #define DBG_INIT(x...) printk(x) 69 #else 70 #define DBG_INIT(x...) 71 #endif 72 73 #ifdef DEBUG_SBA_RUN 74 #define DBG_RUN(x...) printk(x) 75 #else 76 #define DBG_RUN(x...) 77 #endif 78 79 #ifdef DEBUG_SBA_RUN_SG 80 #define DBG_RUN_SG(x...) printk(x) 81 #else 82 #define DBG_RUN_SG(x...) 83 #endif 84 85 86 #ifdef DEBUG_SBA_RESOURCE 87 #define DBG_RES(x...) printk(x) 88 #else 89 #define DBG_RES(x...) 90 #endif 91 92 #define SBA_INLINE __inline__ 93 94 #define DEFAULT_DMA_HINT_REG 0 95 96 #define SBA_MAPPING_ERROR (~(dma_addr_t)0) 97 98 struct sba_device *sba_list; 99 EXPORT_SYMBOL_GPL(sba_list); 100 101 static unsigned long ioc_needs_fdc = 0; 102 103 /* global count of IOMMUs in the system */ 104 static unsigned int global_ioc_cnt = 0; 105 106 /* PA8700 (Piranha 2.2) bug workaround */ 107 static unsigned long piranha_bad_128k = 0; 108 109 /* Looks nice and keeps the compiler happy */ 110 #define SBA_DEV(d) ((struct sba_device *) (d)) 111 112 #ifdef CONFIG_AGP_PARISC 113 #define SBA_AGP_SUPPORT 114 #endif /*CONFIG_AGP_PARISC*/ 115 116 #ifdef SBA_AGP_SUPPORT 117 static int sba_reserve_agpgart = 1; 118 module_param(sba_reserve_agpgart, int, 0444); 119 MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART"); 120 #endif 121 122 123 /************************************ 124 ** SBA register read and write support 125 ** 126 ** BE WARNED: register writes are posted. 127 ** (ie follow writes which must reach HW with a read) 128 ** 129 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 130 */ 131 #define READ_REG32(addr) readl(addr) 132 #define READ_REG64(addr) readq(addr) 133 #define WRITE_REG32(val, addr) writel((val), (addr)) 134 #define WRITE_REG64(val, addr) writeq((val), (addr)) 135 136 #ifdef CONFIG_64BIT 137 #define READ_REG(addr) READ_REG64(addr) 138 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 139 #else 140 #define READ_REG(addr) READ_REG32(addr) 141 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 142 #endif 143 144 #ifdef DEBUG_SBA_INIT 145 146 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 147 148 /** 149 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 150 * @hpa: base address of the sba 151 * 152 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 153 * IO Adapter (aka Bus Converter). 154 */ 155 static void 156 sba_dump_ranges(void __iomem *hpa) 157 { 158 DBG_INIT("SBA at 0x%p\n", hpa); 159 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 160 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 161 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 162 DBG_INIT("\n"); 163 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 164 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 165 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 166 } 167 168 /** 169 * sba_dump_tlb - debugging only - print IOMMU operating parameters 170 * @hpa: base address of the IOMMU 171 * 172 * Print the size/location of the IO MMU PDIR. 173 */ 174 static void sba_dump_tlb(void __iomem *hpa) 175 { 176 DBG_INIT("IO TLB at 0x%p\n", hpa); 177 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 178 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 179 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 180 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 181 DBG_INIT("\n"); 182 } 183 #else 184 #define sba_dump_ranges(x) 185 #define sba_dump_tlb(x) 186 #endif /* DEBUG_SBA_INIT */ 187 188 189 #ifdef ASSERT_PDIR_SANITY 190 191 /** 192 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 193 * @ioc: IO MMU structure which owns the pdir we are interested in. 194 * @msg: text to print ont the output line. 195 * @pide: pdir index. 196 * 197 * Print one entry of the IO MMU PDIR in human readable form. 198 */ 199 static void 200 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 201 { 202 /* start printing from lowest pde in rval */ 203 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 204 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 205 uint rcnt; 206 207 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 208 msg, 209 rptr, pide & (BITS_PER_LONG - 1), *rptr); 210 211 rcnt = 0; 212 while (rcnt < BITS_PER_LONG) { 213 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 214 (rcnt == (pide & (BITS_PER_LONG - 1))) 215 ? " -->" : " ", 216 rcnt, ptr, *ptr ); 217 rcnt++; 218 ptr++; 219 } 220 printk(KERN_DEBUG "%s", msg); 221 } 222 223 224 /** 225 * sba_check_pdir - debugging only - consistency checker 226 * @ioc: IO MMU structure which owns the pdir we are interested in. 227 * @msg: text to print ont the output line. 228 * 229 * Verify the resource map and pdir state is consistent 230 */ 231 static int 232 sba_check_pdir(struct ioc *ioc, char *msg) 233 { 234 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 235 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 236 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 237 uint pide = 0; 238 239 while (rptr < rptr_end) { 240 u32 rval = *rptr; 241 int rcnt = 32; /* number of bits we might check */ 242 243 while (rcnt) { 244 /* Get last byte and highest bit from that */ 245 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 246 if ((rval ^ pde) & 0x80000000) 247 { 248 /* 249 ** BUMMER! -- res_map != pdir -- 250 ** Dump rval and matching pdir entries 251 */ 252 sba_dump_pdir_entry(ioc, msg, pide); 253 return(1); 254 } 255 rcnt--; 256 rval <<= 1; /* try the next bit */ 257 pptr++; 258 pide++; 259 } 260 rptr++; /* look at next word of res_map */ 261 } 262 /* It'd be nice if we always got here :^) */ 263 return 0; 264 } 265 266 267 /** 268 * sba_dump_sg - debugging only - print Scatter-Gather list 269 * @ioc: IO MMU structure which owns the pdir we are interested in. 270 * @startsg: head of the SG list 271 * @nents: number of entries in SG list 272 * 273 * print the SG list so we can verify it's correct by hand. 274 */ 275 static void 276 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 277 { 278 while (nents-- > 0) { 279 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 280 nents, 281 (unsigned long) sg_dma_address(startsg), 282 sg_dma_len(startsg), 283 sg_virt(startsg), startsg->length); 284 startsg++; 285 } 286 } 287 288 #endif /* ASSERT_PDIR_SANITY */ 289 290 291 292 293 /************************************************************** 294 * 295 * I/O Pdir Resource Management 296 * 297 * Bits set in the resource map are in use. 298 * Each bit can represent a number of pages. 299 * LSbs represent lower addresses (IOVA's). 300 * 301 ***************************************************************/ 302 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 303 304 /* Convert from IOVP to IOVA and vice versa. */ 305 306 #ifdef ZX1_SUPPORT 307 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 308 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 309 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 310 #else 311 /* only support Astro and ancestors. Saves a few cycles in key places */ 312 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 313 #define SBA_IOVP(ioc,iova) (iova) 314 #endif 315 316 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 317 318 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 319 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 320 321 static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, 322 unsigned int bitshiftcnt) 323 { 324 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) 325 + bitshiftcnt; 326 } 327 328 /** 329 * sba_search_bitmap - find free space in IO PDIR resource bitmap 330 * @ioc: IO MMU structure which owns the pdir we are interested in. 331 * @bits_wanted: number of entries we need. 332 * 333 * Find consecutive free bits in resource bitmap. 334 * Each bit represents one entry in the IO Pdir. 335 * Cool perf optimization: search for log2(size) bits at a time. 336 */ 337 static SBA_INLINE unsigned long 338 sba_search_bitmap(struct ioc *ioc, struct device *dev, 339 unsigned long bits_wanted) 340 { 341 unsigned long *res_ptr = ioc->res_hint; 342 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 343 unsigned long pide = ~0UL, tpide; 344 unsigned long boundary_size; 345 unsigned long shift; 346 int ret; 347 348 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, 349 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; 350 351 #if defined(ZX1_SUPPORT) 352 BUG_ON(ioc->ibase & ~IOVP_MASK); 353 shift = ioc->ibase >> IOVP_SHIFT; 354 #else 355 shift = 0; 356 #endif 357 358 if (bits_wanted > (BITS_PER_LONG/2)) { 359 /* Search word at a time - no mask needed */ 360 for(; res_ptr < res_end; ++res_ptr) { 361 tpide = ptr_to_pide(ioc, res_ptr, 0); 362 ret = iommu_is_span_boundary(tpide, bits_wanted, 363 shift, 364 boundary_size); 365 if ((*res_ptr == 0) && !ret) { 366 *res_ptr = RESMAP_MASK(bits_wanted); 367 pide = tpide; 368 break; 369 } 370 } 371 /* point to the next word on next pass */ 372 res_ptr++; 373 ioc->res_bitshift = 0; 374 } else { 375 /* 376 ** Search the resource bit map on well-aligned values. 377 ** "o" is the alignment. 378 ** We need the alignment to invalidate I/O TLB using 379 ** SBA HW features in the unmap path. 380 */ 381 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 382 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o); 383 unsigned long mask; 384 385 if (bitshiftcnt >= BITS_PER_LONG) { 386 bitshiftcnt = 0; 387 res_ptr++; 388 } 389 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 390 391 DBG_RES("%s() o %ld %p", __func__, o, res_ptr); 392 while(res_ptr < res_end) 393 { 394 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 395 WARN_ON(mask == 0); 396 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); 397 ret = iommu_is_span_boundary(tpide, bits_wanted, 398 shift, 399 boundary_size); 400 if ((((*res_ptr) & mask) == 0) && !ret) { 401 *res_ptr |= mask; /* mark resources busy! */ 402 pide = tpide; 403 break; 404 } 405 mask >>= o; 406 bitshiftcnt += o; 407 if (mask == 0) { 408 mask = RESMAP_MASK(bits_wanted); 409 bitshiftcnt=0; 410 res_ptr++; 411 } 412 } 413 /* look in the same word on the next pass */ 414 ioc->res_bitshift = bitshiftcnt + bits_wanted; 415 } 416 417 /* wrapped ? */ 418 if (res_end <= res_ptr) { 419 ioc->res_hint = (unsigned long *) ioc->res_map; 420 ioc->res_bitshift = 0; 421 } else { 422 ioc->res_hint = res_ptr; 423 } 424 return (pide); 425 } 426 427 428 /** 429 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 430 * @ioc: IO MMU structure which owns the pdir we are interested in. 431 * @size: number of bytes to create a mapping for 432 * 433 * Given a size, find consecutive unmarked and then mark those bits in the 434 * resource bit map. 435 */ 436 static int 437 sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 438 { 439 unsigned int pages_needed = size >> IOVP_SHIFT; 440 #ifdef SBA_COLLECT_STATS 441 unsigned long cr_start = mfctl(16); 442 #endif 443 unsigned long pide; 444 445 pide = sba_search_bitmap(ioc, dev, pages_needed); 446 if (pide >= (ioc->res_size << 3)) { 447 pide = sba_search_bitmap(ioc, dev, pages_needed); 448 if (pide >= (ioc->res_size << 3)) 449 panic("%s: I/O MMU @ %p is out of mapping resources\n", 450 __FILE__, ioc->ioc_hpa); 451 } 452 453 #ifdef ASSERT_PDIR_SANITY 454 /* verify the first enable bit is clear */ 455 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 456 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 457 } 458 #endif 459 460 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 461 __func__, size, pages_needed, pide, 462 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 463 ioc->res_bitshift ); 464 465 #ifdef SBA_COLLECT_STATS 466 { 467 unsigned long cr_end = mfctl(16); 468 unsigned long tmp = cr_end - cr_start; 469 /* check for roll over */ 470 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 471 } 472 ioc->avg_search[ioc->avg_idx++] = cr_start; 473 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 474 475 ioc->used_pages += pages_needed; 476 #endif 477 478 return (pide); 479 } 480 481 482 /** 483 * sba_free_range - unmark bits in IO PDIR resource bitmap 484 * @ioc: IO MMU structure which owns the pdir we are interested in. 485 * @iova: IO virtual address which was previously allocated. 486 * @size: number of bytes to create a mapping for 487 * 488 * clear bits in the ioc's resource map 489 */ 490 static SBA_INLINE void 491 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 492 { 493 unsigned long iovp = SBA_IOVP(ioc, iova); 494 unsigned int pide = PDIR_INDEX(iovp); 495 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 496 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 497 498 int bits_not_wanted = size >> IOVP_SHIFT; 499 500 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 501 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 502 503 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 504 __func__, (uint) iova, size, 505 bits_not_wanted, m, pide, res_ptr, *res_ptr); 506 507 #ifdef SBA_COLLECT_STATS 508 ioc->used_pages -= bits_not_wanted; 509 #endif 510 511 *res_ptr &= ~m; 512 } 513 514 515 /************************************************************** 516 * 517 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 518 * 519 ***************************************************************/ 520 521 #ifdef SBA_HINT_SUPPORT 522 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 523 #endif 524 525 typedef unsigned long space_t; 526 #define KERNEL_SPACE 0 527 528 /** 529 * sba_io_pdir_entry - fill in one IO PDIR entry 530 * @pdir_ptr: pointer to IO PDIR entry 531 * @sid: process Space ID - currently only support KERNEL_SPACE 532 * @vba: Virtual CPU address of buffer to map 533 * @hint: DMA hint set to use for this mapping 534 * 535 * SBA Mapping Routine 536 * 537 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 538 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 539 * pdir_ptr (arg0). 540 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 541 * for Astro/Ike looks like: 542 * 543 * 544 * 0 19 51 55 63 545 * +-+---------------------+----------------------------------+----+--------+ 546 * |V| U | PPN[43:12] | U | VI | 547 * +-+---------------------+----------------------------------+----+--------+ 548 * 549 * Pluto is basically identical, supports fewer physical address bits: 550 * 551 * 0 23 51 55 63 552 * +-+------------------------+-------------------------------+----+--------+ 553 * |V| U | PPN[39:12] | U | VI | 554 * +-+------------------------+-------------------------------+----+--------+ 555 * 556 * V == Valid Bit (Most Significant Bit is bit 0) 557 * U == Unused 558 * PPN == Physical Page Number 559 * VI == Virtual Index (aka Coherent Index) 560 * 561 * LPA instruction output is put into PPN field. 562 * LCI (Load Coherence Index) instruction provides the "VI" bits. 563 * 564 * We pre-swap the bytes since PCX-W is Big Endian and the 565 * IOMMU uses little endian for the pdir. 566 */ 567 568 static void SBA_INLINE 569 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 570 unsigned long hint) 571 { 572 u64 pa; /* physical address */ 573 register unsigned ci; /* coherent index */ 574 575 pa = virt_to_phys(vba); 576 pa &= IOVP_MASK; 577 578 mtsp(sid,1); 579 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 580 pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */ 581 582 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 583 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 584 585 /* 586 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 587 * (bit #61, big endian), we have to flush and sync every time 588 * IO-PDIR is changed in Ike/Astro. 589 */ 590 asm_io_fdc(pdir_ptr); 591 } 592 593 594 /** 595 * sba_mark_invalid - invalidate one or more IO PDIR entries 596 * @ioc: IO MMU structure which owns the pdir we are interested in. 597 * @iova: IO Virtual Address mapped earlier 598 * @byte_cnt: number of bytes this mapping covers. 599 * 600 * Marking the IO PDIR entry(ies) as Invalid and invalidate 601 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 602 * is to purge stale entries in the IO TLB when unmapping entries. 603 * 604 * The PCOM register supports purging of multiple pages, with a minium 605 * of 1 page and a maximum of 2GB. Hardware requires the address be 606 * aligned to the size of the range being purged. The size of the range 607 * must be a power of 2. The "Cool perf optimization" in the 608 * allocation routine helps keep that true. 609 */ 610 static SBA_INLINE void 611 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 612 { 613 u32 iovp = (u32) SBA_IOVP(ioc,iova); 614 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 615 616 #ifdef ASSERT_PDIR_SANITY 617 /* Assert first pdir entry is set. 618 ** 619 ** Even though this is a big-endian machine, the entries 620 ** in the iopdir are little endian. That's why we look at 621 ** the byte at +7 instead of at +0. 622 */ 623 if (0x80 != (((u8 *) pdir_ptr)[7])) { 624 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 625 } 626 #endif 627 628 if (byte_cnt > IOVP_SIZE) 629 { 630 #if 0 631 unsigned long entries_per_cacheline = ioc_needs_fdc ? 632 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 633 - (unsigned long) pdir_ptr; 634 : 262144; 635 #endif 636 637 /* set "size" field for PCOM */ 638 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 639 640 do { 641 /* clear I/O Pdir entry "valid" bit first */ 642 ((u8 *) pdir_ptr)[7] = 0; 643 asm_io_fdc(pdir_ptr); 644 if (ioc_needs_fdc) { 645 #if 0 646 entries_per_cacheline = L1_CACHE_SHIFT - 3; 647 #endif 648 } 649 pdir_ptr++; 650 byte_cnt -= IOVP_SIZE; 651 } while (byte_cnt > IOVP_SIZE); 652 } else 653 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 654 655 /* 656 ** clear I/O PDIR entry "valid" bit. 657 ** We have to R/M/W the cacheline regardless how much of the 658 ** pdir entry that we clobber. 659 ** The rest of the entry would be useful for debugging if we 660 ** could dump core on HPMC. 661 */ 662 ((u8 *) pdir_ptr)[7] = 0; 663 asm_io_fdc(pdir_ptr); 664 665 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 666 } 667 668 /** 669 * sba_dma_supported - PCI driver can query DMA support 670 * @dev: instance of PCI owned by the driver that's asking 671 * @mask: number of address bits this PCI device can handle 672 * 673 * See Documentation/DMA-API-HOWTO.txt 674 */ 675 static int sba_dma_supported( struct device *dev, u64 mask) 676 { 677 struct ioc *ioc; 678 679 if (dev == NULL) { 680 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 681 BUG(); 682 return(0); 683 } 684 685 /* Documentation/DMA-API-HOWTO.txt tells drivers to try 64-bit 686 * first, then fall back to 32-bit if that fails. 687 * We are just "encouraging" 32-bit DMA masks here since we can 688 * never allow IOMMU bypass unless we add special support for ZX1. 689 */ 690 if (mask > ~0U) 691 return 0; 692 693 ioc = GET_IOC(dev); 694 if (!ioc) 695 return 0; 696 697 /* 698 * check if mask is >= than the current max IO Virt Address 699 * The max IO Virt address will *always* < 30 bits. 700 */ 701 return((int)(mask >= (ioc->ibase - 1 + 702 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 703 } 704 705 706 /** 707 * sba_map_single - map one buffer and return IOVA for DMA 708 * @dev: instance of PCI owned by the driver that's asking. 709 * @addr: driver buffer to map. 710 * @size: number of bytes to map in driver buffer. 711 * @direction: R/W or both. 712 * 713 * See Documentation/DMA-API-HOWTO.txt 714 */ 715 static dma_addr_t 716 sba_map_single(struct device *dev, void *addr, size_t size, 717 enum dma_data_direction direction) 718 { 719 struct ioc *ioc; 720 unsigned long flags; 721 dma_addr_t iovp; 722 dma_addr_t offset; 723 u64 *pdir_start; 724 int pide; 725 726 ioc = GET_IOC(dev); 727 if (!ioc) 728 return SBA_MAPPING_ERROR; 729 730 /* save offset bits */ 731 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; 732 733 /* round up to nearest IOVP_SIZE */ 734 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 735 736 spin_lock_irqsave(&ioc->res_lock, flags); 737 #ifdef ASSERT_PDIR_SANITY 738 sba_check_pdir(ioc,"Check before sba_map_single()"); 739 #endif 740 741 #ifdef SBA_COLLECT_STATS 742 ioc->msingle_calls++; 743 ioc->msingle_pages += size >> IOVP_SHIFT; 744 #endif 745 pide = sba_alloc_range(ioc, dev, size); 746 iovp = (dma_addr_t) pide << IOVP_SHIFT; 747 748 DBG_RUN("%s() 0x%p -> 0x%lx\n", 749 __func__, addr, (long) iovp | offset); 750 751 pdir_start = &(ioc->pdir_base[pide]); 752 753 while (size > 0) { 754 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); 755 756 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 757 pdir_start, 758 (u8) (((u8 *) pdir_start)[7]), 759 (u8) (((u8 *) pdir_start)[6]), 760 (u8) (((u8 *) pdir_start)[5]), 761 (u8) (((u8 *) pdir_start)[4]), 762 (u8) (((u8 *) pdir_start)[3]), 763 (u8) (((u8 *) pdir_start)[2]), 764 (u8) (((u8 *) pdir_start)[1]), 765 (u8) (((u8 *) pdir_start)[0]) 766 ); 767 768 addr += IOVP_SIZE; 769 size -= IOVP_SIZE; 770 pdir_start++; 771 } 772 773 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 774 asm_io_sync(); 775 776 #ifdef ASSERT_PDIR_SANITY 777 sba_check_pdir(ioc,"Check after sba_map_single()"); 778 #endif 779 spin_unlock_irqrestore(&ioc->res_lock, flags); 780 781 /* form complete address */ 782 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 783 } 784 785 786 static dma_addr_t 787 sba_map_page(struct device *dev, struct page *page, unsigned long offset, 788 size_t size, enum dma_data_direction direction, 789 unsigned long attrs) 790 { 791 return sba_map_single(dev, page_address(page) + offset, size, 792 direction); 793 } 794 795 796 /** 797 * sba_unmap_page - unmap one IOVA and free resources 798 * @dev: instance of PCI owned by the driver that's asking. 799 * @iova: IOVA of driver buffer previously mapped. 800 * @size: number of bytes mapped in driver buffer. 801 * @direction: R/W or both. 802 * 803 * See Documentation/DMA-API-HOWTO.txt 804 */ 805 static void 806 sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size, 807 enum dma_data_direction direction, unsigned long attrs) 808 { 809 struct ioc *ioc; 810 #if DELAYED_RESOURCE_CNT > 0 811 struct sba_dma_pair *d; 812 #endif 813 unsigned long flags; 814 dma_addr_t offset; 815 816 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); 817 818 ioc = GET_IOC(dev); 819 if (!ioc) { 820 WARN_ON(!ioc); 821 return; 822 } 823 offset = iova & ~IOVP_MASK; 824 iova ^= offset; /* clear offset bits */ 825 size += offset; 826 size = ALIGN(size, IOVP_SIZE); 827 828 spin_lock_irqsave(&ioc->res_lock, flags); 829 830 #ifdef SBA_COLLECT_STATS 831 ioc->usingle_calls++; 832 ioc->usingle_pages += size >> IOVP_SHIFT; 833 #endif 834 835 sba_mark_invalid(ioc, iova, size); 836 837 #if DELAYED_RESOURCE_CNT > 0 838 /* Delaying when we re-use a IO Pdir entry reduces the number 839 * of MMIO reads needed to flush writes to the PCOM register. 840 */ 841 d = &(ioc->saved[ioc->saved_cnt]); 842 d->iova = iova; 843 d->size = size; 844 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 845 int cnt = ioc->saved_cnt; 846 while (cnt--) { 847 sba_free_range(ioc, d->iova, d->size); 848 d--; 849 } 850 ioc->saved_cnt = 0; 851 852 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 853 } 854 #else /* DELAYED_RESOURCE_CNT == 0 */ 855 sba_free_range(ioc, iova, size); 856 857 /* If fdc's were issued, force fdc's to be visible now */ 858 asm_io_sync(); 859 860 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 861 #endif /* DELAYED_RESOURCE_CNT == 0 */ 862 863 spin_unlock_irqrestore(&ioc->res_lock, flags); 864 865 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 866 ** For Astro based systems this isn't a big deal WRT performance. 867 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 868 ** we don't need the syncdma. The issue here is I/O MMU cachelines 869 ** are *not* coherent in all cases. May be hwrev dependent. 870 ** Need to investigate more. 871 asm volatile("syncdma"); 872 */ 873 } 874 875 876 /** 877 * sba_alloc - allocate/map shared mem for DMA 878 * @hwdev: instance of PCI owned by the driver that's asking. 879 * @size: number of bytes mapped in driver buffer. 880 * @dma_handle: IOVA of new buffer. 881 * 882 * See Documentation/DMA-API-HOWTO.txt 883 */ 884 static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, 885 gfp_t gfp, unsigned long attrs) 886 { 887 void *ret; 888 889 if (!hwdev) { 890 /* only support PCI */ 891 *dma_handle = 0; 892 return NULL; 893 } 894 895 ret = (void *) __get_free_pages(gfp, get_order(size)); 896 897 if (ret) { 898 memset(ret, 0, size); 899 *dma_handle = sba_map_single(hwdev, ret, size, 0); 900 } 901 902 return ret; 903 } 904 905 906 /** 907 * sba_free - free/unmap shared mem for DMA 908 * @hwdev: instance of PCI owned by the driver that's asking. 909 * @size: number of bytes mapped in driver buffer. 910 * @vaddr: virtual address IOVA of "consistent" buffer. 911 * @dma_handler: IO virtual address of "consistent" buffer. 912 * 913 * See Documentation/DMA-API-HOWTO.txt 914 */ 915 static void 916 sba_free(struct device *hwdev, size_t size, void *vaddr, 917 dma_addr_t dma_handle, unsigned long attrs) 918 { 919 sba_unmap_page(hwdev, dma_handle, size, 0, 0); 920 free_pages((unsigned long) vaddr, get_order(size)); 921 } 922 923 924 /* 925 ** Since 0 is a valid pdir_base index value, can't use that 926 ** to determine if a value is valid or not. Use a flag to indicate 927 ** the SG list entry contains a valid pdir index. 928 */ 929 #define PIDE_FLAG 0x80000000UL 930 931 #ifdef SBA_COLLECT_STATS 932 #define IOMMU_MAP_STATS 933 #endif 934 #include "iommu-helpers.h" 935 936 #ifdef DEBUG_LARGE_SG_ENTRIES 937 int dump_run_sg = 0; 938 #endif 939 940 941 /** 942 * sba_map_sg - map Scatter/Gather list 943 * @dev: instance of PCI owned by the driver that's asking. 944 * @sglist: array of buffer/length pairs 945 * @nents: number of entries in list 946 * @direction: R/W or both. 947 * 948 * See Documentation/DMA-API-HOWTO.txt 949 */ 950 static int 951 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 952 enum dma_data_direction direction, unsigned long attrs) 953 { 954 struct ioc *ioc; 955 int coalesced, filled = 0; 956 unsigned long flags; 957 958 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 959 960 ioc = GET_IOC(dev); 961 if (!ioc) 962 return 0; 963 964 /* Fast path single entry scatterlists. */ 965 if (nents == 1) { 966 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist), 967 sglist->length, direction); 968 sg_dma_len(sglist) = sglist->length; 969 return 1; 970 } 971 972 spin_lock_irqsave(&ioc->res_lock, flags); 973 974 #ifdef ASSERT_PDIR_SANITY 975 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 976 { 977 sba_dump_sg(ioc, sglist, nents); 978 panic("Check before sba_map_sg()"); 979 } 980 #endif 981 982 #ifdef SBA_COLLECT_STATS 983 ioc->msg_calls++; 984 #endif 985 986 /* 987 ** First coalesce the chunks and allocate I/O pdir space 988 ** 989 ** If this is one DMA stream, we can properly map using the 990 ** correct virtual address associated with each DMA page. 991 ** w/o this association, we wouldn't have coherent DMA! 992 ** Access to the virtual address is what forces a two pass algorithm. 993 */ 994 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range); 995 996 /* 997 ** Program the I/O Pdir 998 ** 999 ** map the virtual addresses to the I/O Pdir 1000 ** o dma_address will contain the pdir index 1001 ** o dma_len will contain the number of bytes to map 1002 ** o address contains the virtual address. 1003 */ 1004 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 1005 1006 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 1007 asm_io_sync(); 1008 1009 #ifdef ASSERT_PDIR_SANITY 1010 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 1011 { 1012 sba_dump_sg(ioc, sglist, nents); 1013 panic("Check after sba_map_sg()\n"); 1014 } 1015 #endif 1016 1017 spin_unlock_irqrestore(&ioc->res_lock, flags); 1018 1019 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 1020 1021 return filled; 1022 } 1023 1024 1025 /** 1026 * sba_unmap_sg - unmap Scatter/Gather list 1027 * @dev: instance of PCI owned by the driver that's asking. 1028 * @sglist: array of buffer/length pairs 1029 * @nents: number of entries in list 1030 * @direction: R/W or both. 1031 * 1032 * See Documentation/DMA-API-HOWTO.txt 1033 */ 1034 static void 1035 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 1036 enum dma_data_direction direction, unsigned long attrs) 1037 { 1038 struct ioc *ioc; 1039 #ifdef ASSERT_PDIR_SANITY 1040 unsigned long flags; 1041 #endif 1042 1043 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1044 __func__, nents, sg_virt(sglist), sglist->length); 1045 1046 ioc = GET_IOC(dev); 1047 if (!ioc) { 1048 WARN_ON(!ioc); 1049 return; 1050 } 1051 1052 #ifdef SBA_COLLECT_STATS 1053 ioc->usg_calls++; 1054 #endif 1055 1056 #ifdef ASSERT_PDIR_SANITY 1057 spin_lock_irqsave(&ioc->res_lock, flags); 1058 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1059 spin_unlock_irqrestore(&ioc->res_lock, flags); 1060 #endif 1061 1062 while (sg_dma_len(sglist) && nents--) { 1063 1064 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist), 1065 direction, 0); 1066 #ifdef SBA_COLLECT_STATS 1067 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1068 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1069 #endif 1070 ++sglist; 1071 } 1072 1073 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1074 1075 #ifdef ASSERT_PDIR_SANITY 1076 spin_lock_irqsave(&ioc->res_lock, flags); 1077 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1078 spin_unlock_irqrestore(&ioc->res_lock, flags); 1079 #endif 1080 1081 } 1082 1083 static int sba_mapping_error(struct device *dev, dma_addr_t dma_addr) 1084 { 1085 return dma_addr == SBA_MAPPING_ERROR; 1086 } 1087 1088 static const struct dma_map_ops sba_ops = { 1089 .dma_supported = sba_dma_supported, 1090 .alloc = sba_alloc, 1091 .free = sba_free, 1092 .map_page = sba_map_page, 1093 .unmap_page = sba_unmap_page, 1094 .map_sg = sba_map_sg, 1095 .unmap_sg = sba_unmap_sg, 1096 .mapping_error = sba_mapping_error, 1097 }; 1098 1099 1100 /************************************************************************** 1101 ** 1102 ** SBA PAT PDC support 1103 ** 1104 ** o call pdc_pat_cell_module() 1105 ** o store ranges in PCI "resource" structures 1106 ** 1107 **************************************************************************/ 1108 1109 static void 1110 sba_get_pat_resources(struct sba_device *sba_dev) 1111 { 1112 #if 0 1113 /* 1114 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1115 ** PAT PDC to program the SBA/LBA directed range registers...this 1116 ** burden may fall on the LBA code since it directly supports the 1117 ** PCI subsystem. It's not clear yet. - ggg 1118 */ 1119 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1120 FIXME : ??? 1121 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1122 Tells where the dvi bits are located in the address. 1123 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1124 FIXME : ??? 1125 #endif 1126 } 1127 1128 1129 /************************************************************** 1130 * 1131 * Initialization and claim 1132 * 1133 ***************************************************************/ 1134 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1135 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1136 static void * 1137 sba_alloc_pdir(unsigned int pdir_size) 1138 { 1139 unsigned long pdir_base; 1140 unsigned long pdir_order = get_order(pdir_size); 1141 1142 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1143 if (NULL == (void *) pdir_base) { 1144 panic("%s() could not allocate I/O Page Table\n", 1145 __func__); 1146 } 1147 1148 /* If this is not PA8700 (PCX-W2) 1149 ** OR newer than ver 2.2 1150 ** OR in a system that doesn't need VINDEX bits from SBA, 1151 ** 1152 ** then we aren't exposed to the HW bug. 1153 */ 1154 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1155 || (boot_cpu_data.pdc.versions > 0x202) 1156 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1157 return (void *) pdir_base; 1158 1159 /* 1160 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1161 * 1162 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1163 * Ike/Astro can cause silent data corruption. This is only 1164 * a problem if the I/O PDIR is located in memory such that 1165 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1166 * 1167 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1168 * right physical address, we can either avoid (IOPDIR <= 1MB) 1169 * or minimize (2MB IO Pdir) the problem if we restrict the 1170 * IO Pdir to a maximum size of 2MB-128K (1902K). 1171 * 1172 * Because we always allocate 2^N sized IO pdirs, either of the 1173 * "bad" regions will be the last 128K if at all. That's easy 1174 * to test for. 1175 * 1176 */ 1177 if (pdir_order <= (19-12)) { 1178 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1179 /* allocate a new one on 512k alignment */ 1180 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1181 /* release original */ 1182 free_pages(pdir_base, pdir_order); 1183 1184 pdir_base = new_pdir; 1185 1186 /* release excess */ 1187 while (pdir_order < (19-12)) { 1188 new_pdir += pdir_size; 1189 free_pages(new_pdir, pdir_order); 1190 pdir_order +=1; 1191 pdir_size <<=1; 1192 } 1193 } 1194 } else { 1195 /* 1196 ** 1MB or 2MB Pdir 1197 ** Needs to be aligned on an "odd" 1MB boundary. 1198 */ 1199 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1200 1201 /* release original */ 1202 free_pages( pdir_base, pdir_order); 1203 1204 /* release first 1MB */ 1205 free_pages(new_pdir, 20-12); 1206 1207 pdir_base = new_pdir + 1024*1024; 1208 1209 if (pdir_order > (20-12)) { 1210 /* 1211 ** 2MB Pdir. 1212 ** 1213 ** Flag tells init_bitmap() to mark bad 128k as used 1214 ** and to reduce the size by 128k. 1215 */ 1216 piranha_bad_128k = 1; 1217 1218 new_pdir += 3*1024*1024; 1219 /* release last 1MB */ 1220 free_pages(new_pdir, 20-12); 1221 1222 /* release unusable 128KB */ 1223 free_pages(new_pdir - 128*1024 , 17-12); 1224 1225 pdir_size -= 128*1024; 1226 } 1227 } 1228 1229 memset((void *) pdir_base, 0, pdir_size); 1230 return (void *) pdir_base; 1231 } 1232 1233 struct ibase_data_struct { 1234 struct ioc *ioc; 1235 int ioc_num; 1236 }; 1237 1238 static int setup_ibase_imask_callback(struct device *dev, void *data) 1239 { 1240 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ 1241 extern void lba_set_iregs(struct parisc_device *, u32, u32); 1242 struct parisc_device *lba = to_parisc_device(dev); 1243 struct ibase_data_struct *ibd = data; 1244 int rope_num = (lba->hpa.start >> 13) & 0xf; 1245 if (rope_num >> 3 == ibd->ioc_num) 1246 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); 1247 return 0; 1248 } 1249 1250 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1251 static void 1252 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1253 { 1254 struct ibase_data_struct ibase_data = { 1255 .ioc = ioc, 1256 .ioc_num = ioc_num, 1257 }; 1258 1259 device_for_each_child(&sba->dev, &ibase_data, 1260 setup_ibase_imask_callback); 1261 } 1262 1263 #ifdef SBA_AGP_SUPPORT 1264 static int 1265 sba_ioc_find_quicksilver(struct device *dev, void *data) 1266 { 1267 int *agp_found = data; 1268 struct parisc_device *lba = to_parisc_device(dev); 1269 1270 if (IS_QUICKSILVER(lba)) 1271 *agp_found = 1; 1272 return 0; 1273 } 1274 #endif 1275 1276 static void 1277 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1278 { 1279 u32 iova_space_mask; 1280 u32 iova_space_size; 1281 int iov_order, tcnfg; 1282 #ifdef SBA_AGP_SUPPORT 1283 int agp_found = 0; 1284 #endif 1285 /* 1286 ** Firmware programs the base and size of a "safe IOVA space" 1287 ** (one that doesn't overlap memory or LMMIO space) in the 1288 ** IBASE and IMASK registers. 1289 */ 1290 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE); 1291 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1292 1293 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1294 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1295 iova_space_size /= 2; 1296 } 1297 1298 /* 1299 ** iov_order is always based on a 1GB IOVA space since we want to 1300 ** turn on the other half for AGP GART. 1301 */ 1302 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1303 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1304 1305 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1306 __func__, ioc->ioc_hpa, iova_space_size >> 20, 1307 iov_order + PAGE_SHIFT); 1308 1309 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1310 get_order(ioc->pdir_size)); 1311 if (!ioc->pdir_base) 1312 panic("Couldn't allocate I/O Page Table\n"); 1313 1314 memset(ioc->pdir_base, 0, ioc->pdir_size); 1315 1316 DBG_INIT("%s() pdir %p size %x\n", 1317 __func__, ioc->pdir_base, ioc->pdir_size); 1318 1319 #ifdef SBA_HINT_SUPPORT 1320 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1321 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1322 1323 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1324 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1325 #endif 1326 1327 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1328 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1329 1330 /* build IMASK for IOC and Elroy */ 1331 iova_space_mask = 0xffffffff; 1332 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1333 ioc->imask = iova_space_mask; 1334 #ifdef ZX1_SUPPORT 1335 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1336 #endif 1337 sba_dump_tlb(ioc->ioc_hpa); 1338 1339 setup_ibase_imask(sba, ioc, ioc_num); 1340 1341 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1342 1343 #ifdef CONFIG_64BIT 1344 /* 1345 ** Setting the upper bits makes checking for bypass addresses 1346 ** a little faster later on. 1347 */ 1348 ioc->imask |= 0xFFFFFFFF00000000UL; 1349 #endif 1350 1351 /* Set I/O PDIR Page size to system page size */ 1352 switch (PAGE_SHIFT) { 1353 case 12: tcnfg = 0; break; /* 4K */ 1354 case 13: tcnfg = 1; break; /* 8K */ 1355 case 14: tcnfg = 2; break; /* 16K */ 1356 case 16: tcnfg = 3; break; /* 64K */ 1357 default: 1358 panic(__FILE__ "Unsupported system page size %d", 1359 1 << PAGE_SHIFT); 1360 break; 1361 } 1362 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1363 1364 /* 1365 ** Program the IOC's ibase and enable IOVA translation 1366 ** Bit zero == enable bit. 1367 */ 1368 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1369 1370 /* 1371 ** Clear I/O TLB of any possible entries. 1372 ** (Yes. This is a bit paranoid...but so what) 1373 */ 1374 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1375 1376 #ifdef SBA_AGP_SUPPORT 1377 1378 /* 1379 ** If an AGP device is present, only use half of the IOV space 1380 ** for PCI DMA. Unfortunately we can't know ahead of time 1381 ** whether GART support will actually be used, for now we 1382 ** can just key on any AGP device found in the system. 1383 ** We program the next pdir index after we stop w/ a key for 1384 ** the GART code to handshake on. 1385 */ 1386 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); 1387 1388 if (agp_found && sba_reserve_agpgart) { 1389 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", 1390 __func__, (iova_space_size/2) >> 20); 1391 ioc->pdir_size /= 2; 1392 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; 1393 } 1394 #endif /*SBA_AGP_SUPPORT*/ 1395 } 1396 1397 static void 1398 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1399 { 1400 u32 iova_space_size, iova_space_mask; 1401 unsigned int pdir_size, iov_order, tcnfg; 1402 1403 /* 1404 ** Determine IOVA Space size from memory size. 1405 ** 1406 ** Ideally, PCI drivers would register the maximum number 1407 ** of DMA they can have outstanding for each device they 1408 ** own. Next best thing would be to guess how much DMA 1409 ** can be outstanding based on PCI Class/sub-class. Both 1410 ** methods still require some "extra" to support PCI 1411 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1412 ** 1413 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1414 ** for DMA hints - ergo only 30 bits max. 1415 */ 1416 1417 iova_space_size = (u32) (totalram_pages/global_ioc_cnt); 1418 1419 /* limit IOVA space size to 1MB-1GB */ 1420 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1421 iova_space_size = 1 << (20 - PAGE_SHIFT); 1422 } 1423 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1424 iova_space_size = 1 << (30 - PAGE_SHIFT); 1425 } 1426 1427 /* 1428 ** iova space must be log2() in size. 1429 ** thus, pdir/res_map will also be log2(). 1430 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1431 */ 1432 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1433 1434 /* iova_space_size is now bytes, not pages */ 1435 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1436 1437 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1438 1439 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", 1440 __func__, 1441 ioc->ioc_hpa, 1442 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT), 1443 iova_space_size>>20, 1444 iov_order + PAGE_SHIFT); 1445 1446 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1447 1448 DBG_INIT("%s() pdir %p size %x\n", 1449 __func__, ioc->pdir_base, pdir_size); 1450 1451 #ifdef SBA_HINT_SUPPORT 1452 /* FIXME : DMA HINTs not used */ 1453 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1454 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1455 1456 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1457 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1458 #endif 1459 1460 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1461 1462 /* build IMASK for IOC and Elroy */ 1463 iova_space_mask = 0xffffffff; 1464 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1465 1466 /* 1467 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1468 ** ibase=0, imask=0xFE000000, size=0x2000000. 1469 */ 1470 ioc->ibase = 0; 1471 ioc->imask = iova_space_mask; /* save it */ 1472 #ifdef ZX1_SUPPORT 1473 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1474 #endif 1475 1476 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", 1477 __func__, ioc->ibase, ioc->imask); 1478 1479 /* 1480 ** FIXME: Hint registers are programmed with default hint 1481 ** values during boot, so hints should be sane even if we 1482 ** can't reprogram them the way drivers want. 1483 */ 1484 1485 setup_ibase_imask(sba, ioc, ioc_num); 1486 1487 /* 1488 ** Program the IOC's ibase and enable IOVA translation 1489 */ 1490 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1491 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1492 1493 /* Set I/O PDIR Page size to system page size */ 1494 switch (PAGE_SHIFT) { 1495 case 12: tcnfg = 0; break; /* 4K */ 1496 case 13: tcnfg = 1; break; /* 8K */ 1497 case 14: tcnfg = 2; break; /* 16K */ 1498 case 16: tcnfg = 3; break; /* 64K */ 1499 default: 1500 panic(__FILE__ "Unsupported system page size %d", 1501 1 << PAGE_SHIFT); 1502 break; 1503 } 1504 /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */ 1505 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG); 1506 1507 /* 1508 ** Clear I/O TLB of any possible entries. 1509 ** (Yes. This is a bit paranoid...but so what) 1510 */ 1511 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1512 1513 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1514 1515 DBG_INIT("%s() DONE\n", __func__); 1516 } 1517 1518 1519 1520 /************************************************************************** 1521 ** 1522 ** SBA initialization code (HW and SW) 1523 ** 1524 ** o identify SBA chip itself 1525 ** o initialize SBA chip modes (HardFail) 1526 ** o initialize SBA chip modes (HardFail) 1527 ** o FIXME: initialize DMA hints for reasonable defaults 1528 ** 1529 **************************************************************************/ 1530 1531 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1532 { 1533 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1534 } 1535 1536 static void sba_hw_init(struct sba_device *sba_dev) 1537 { 1538 int i; 1539 int num_ioc; 1540 u64 ioc_ctl; 1541 1542 if (!is_pdc_pat()) { 1543 /* Shutdown the USB controller on Astro-based workstations. 1544 ** Once we reprogram the IOMMU, the next DMA performed by 1545 ** USB will HPMC the box. USB is only enabled if a 1546 ** keyboard is present and found. 1547 ** 1548 ** With serial console, j6k v5.0 firmware says: 1549 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1550 ** 1551 ** FIXME: Using GFX+USB console at power up but direct 1552 ** linux to serial console is still broken. 1553 ** USB could generate DMA so we must reset USB. 1554 ** The proper sequence would be: 1555 ** o block console output 1556 ** o reset USB device 1557 ** o reprogram serial port 1558 ** o unblock console output 1559 */ 1560 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1561 pdc_io_reset_devices(); 1562 } 1563 1564 } 1565 1566 1567 #if 0 1568 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1569 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1570 1571 /* 1572 ** Need to deal with DMA from LAN. 1573 ** Maybe use page zero boot device as a handle to talk 1574 ** to PDC about which device to shutdown. 1575 ** 1576 ** Netbooting, j6k v5.0 firmware says: 1577 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1578 ** ARGH! invalid class. 1579 */ 1580 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1581 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1582 pdc_io_reset(); 1583 } 1584 #endif 1585 1586 if (!IS_PLUTO(sba_dev->dev)) { 1587 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1588 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", 1589 __func__, sba_dev->sba_hpa, ioc_ctl); 1590 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1591 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1592 /* j6700 v1.6 firmware sets 0x294f */ 1593 /* A500 firmware sets 0x4d */ 1594 1595 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1596 1597 #ifdef DEBUG_SBA_INIT 1598 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1599 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1600 #endif 1601 } /* if !PLUTO */ 1602 1603 if (IS_ASTRO(sba_dev->dev)) { 1604 int err; 1605 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1606 num_ioc = 1; 1607 1608 sba_dev->chip_resv.name = "Astro Intr Ack"; 1609 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1610 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1611 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1612 BUG_ON(err < 0); 1613 1614 } else if (IS_PLUTO(sba_dev->dev)) { 1615 int err; 1616 1617 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1618 num_ioc = 1; 1619 1620 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1621 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1622 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1623 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1624 WARN_ON(err < 0); 1625 1626 sba_dev->iommu_resv.name = "IOVA Space"; 1627 sba_dev->iommu_resv.start = 0x40000000UL; 1628 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1629 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1630 WARN_ON(err < 0); 1631 } else { 1632 /* IKE, REO */ 1633 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1634 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1635 num_ioc = 2; 1636 1637 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1638 } 1639 /* XXX: What about Reo Grande? */ 1640 1641 sba_dev->num_ioc = num_ioc; 1642 for (i = 0; i < num_ioc; i++) { 1643 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1644 unsigned int j; 1645 1646 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1647 1648 /* 1649 * Clear ROPE(N)_CONFIG AO bit. 1650 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1651 * Overrides bit 1 in DMA Hint Sets. 1652 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1653 */ 1654 if (IS_PLUTO(sba_dev->dev)) { 1655 void __iomem *rope_cfg; 1656 unsigned long cfg_val; 1657 1658 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1659 cfg_val = READ_REG(rope_cfg); 1660 cfg_val &= ~IOC_ROPE_AO; 1661 WRITE_REG(cfg_val, rope_cfg); 1662 } 1663 1664 /* 1665 ** Make sure the box crashes on rope errors. 1666 */ 1667 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1668 } 1669 1670 /* flush out the last writes */ 1671 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1672 1673 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", 1674 i, 1675 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1676 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1677 ); 1678 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", 1679 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1680 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1681 ); 1682 1683 if (IS_PLUTO(sba_dev->dev)) { 1684 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1685 } else { 1686 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1687 } 1688 } 1689 } 1690 1691 static void 1692 sba_common_init(struct sba_device *sba_dev) 1693 { 1694 int i; 1695 1696 /* add this one to the head of the list (order doesn't matter) 1697 ** This will be useful for debugging - especially if we get coredumps 1698 */ 1699 sba_dev->next = sba_list; 1700 sba_list = sba_dev; 1701 1702 for(i=0; i< sba_dev->num_ioc; i++) { 1703 int res_size; 1704 #ifdef DEBUG_DMB_TRAP 1705 extern void iterate_pages(unsigned long , unsigned long , 1706 void (*)(pte_t * , unsigned long), 1707 unsigned long ); 1708 void set_data_memory_break(pte_t * , unsigned long); 1709 #endif 1710 /* resource map size dictated by pdir_size */ 1711 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1712 1713 /* Second part of PIRANHA BUG */ 1714 if (piranha_bad_128k) { 1715 res_size -= (128*1024)/sizeof(u64); 1716 } 1717 1718 res_size >>= 3; /* convert bit count to byte count */ 1719 DBG_INIT("%s() res_size 0x%x\n", 1720 __func__, res_size); 1721 1722 sba_dev->ioc[i].res_size = res_size; 1723 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1724 1725 #ifdef DEBUG_DMB_TRAP 1726 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1727 set_data_memory_break, 0); 1728 #endif 1729 1730 if (NULL == sba_dev->ioc[i].res_map) 1731 { 1732 panic("%s:%s() could not allocate resource map\n", 1733 __FILE__, __func__ ); 1734 } 1735 1736 memset(sba_dev->ioc[i].res_map, 0, res_size); 1737 /* next available IOVP - circular search */ 1738 sba_dev->ioc[i].res_hint = (unsigned long *) 1739 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1740 1741 #ifdef ASSERT_PDIR_SANITY 1742 /* Mark first bit busy - ie no IOVA 0 */ 1743 sba_dev->ioc[i].res_map[0] = 0x80; 1744 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; 1745 #endif 1746 1747 /* Third (and last) part of PIRANHA BUG */ 1748 if (piranha_bad_128k) { 1749 /* region from +1408K to +1536 is un-usable. */ 1750 1751 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1752 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1753 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1754 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1755 1756 /* mark that part of the io pdir busy */ 1757 while (p_start < p_end) 1758 *p_start++ = -1; 1759 1760 } 1761 1762 #ifdef DEBUG_DMB_TRAP 1763 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1764 set_data_memory_break, 0); 1765 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1766 set_data_memory_break, 0); 1767 #endif 1768 1769 DBG_INIT("%s() %d res_map %x %p\n", 1770 __func__, i, res_size, sba_dev->ioc[i].res_map); 1771 } 1772 1773 spin_lock_init(&sba_dev->sba_lock); 1774 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1775 1776 #ifdef DEBUG_SBA_INIT 1777 /* 1778 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1779 * (bit #61, big endian), we have to flush and sync every time 1780 * IO-PDIR is changed in Ike/Astro. 1781 */ 1782 if (ioc_needs_fdc) { 1783 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1784 } else { 1785 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1786 } 1787 #endif 1788 } 1789 1790 #ifdef CONFIG_PROC_FS 1791 static int sba_proc_info(struct seq_file *m, void *p) 1792 { 1793 struct sba_device *sba_dev = sba_list; 1794 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1795 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1796 #ifdef SBA_COLLECT_STATS 1797 unsigned long avg = 0, min, max; 1798 #endif 1799 int i; 1800 1801 seq_printf(m, "%s rev %d.%d\n", 1802 sba_dev->name, 1803 (sba_dev->hw_rev & 0x7) + 1, 1804 (sba_dev->hw_rev & 0x18) >> 3); 1805 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1806 (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1807 total_pages); 1808 1809 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1810 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1811 1812 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1813 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1814 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1815 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)); 1816 1817 for (i=0; i<4; i++) 1818 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", 1819 i, 1820 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1821 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1822 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)); 1823 1824 #ifdef SBA_COLLECT_STATS 1825 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1826 total_pages - ioc->used_pages, ioc->used_pages, 1827 (int)(ioc->used_pages * 100 / total_pages)); 1828 1829 min = max = ioc->avg_search[0]; 1830 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1831 avg += ioc->avg_search[i]; 1832 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1833 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1834 } 1835 avg /= SBA_SEARCH_SAMPLE; 1836 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1837 min, avg, max); 1838 1839 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1840 ioc->msingle_calls, ioc->msingle_pages, 1841 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1842 1843 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1844 min = ioc->usingle_calls; 1845 max = ioc->usingle_pages - ioc->usg_pages; 1846 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1847 min, max, (int)((max * 1000)/min)); 1848 1849 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1850 ioc->msg_calls, ioc->msg_pages, 1851 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1852 1853 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1854 ioc->usg_calls, ioc->usg_pages, 1855 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1856 #endif 1857 1858 return 0; 1859 } 1860 1861 static int 1862 sba_proc_bitmap_info(struct seq_file *m, void *p) 1863 { 1864 struct sba_device *sba_dev = sba_list; 1865 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1866 1867 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, 1868 ioc->res_size, false); 1869 seq_putc(m, '\n'); 1870 1871 return 0; 1872 } 1873 #endif /* CONFIG_PROC_FS */ 1874 1875 static const struct parisc_device_id sba_tbl[] __initconst = { 1876 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1877 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1878 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1879 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1880 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1881 { 0, } 1882 }; 1883 1884 static int sba_driver_callback(struct parisc_device *); 1885 1886 static struct parisc_driver sba_driver __refdata = { 1887 .name = MODULE_NAME, 1888 .id_table = sba_tbl, 1889 .probe = sba_driver_callback, 1890 }; 1891 1892 /* 1893 ** Determine if sba should claim this chip (return 0) or not (return 1). 1894 ** If so, initialize the chip and tell other partners in crime they 1895 ** have work to do. 1896 */ 1897 static int __init sba_driver_callback(struct parisc_device *dev) 1898 { 1899 struct sba_device *sba_dev; 1900 u32 func_class; 1901 int i; 1902 char *version; 1903 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE); 1904 #ifdef CONFIG_PROC_FS 1905 struct proc_dir_entry *root; 1906 #endif 1907 1908 sba_dump_ranges(sba_addr); 1909 1910 /* Read HW Rev First */ 1911 func_class = READ_REG(sba_addr + SBA_FCLASS); 1912 1913 if (IS_ASTRO(dev)) { 1914 unsigned long fclass; 1915 static char astro_rev[]="Astro ?.?"; 1916 1917 /* Astro is broken...Read HW Rev First */ 1918 fclass = READ_REG(sba_addr); 1919 1920 astro_rev[6] = '1' + (char) (fclass & 0x7); 1921 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1922 version = astro_rev; 1923 1924 } else if (IS_IKE(dev)) { 1925 static char ike_rev[] = "Ike rev ?"; 1926 ike_rev[8] = '0' + (char) (func_class & 0xff); 1927 version = ike_rev; 1928 } else if (IS_PLUTO(dev)) { 1929 static char pluto_rev[]="Pluto ?.?"; 1930 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1931 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1932 version = pluto_rev; 1933 } else { 1934 static char reo_rev[] = "REO rev ?"; 1935 reo_rev[8] = '0' + (char) (func_class & 0xff); 1936 version = reo_rev; 1937 } 1938 1939 if (!global_ioc_cnt) { 1940 global_ioc_cnt = count_parisc_driver(&sba_driver); 1941 1942 /* Astro and Pluto have one IOC per SBA */ 1943 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1944 global_ioc_cnt *= 2; 1945 } 1946 1947 printk(KERN_INFO "%s found %s at 0x%llx\n", 1948 MODULE_NAME, version, (unsigned long long)dev->hpa.start); 1949 1950 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 1951 if (!sba_dev) { 1952 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1953 return -ENOMEM; 1954 } 1955 1956 parisc_set_drvdata(dev, sba_dev); 1957 1958 for(i=0; i<MAX_IOC; i++) 1959 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1960 1961 sba_dev->dev = dev; 1962 sba_dev->hw_rev = func_class; 1963 sba_dev->name = dev->name; 1964 sba_dev->sba_hpa = sba_addr; 1965 1966 sba_get_pat_resources(sba_dev); 1967 sba_hw_init(sba_dev); 1968 sba_common_init(sba_dev); 1969 1970 hppa_dma_ops = &sba_ops; 1971 1972 #ifdef CONFIG_PROC_FS 1973 switch (dev->id.hversion) { 1974 case PLUTO_MCKINLEY_PORT: 1975 root = proc_mckinley_root; 1976 break; 1977 case ASTRO_RUNWAY_PORT: 1978 case IKE_MERCED_PORT: 1979 default: 1980 root = proc_runway_root; 1981 break; 1982 } 1983 1984 proc_create_single("sba_iommu", 0, root, sba_proc_info); 1985 proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info); 1986 #endif 1987 return 0; 1988 } 1989 1990 /* 1991 ** One time initialization to let the world know the SBA was found. 1992 ** This is the only routine which is NOT static. 1993 ** Must be called exactly once before pci_init(). 1994 */ 1995 void __init sba_init(void) 1996 { 1997 register_parisc_driver(&sba_driver); 1998 } 1999 2000 2001 /** 2002 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 2003 * @dev: The parisc device. 2004 * 2005 * Returns the appropriate IOMMU data for the given parisc PCI controller. 2006 * This is cached and used later for PCI DMA Mapping. 2007 */ 2008 void * sba_get_iommu(struct parisc_device *pci_hba) 2009 { 2010 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2011 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2012 char t = sba_dev->id.hw_type; 2013 int iocnum = (pci_hba->hw_path >> 3); /* rope # */ 2014 2015 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 2016 2017 return &(sba->ioc[iocnum]); 2018 } 2019 2020 2021 /** 2022 * sba_directed_lmmio - return first directed LMMIO range routed to rope 2023 * @pa_dev: The parisc device. 2024 * @r: resource PCI host controller wants start/end fields assigned. 2025 * 2026 * For the given parisc PCI controller, determine if any direct ranges 2027 * are routed down the corresponding rope. 2028 */ 2029 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 2030 { 2031 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2032 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2033 char t = sba_dev->id.hw_type; 2034 int i; 2035 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2036 2037 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2038 2039 r->start = r->end = 0; 2040 2041 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2042 for (i=0; i<4; i++) { 2043 int base, size; 2044 void __iomem *reg = sba->sba_hpa + i*0x18; 2045 2046 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2047 if ((base & 1) == 0) 2048 continue; /* not enabled */ 2049 2050 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2051 2052 if ((size & (ROPES_PER_IOC-1)) != rope) 2053 continue; /* directed down different rope */ 2054 2055 r->start = (base & ~1UL) | PCI_F_EXTEND; 2056 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2057 r->end = r->start + size; 2058 r->flags = IORESOURCE_MEM; 2059 } 2060 } 2061 2062 2063 /** 2064 * sba_distributed_lmmio - return portion of distributed LMMIO range 2065 * @pa_dev: The parisc device. 2066 * @r: resource PCI host controller wants start/end fields assigned. 2067 * 2068 * For the given parisc PCI controller, return portion of distributed LMMIO 2069 * range. The distributed LMMIO is always present and it's just a question 2070 * of the base address and size of the range. 2071 */ 2072 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2073 { 2074 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2075 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev); 2076 char t = sba_dev->id.hw_type; 2077 int base, size; 2078 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2079 2080 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2081 2082 r->start = r->end = 0; 2083 2084 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2085 if ((base & 1) == 0) { 2086 BUG(); /* Gah! Distr Range wasn't enabled! */ 2087 return; 2088 } 2089 2090 r->start = (base & ~1UL) | PCI_F_EXTEND; 2091 2092 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2093 r->start += rope * (size + 1); /* adjust base for this rope */ 2094 r->end = r->start + size; 2095 r->flags = IORESOURCE_MEM; 2096 } 2097