1 /* 2 ** 3 ** PCI Lower Bus Adapter (LBA) manager 4 ** 5 ** (c) Copyright 1999,2000 Grant Grundler 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** 8 ** This program is free software; you can redistribute it and/or modify 9 ** it under the terms of the GNU General Public License as published by 10 ** the Free Software Foundation; either version 2 of the License, or 11 ** (at your option) any later version. 12 ** 13 ** 14 ** This module primarily provides access to PCI bus (config/IOport 15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class 16 ** with 4 digit model numbers - eg C3000 (and A400...sigh). 17 ** 18 ** LBA driver isn't as simple as the Dino driver because: 19 ** (a) this chip has substantial bug fixes between revisions 20 ** (Only one Dino bug has a software workaround :^( ) 21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD) 22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver) 23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC). 24 ** (dino only deals with "Legacy" PDC) 25 ** 26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver. 27 ** (I/O SAPIC is integratd in the LBA chip). 28 ** 29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets 30 ** FIXME: Add support for PCI card hot-plug (OLARD). 31 */ 32 33 #include <linux/delay.h> 34 #include <linux/types.h> 35 #include <linux/kernel.h> 36 #include <linux/spinlock.h> 37 #include <linux/init.h> /* for __init and __devinit */ 38 #include <linux/pci.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/smp_lock.h> 42 43 #include <asm/byteorder.h> 44 #include <asm/pdc.h> 45 #include <asm/pdcpat.h> 46 #include <asm/page.h> 47 #include <asm/system.h> 48 49 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 50 #include <asm/parisc-device.h> 51 #include <asm/iosapic.h> /* for iosapic_register() */ 52 #include <asm/io.h> /* read/write stuff */ 53 54 #undef DEBUG_LBA /* general stuff */ 55 #undef DEBUG_LBA_PORT /* debug I/O Port access */ 56 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */ 57 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */ 58 59 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */ 60 61 62 #ifdef DEBUG_LBA 63 #define DBG(x...) printk(x) 64 #else 65 #define DBG(x...) 66 #endif 67 68 #ifdef DEBUG_LBA_PORT 69 #define DBG_PORT(x...) printk(x) 70 #else 71 #define DBG_PORT(x...) 72 #endif 73 74 #ifdef DEBUG_LBA_CFG 75 #define DBG_CFG(x...) printk(x) 76 #else 77 #define DBG_CFG(x...) 78 #endif 79 80 #ifdef DEBUG_LBA_PAT 81 #define DBG_PAT(x...) printk(x) 82 #else 83 #define DBG_PAT(x...) 84 #endif 85 86 87 /* 88 ** Config accessor functions only pass in the 8-bit bus number and not 89 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus 90 ** number based on what firmware wrote into the scratch register. 91 ** 92 ** The "secondary" bus number is set to this before calling 93 ** pci_register_ops(). If any PPB's are present, the scan will 94 ** discover them and update the "secondary" and "subordinate" 95 ** fields in the pci_bus structure. 96 ** 97 ** Changes in the configuration *may* result in a different 98 ** bus number for each LBA depending on what firmware does. 99 */ 100 101 #define MODULE_NAME "LBA" 102 103 #define LBA_FUNC_ID 0x0000 /* function id */ 104 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 105 #define LBA_CAPABLE 0x0030 /* capabilities register */ 106 107 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */ 108 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */ 109 110 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */ 111 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */ 112 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */ 113 114 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */ 115 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */ 116 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */ 117 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */ 118 119 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */ 120 121 #define LBA_STAT_CTL 0x0108 /* Status & Control */ 122 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */ 123 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */ 124 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */ 125 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */ 126 127 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */ 128 #define LBA_LMMIO_MASK 0x0208 129 130 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */ 131 #define LBA_GMMIO_MASK 0x0218 132 133 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */ 134 #define LBA_WLMMIO_MASK 0x0228 135 136 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */ 137 #define LBA_WGMMIO_MASK 0x0238 138 139 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */ 140 #define LBA_IOS_MASK 0x0248 141 142 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */ 143 #define LBA_ELMMIO_MASK 0x0258 144 145 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */ 146 #define LBA_EIOS_MASK 0x0268 147 148 #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */ 149 #define LBA_DMA_CTL 0x0278 /* firmware sets this */ 150 151 #define LBA_IBASE 0x0300 /* SBA DMA support */ 152 #define LBA_IMASK 0x0308 153 154 /* FIXME: ignore DMA Hint stuff until we can measure performance */ 155 #define LBA_HINT_CFG 0x0310 156 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */ 157 158 #define LBA_BUS_MODE 0x0620 159 160 /* ERROR regs are needed for config cycle kluges */ 161 #define LBA_ERROR_CONFIG 0x0680 162 #define LBA_SMART_MODE 0x20 163 #define LBA_ERROR_STATUS 0x0688 164 #define LBA_ROPE_CTL 0x06A0 165 166 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */ 167 168 /* non-postable I/O port space, densely packed */ 169 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) 170 static void __iomem *astro_iop_base; 171 172 #define ELROY_HVERS 0x782 173 #define MERCURY_HVERS 0x783 174 #define QUICKSILVER_HVERS 0x784 175 176 static inline int IS_ELROY(struct parisc_device *d) 177 { 178 return (d->id.hversion == ELROY_HVERS); 179 } 180 181 static inline int IS_MERCURY(struct parisc_device *d) 182 { 183 return (d->id.hversion == MERCURY_HVERS); 184 } 185 186 static inline int IS_QUICKSILVER(struct parisc_device *d) 187 { 188 return (d->id.hversion == QUICKSILVER_HVERS); 189 } 190 191 192 /* 193 ** lba_device: Per instance Elroy data structure 194 */ 195 struct lba_device { 196 struct pci_hba_data hba; 197 198 spinlock_t lba_lock; 199 void *iosapic_obj; 200 201 #ifdef CONFIG_64BIT 202 void __iomem * iop_base; /* PA_VIEW - for IO port accessor funcs */ 203 #endif 204 205 int flags; /* state/functionality enabled */ 206 int hw_rev; /* HW revision of chip */ 207 }; 208 209 210 static u32 lba_t32; 211 212 /* lba flags */ 213 #define LBA_FLAG_SKIP_PROBE 0x10 214 215 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE) 216 217 218 /* Looks nice and keeps the compiler happy */ 219 #define LBA_DEV(d) ((struct lba_device *) (d)) 220 221 222 /* 223 ** Only allow 8 subsidiary busses per LBA 224 ** Problem is the PCI bus numbering is globally shared. 225 */ 226 #define LBA_MAX_NUM_BUSES 8 227 228 /************************************ 229 * LBA register read and write support 230 * 231 * BE WARNED: register writes are posted. 232 * (ie follow writes which must reach HW with a read) 233 */ 234 #define READ_U8(addr) __raw_readb(addr) 235 #define READ_U16(addr) __raw_readw(addr) 236 #define READ_U32(addr) __raw_readl(addr) 237 #define WRITE_U8(value, addr) __raw_writeb(value, addr) 238 #define WRITE_U16(value, addr) __raw_writew(value, addr) 239 #define WRITE_U32(value, addr) __raw_writel(value, addr) 240 241 #define READ_REG8(addr) readb(addr) 242 #define READ_REG16(addr) readw(addr) 243 #define READ_REG32(addr) readl(addr) 244 #define READ_REG64(addr) readq(addr) 245 #define WRITE_REG8(value, addr) writeb(value, addr) 246 #define WRITE_REG16(value, addr) writew(value, addr) 247 #define WRITE_REG32(value, addr) writel(value, addr) 248 249 250 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8)) 251 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16)) 252 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f) 253 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7) 254 255 256 /* 257 ** Extract LBA (Rope) number from HPA 258 ** REVISIT: 16 ropes for Stretch/Ike? 259 */ 260 #define ROPES_PER_IOC 8 261 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1)) 262 263 264 static void 265 lba_dump_res(struct resource *r, int d) 266 { 267 int i; 268 269 if (NULL == r) 270 return; 271 272 printk(KERN_DEBUG "(%p)", r->parent); 273 for (i = d; i ; --i) printk(" "); 274 printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r, r->start, r->end, r->flags); 275 lba_dump_res(r->child, d+2); 276 lba_dump_res(r->sibling, d); 277 } 278 279 280 /* 281 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex 282 ** workaround for cfg cycles: 283 ** -- preserve LBA state 284 ** -- prevent any DMA from occurring 285 ** -- turn on smart mode 286 ** -- probe with config writes before doing config reads 287 ** -- check ERROR_STATUS 288 ** -- clear ERROR_STATUS 289 ** -- restore LBA state 290 ** 291 ** The workaround is only used for device discovery. 292 */ 293 294 static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d) 295 { 296 u8 first_bus = d->hba.hba_bus->secondary; 297 u8 last_sub_bus = d->hba.hba_bus->subordinate; 298 299 if ((bus < first_bus) || 300 (bus > last_sub_bus) || 301 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) { 302 return 0; 303 } 304 305 return 1; 306 } 307 308 309 310 #define LBA_CFG_SETUP(d, tok) { \ 311 /* Save contents of error config register. */ \ 312 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \ 313 \ 314 /* Save contents of status control register. */ \ 315 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \ 316 \ 317 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \ 318 ** arbitration for full bus walks. \ 319 */ \ 320 /* Save contents of arb mask register. */ \ 321 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \ 322 \ 323 /* \ 324 * Turn off all device arbitration bits (i.e. everything \ 325 * except arbitration enable bit). \ 326 */ \ 327 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \ 328 \ 329 /* \ 330 * Set the smart mode bit so that master aborts don't cause \ 331 * LBA to go into PCI fatal mode (required). \ 332 */ \ 333 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \ 334 } 335 336 337 #define LBA_CFG_PROBE(d, tok) { \ 338 /* \ 339 * Setup Vendor ID write and read back the address register \ 340 * to make sure that LBA is the bus master. \ 341 */ \ 342 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\ 343 /* \ 344 * Read address register to ensure that LBA is the bus master, \ 345 * which implies that DMA traffic has stopped when DMA arb is off. \ 346 */ \ 347 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 348 /* \ 349 * Generate a cfg write cycle (will have no affect on \ 350 * Vendor ID register since read-only). \ 351 */ \ 352 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \ 353 /* \ 354 * Make sure write has completed before proceeding further, \ 355 * i.e. before setting clear enable. \ 356 */ \ 357 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 358 } 359 360 361 /* 362 * HPREVISIT: 363 * -- Can't tell if config cycle got the error. 364 * 365 * OV bit is broken until rev 4.0, so can't use OV bit and 366 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle. 367 * 368 * As of rev 4.0, no longer need the error check. 369 * 370 * -- Even if we could tell, we still want to return -1 371 * for **ANY** error (not just master abort). 372 * 373 * -- Only clear non-fatal errors (we don't want to bring 374 * LBA out of pci-fatal mode). 375 * 376 * Actually, there is still a race in which 377 * we could be clearing a fatal error. We will 378 * live with this during our initial bus walk 379 * until rev 4.0 (no driver activity during 380 * initial bus walk). The initial bus walk 381 * has race conditions concerning the use of 382 * smart mode as well. 383 */ 384 385 #define LBA_MASTER_ABORT_ERROR 0xc 386 #define LBA_FATAL_ERROR 0x10 387 388 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ 389 u32 error_status = 0; \ 390 /* \ 391 * Set clear enable (CE) bit. Unset by HW when new \ 392 * errors are logged -- LBA HW ERS section 14.3.3). \ 393 */ \ 394 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \ 395 error_status = READ_REG32(base + LBA_ERROR_STATUS); \ 396 if ((error_status & 0x1f) != 0) { \ 397 /* \ 398 * Fail the config read request. \ 399 */ \ 400 error = 1; \ 401 if ((error_status & LBA_FATAL_ERROR) == 0) { \ 402 /* \ 403 * Clear error status (if fatal bit not set) by setting \ 404 * clear error log bit (CL). \ 405 */ \ 406 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \ 407 } \ 408 } \ 409 } 410 411 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \ 412 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); 413 414 #define LBA_CFG_ADDR_SETUP(d, addr) { \ 415 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 416 /* \ 417 * Read address register to ensure that LBA is the bus master, \ 418 * which implies that DMA traffic has stopped when DMA arb is off. \ 419 */ \ 420 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 421 } 422 423 424 #define LBA_CFG_RESTORE(d, base) { \ 425 /* \ 426 * Restore status control register (turn off clear enable). \ 427 */ \ 428 WRITE_REG32(status_control, base + LBA_STAT_CTL); \ 429 /* \ 430 * Restore error config register (turn off smart mode). \ 431 */ \ 432 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \ 433 /* \ 434 * Restore arb mask register (reenables DMA arbitration). \ 435 */ \ 436 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \ 437 } 438 439 440 441 static unsigned int 442 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) 443 { 444 u32 data = ~0U; 445 int error = 0; 446 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */ 447 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */ 448 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */ 449 450 LBA_CFG_SETUP(d, tok); 451 LBA_CFG_PROBE(d, tok); 452 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 453 if (!error) { 454 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 455 456 LBA_CFG_ADDR_SETUP(d, tok | reg); 457 switch (size) { 458 case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; 459 case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; 460 case 4: data = READ_REG32(data_reg); break; 461 } 462 } 463 LBA_CFG_RESTORE(d, d->hba.base_addr); 464 return(data); 465 } 466 467 468 static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 469 { 470 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 471 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 472 u32 tok = LBA_CFG_TOK(local_bus, devfn); 473 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 474 475 if ((pos > 255) || (devfn > 255)) 476 return -EINVAL; 477 478 /* FIXME: B2K/C3600 workaround is always use old method... */ 479 /* if (!LBA_SKIP_PROBE(d)) */ { 480 /* original - Generate config cycle on broken elroy 481 with risk we will miss PCI bus errors. */ 482 *data = lba_rd_cfg(d, tok, pos, size); 483 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data); 484 return 0; 485 } 486 487 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) { 488 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos); 489 /* either don't want to look or know device isn't present. */ 490 *data = ~0U; 491 return(0); 492 } 493 494 /* Basic Algorithm 495 ** Should only get here on fully working LBA rev. 496 ** This is how simple the code should have been. 497 */ 498 LBA_CFG_ADDR_SETUP(d, tok | pos); 499 switch(size) { 500 case 1: *data = READ_REG8 (data_reg + (pos & 3)); break; 501 case 2: *data = READ_REG16(data_reg + (pos & 2)); break; 502 case 4: *data = READ_REG32(data_reg); break; 503 } 504 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data); 505 return 0; 506 } 507 508 509 static void 510 lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) 511 { 512 int error = 0; 513 u32 arb_mask = 0; 514 u32 error_config = 0; 515 u32 status_control = 0; 516 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 517 518 LBA_CFG_SETUP(d, tok); 519 LBA_CFG_ADDR_SETUP(d, tok | reg); 520 switch (size) { 521 case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; 522 case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; 523 case 4: WRITE_REG32(data, data_reg); break; 524 } 525 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 526 LBA_CFG_RESTORE(d, d->hba.base_addr); 527 } 528 529 530 /* 531 * LBA 4.0 config write code implements non-postable semantics 532 * by doing a read of CONFIG ADDR after the write. 533 */ 534 535 static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 536 { 537 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 538 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 539 u32 tok = LBA_CFG_TOK(local_bus,devfn); 540 541 if ((pos > 255) || (devfn > 255)) 542 return -EINVAL; 543 544 if (!LBA_SKIP_PROBE(d)) { 545 /* Original Workaround */ 546 lba_wr_cfg(d, tok, pos, (u32) data, size); 547 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data); 548 return 0; 549 } 550 551 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { 552 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data); 553 return 1; /* New Workaround */ 554 } 555 556 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data); 557 558 /* Basic Algorithm */ 559 LBA_CFG_ADDR_SETUP(d, tok | pos); 560 switch(size) { 561 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); 562 break; 563 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); 564 break; 565 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); 566 break; 567 } 568 /* flush posted write */ 569 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 570 return 0; 571 } 572 573 574 static struct pci_ops elroy_cfg_ops = { 575 .read = elroy_cfg_read, 576 .write = elroy_cfg_write, 577 }; 578 579 /* 580 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy 581 * TR4.0 as no additional bugs were found in this areea between Elroy and 582 * Mercury 583 */ 584 585 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 586 { 587 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 588 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 589 u32 tok = LBA_CFG_TOK(local_bus, devfn); 590 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 591 592 if ((pos > 255) || (devfn > 255)) 593 return -EINVAL; 594 595 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 596 switch(size) { 597 case 1: 598 *data = READ_REG8(data_reg + (pos & 3)); 599 break; 600 case 2: 601 *data = READ_REG16(data_reg + (pos & 2)); 602 break; 603 case 4: 604 *data = READ_REG32(data_reg); break; 605 break; 606 } 607 608 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data); 609 return 0; 610 } 611 612 /* 613 * LBA 4.0 config write code implements non-postable semantics 614 * by doing a read of CONFIG ADDR after the write. 615 */ 616 617 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 618 { 619 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 620 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 621 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 622 u32 tok = LBA_CFG_TOK(local_bus,devfn); 623 624 if ((pos > 255) || (devfn > 255)) 625 return -EINVAL; 626 627 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data); 628 629 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 630 switch(size) { 631 case 1: 632 WRITE_REG8 (data, data_reg + (pos & 3)); 633 break; 634 case 2: 635 WRITE_REG16(data, data_reg + (pos & 2)); 636 break; 637 case 4: 638 WRITE_REG32(data, data_reg); 639 break; 640 } 641 642 /* flush posted write */ 643 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 644 return 0; 645 } 646 647 static struct pci_ops mercury_cfg_ops = { 648 .read = mercury_cfg_read, 649 .write = mercury_cfg_write, 650 }; 651 652 653 static void 654 lba_bios_init(void) 655 { 656 DBG(MODULE_NAME ": lba_bios_init\n"); 657 } 658 659 660 #ifdef CONFIG_64BIT 661 662 /* 663 ** Determine if a device is already configured. 664 ** If so, reserve it resources. 665 ** 666 ** Read PCI cfg command register and see if I/O or MMIO is enabled. 667 ** PAT has to enable the devices it's using. 668 ** 669 ** Note: resources are fixed up before we try to claim them. 670 */ 671 static void 672 lba_claim_dev_resources(struct pci_dev *dev) 673 { 674 u16 cmd; 675 int i, srch_flags; 676 677 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd); 678 679 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0; 680 if (cmd & PCI_COMMAND_MEMORY) 681 srch_flags |= IORESOURCE_MEM; 682 683 if (!srch_flags) 684 return; 685 686 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 687 if (dev->resource[i].flags & srch_flags) { 688 pci_claim_resource(dev, i); 689 DBG(" claimed %s %d [%lx,%lx]/%lx\n", 690 pci_name(dev), i, 691 dev->resource[i].start, 692 dev->resource[i].end, 693 dev->resource[i].flags 694 ); 695 } 696 } 697 } 698 #else 699 #define lba_claim_dev_resources(dev) 700 #endif 701 702 703 /* 704 ** The algorithm is generic code. 705 ** But it needs to access local data structures to get the IRQ base. 706 ** Could make this a "pci_fixup_irq(bus, region)" but not sure 707 ** it's worth it. 708 ** 709 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked. 710 ** Resources aren't allocated until recursive buswalk below HBA is completed. 711 */ 712 static void 713 lba_fixup_bus(struct pci_bus *bus) 714 { 715 struct list_head *ln; 716 #ifdef FBB_SUPPORT 717 u16 status; 718 #endif 719 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); 720 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num); 721 722 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n", 723 bus, bus->secondary, bus->bridge->platform_data); 724 725 /* 726 ** Properly Setup MMIO resources for this bus. 727 ** pci_alloc_primary_bus() mangles this. 728 */ 729 if (bus->self) { 730 /* PCI-PCI Bridge */ 731 pci_read_bridge_bases(bus); 732 } else { 733 /* Host-PCI Bridge */ 734 int err, i; 735 736 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 737 ldev->hba.io_space.name, 738 ldev->hba.io_space.start, ldev->hba.io_space.end, 739 ldev->hba.io_space.flags); 740 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 741 ldev->hba.lmmio_space.name, 742 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, 743 ldev->hba.lmmio_space.flags); 744 745 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); 746 if (err < 0) { 747 lba_dump_res(&ioport_resource, 2); 748 BUG(); 749 } 750 751 if (ldev->hba.elmmio_space.start) { 752 err = request_resource(&iomem_resource, 753 &(ldev->hba.elmmio_space)); 754 if (err < 0) { 755 756 printk("FAILED: lba_fixup_bus() request for " 757 "elmmio_space [%lx/%lx]\n", 758 ldev->hba.elmmio_space.start, 759 ldev->hba.elmmio_space.end); 760 761 /* lba_dump_res(&iomem_resource, 2); */ 762 /* BUG(); */ 763 } 764 } 765 766 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); 767 if (err < 0) { 768 /* FIXME overlaps with elmmio will fail here. 769 * Need to prune (or disable) the distributed range. 770 * 771 * BEWARE: conflicts with this lmmio range may be 772 * elmmio range which is pointing down another rope. 773 */ 774 775 printk("FAILED: lba_fixup_bus() request for " 776 "lmmio_space [%lx/%lx]\n", 777 ldev->hba.lmmio_space.start, 778 ldev->hba.lmmio_space.end); 779 /* lba_dump_res(&iomem_resource, 2); */ 780 } 781 782 #ifdef CONFIG_64BIT 783 /* GMMIO is distributed range. Every LBA/Rope gets part it. */ 784 if (ldev->hba.gmmio_space.flags) { 785 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); 786 if (err < 0) { 787 printk("FAILED: lba_fixup_bus() request for " 788 "gmmio_space [%lx/%lx]\n", 789 ldev->hba.gmmio_space.start, 790 ldev->hba.gmmio_space.end); 791 lba_dump_res(&iomem_resource, 2); 792 BUG(); 793 } 794 } 795 #endif 796 797 /* advertize Host bridge resources to PCI bus */ 798 bus->resource[0] = &(ldev->hba.io_space); 799 bus->resource[1] = &(ldev->hba.lmmio_space); 800 i=2; 801 if (ldev->hba.elmmio_space.start) 802 bus->resource[i++] = &(ldev->hba.elmmio_space); 803 if (ldev->hba.gmmio_space.start) 804 bus->resource[i++] = &(ldev->hba.gmmio_space); 805 806 } 807 808 list_for_each(ln, &bus->devices) { 809 int i; 810 struct pci_dev *dev = pci_dev_b(ln); 811 812 DBG("lba_fixup_bus() %s\n", pci_name(dev)); 813 814 /* Virtualize Device/Bridge Resources. */ 815 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 816 struct resource *res = &dev->resource[i]; 817 818 /* If resource not allocated - skip it */ 819 if (!res->start) 820 continue; 821 822 if (res->flags & IORESOURCE_IO) { 823 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ", 824 res->start, res->end); 825 res->start |= lba_portbase; 826 res->end |= lba_portbase; 827 DBG("[%lx/%lx]\n", res->start, res->end); 828 } else if (res->flags & IORESOURCE_MEM) { 829 /* 830 ** Convert PCI (IO_VIEW) addresses to 831 ** processor (PA_VIEW) addresses 832 */ 833 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ", 834 res->start, res->end); 835 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start); 836 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end); 837 DBG("[%lx/%lx]\n", res->start, res->end); 838 } else { 839 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX", 840 res->flags, res->start, res->end); 841 } 842 } 843 844 #ifdef FBB_SUPPORT 845 /* 846 ** If one device does not support FBB transfers, 847 ** No one on the bus can be allowed to use them. 848 */ 849 (void) pci_read_config_word(dev, PCI_STATUS, &status); 850 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK); 851 #endif 852 853 if (is_pdc_pat()) { 854 /* Claim resources for PDC's devices */ 855 lba_claim_dev_resources(dev); 856 } 857 858 /* 859 ** P2PB's have no IRQs. ignore them. 860 */ 861 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 862 continue; 863 864 /* Adjust INTERRUPT_LINE for this dev */ 865 iosapic_fixup_irq(ldev->iosapic_obj, dev); 866 } 867 868 #ifdef FBB_SUPPORT 869 /* FIXME/REVISIT - finish figuring out to set FBB on both 870 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL. 871 ** Can't fixup here anyway....garr... 872 */ 873 if (fbb_enable) { 874 if (bus->self) { 875 u8 control; 876 /* enable on PPB */ 877 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); 878 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK); 879 880 } else { 881 /* enable on LBA */ 882 } 883 fbb_enable = PCI_COMMAND_FAST_BACK; 884 } 885 886 /* Lastly enable FBB/PERR/SERR on all devices too */ 887 list_for_each(ln, &bus->devices) { 888 (void) pci_read_config_word(dev, PCI_COMMAND, &status); 889 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable; 890 (void) pci_write_config_word(dev, PCI_COMMAND, status); 891 } 892 #endif 893 } 894 895 896 struct pci_bios_ops lba_bios_ops = { 897 .init = lba_bios_init, 898 .fixup_bus = lba_fixup_bus, 899 }; 900 901 902 903 904 /******************************************************* 905 ** 906 ** LBA Sprockets "I/O Port" Space Accessor Functions 907 ** 908 ** This set of accessor functions is intended for use with 909 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes). 910 ** 911 ** Many PCI devices don't require use of I/O port space (eg Tulip, 912 ** NCR720) since they export the same registers to both MMIO and 913 ** I/O port space. In general I/O port space is slower than 914 ** MMIO since drivers are designed so PIO writes can be posted. 915 ** 916 ********************************************************/ 917 918 #define LBA_PORT_IN(size, mask) \ 919 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \ 920 { \ 921 u##size t; \ 922 t = READ_REG##size(astro_iop_base + addr); \ 923 DBG_PORT(" 0x%x\n", t); \ 924 return (t); \ 925 } 926 927 LBA_PORT_IN( 8, 3) 928 LBA_PORT_IN(16, 2) 929 LBA_PORT_IN(32, 0) 930 931 932 933 /* 934 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR 935 ** 936 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is 937 ** guarantee non-postable completion semantics - not avoid X4107. 938 ** The READ_U32 only guarantees the write data gets to elroy but 939 ** out to the PCI bus. We can't read stuff from I/O port space 940 ** since we don't know what has side-effects. Attempting to read 941 ** from configuration space would be suicidal given the number of 942 ** bugs in that elroy functionality. 943 ** 944 ** Description: 945 ** DMA read results can improperly pass PIO writes (X4107). The 946 ** result of this bug is that if a processor modifies a location in 947 ** memory after having issued PIO writes, the PIO writes are not 948 ** guaranteed to be completed before a PCI device is allowed to see 949 ** the modified data in a DMA read. 950 ** 951 ** Note that IKE bug X3719 in TR1 IKEs will result in the same 952 ** symptom. 953 ** 954 ** Workaround: 955 ** The workaround for this bug is to always follow a PIO write with 956 ** a PIO read to the same bus before starting DMA on that PCI bus. 957 ** 958 */ 959 #define LBA_PORT_OUT(size, mask) \ 960 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 961 { \ 962 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \ 963 WRITE_REG##size(val, astro_iop_base + addr); \ 964 if (LBA_DEV(d)->hw_rev < 3) \ 965 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \ 966 } 967 968 LBA_PORT_OUT( 8, 3) 969 LBA_PORT_OUT(16, 2) 970 LBA_PORT_OUT(32, 0) 971 972 973 static struct pci_port_ops lba_astro_port_ops = { 974 .inb = lba_astro_in8, 975 .inw = lba_astro_in16, 976 .inl = lba_astro_in32, 977 .outb = lba_astro_out8, 978 .outw = lba_astro_out16, 979 .outl = lba_astro_out32 980 }; 981 982 983 #ifdef CONFIG_64BIT 984 #define PIOP_TO_GMMIO(lba, addr) \ 985 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3)) 986 987 /******************************************************* 988 ** 989 ** LBA PAT "I/O Port" Space Accessor Functions 990 ** 991 ** This set of accessor functions is intended for use with 992 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes). 993 ** 994 ** This uses the PIOP space located in the first 64MB of GMMIO. 995 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way. 996 ** bits 1:0 stay the same. bits 15:2 become 25:12. 997 ** Then add the base and we can generate an I/O Port cycle. 998 ********************************************************/ 999 #undef LBA_PORT_IN 1000 #define LBA_PORT_IN(size, mask) \ 1001 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \ 1002 { \ 1003 u##size t; \ 1004 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \ 1005 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \ 1006 DBG_PORT(" 0x%x\n", t); \ 1007 return (t); \ 1008 } 1009 1010 LBA_PORT_IN( 8, 3) 1011 LBA_PORT_IN(16, 2) 1012 LBA_PORT_IN(32, 0) 1013 1014 1015 #undef LBA_PORT_OUT 1016 #define LBA_PORT_OUT(size, mask) \ 1017 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \ 1018 { \ 1019 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \ 1020 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \ 1021 WRITE_REG##size(val, where); \ 1022 /* flush the I/O down to the elroy at least */ \ 1023 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \ 1024 } 1025 1026 LBA_PORT_OUT( 8, 3) 1027 LBA_PORT_OUT(16, 2) 1028 LBA_PORT_OUT(32, 0) 1029 1030 1031 static struct pci_port_ops lba_pat_port_ops = { 1032 .inb = lba_pat_in8, 1033 .inw = lba_pat_in16, 1034 .inl = lba_pat_in32, 1035 .outb = lba_pat_out8, 1036 .outw = lba_pat_out16, 1037 .outl = lba_pat_out32 1038 }; 1039 1040 1041 1042 /* 1043 ** make range information from PDC available to PCI subsystem. 1044 ** We make the PDC call here in order to get the PCI bus range 1045 ** numbers. The rest will get forwarded in pcibios_fixup_bus(). 1046 ** We don't have a struct pci_bus assigned to us yet. 1047 */ 1048 static void 1049 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1050 { 1051 unsigned long bytecnt; 1052 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */ 1053 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */ 1054 long io_count; 1055 long status; /* PDC return status */ 1056 long pa_count; 1057 int i; 1058 1059 /* return cell module (IO view) */ 1060 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 1061 PA_VIEW, & pa_pdc_cell); 1062 pa_count = pa_pdc_cell.mod[1]; 1063 1064 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 1065 IO_VIEW, &io_pdc_cell); 1066 io_count = io_pdc_cell.mod[1]; 1067 1068 /* We've already done this once for device discovery...*/ 1069 if (status != PDC_OK) { 1070 panic("pdc_pat_cell_module() call failed for LBA!\n"); 1071 } 1072 1073 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) { 1074 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n"); 1075 } 1076 1077 /* 1078 ** Inspect the resources PAT tells us about 1079 */ 1080 for (i = 0; i < pa_count; i++) { 1081 struct { 1082 unsigned long type; 1083 unsigned long start; 1084 unsigned long end; /* aka finish */ 1085 } *p, *io; 1086 struct resource *r; 1087 1088 p = (void *) &(pa_pdc_cell.mod[2+i*3]); 1089 io = (void *) &(io_pdc_cell.mod[2+i*3]); 1090 1091 /* Convert the PAT range data to PCI "struct resource" */ 1092 switch(p->type & 0xff) { 1093 case PAT_PBNUM: 1094 lba_dev->hba.bus_num.start = p->start; 1095 lba_dev->hba.bus_num.end = p->end; 1096 break; 1097 1098 case PAT_LMMIO: 1099 /* used to fix up pre-initialized MEM BARs */ 1100 if (!lba_dev->hba.lmmio_space.start) { 1101 sprintf(lba_dev->hba.lmmio_name, 1102 "PCI%02lx LMMIO", 1103 lba_dev->hba.bus_num.start); 1104 lba_dev->hba.lmmio_space_offset = p->start - 1105 io->start; 1106 r = &lba_dev->hba.lmmio_space; 1107 r->name = lba_dev->hba.lmmio_name; 1108 } else if (!lba_dev->hba.elmmio_space.start) { 1109 sprintf(lba_dev->hba.elmmio_name, 1110 "PCI%02lx ELMMIO", 1111 lba_dev->hba.bus_num.start); 1112 r = &lba_dev->hba.elmmio_space; 1113 r->name = lba_dev->hba.elmmio_name; 1114 } else { 1115 printk(KERN_WARNING MODULE_NAME 1116 " only supports 2 LMMIO resources!\n"); 1117 break; 1118 } 1119 1120 r->start = p->start; 1121 r->end = p->end; 1122 r->flags = IORESOURCE_MEM; 1123 r->parent = r->sibling = r->child = NULL; 1124 break; 1125 1126 case PAT_GMMIO: 1127 /* MMIO space > 4GB phys addr; for 64-bit BAR */ 1128 sprintf(lba_dev->hba.gmmio_name, "PCI%02lx GMMIO", 1129 lba_dev->hba.bus_num.start); 1130 r = &lba_dev->hba.gmmio_space; 1131 r->name = lba_dev->hba.gmmio_name; 1132 r->start = p->start; 1133 r->end = p->end; 1134 r->flags = IORESOURCE_MEM; 1135 r->parent = r->sibling = r->child = NULL; 1136 break; 1137 1138 case PAT_NPIOP: 1139 printk(KERN_WARNING MODULE_NAME 1140 " range[%d] : ignoring NPIOP (0x%lx)\n", 1141 i, p->start); 1142 break; 1143 1144 case PAT_PIOP: 1145 /* 1146 ** Postable I/O port space is per PCI host adapter. 1147 ** base of 64MB PIOP region 1148 */ 1149 lba_dev->iop_base = ioremap(p->start, 64 * 1024 * 1024); 1150 1151 sprintf(lba_dev->hba.io_name, "PCI%02lx Ports", 1152 lba_dev->hba.bus_num.start); 1153 r = &lba_dev->hba.io_space; 1154 r->name = lba_dev->hba.io_name; 1155 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); 1156 r->end = r->start + HBA_PORT_SPACE_SIZE - 1; 1157 r->flags = IORESOURCE_IO; 1158 r->parent = r->sibling = r->child = NULL; 1159 break; 1160 1161 default: 1162 printk(KERN_WARNING MODULE_NAME 1163 " range[%d] : unknown pat range type (0x%lx)\n", 1164 i, p->type & 0xff); 1165 break; 1166 } 1167 } 1168 } 1169 #else 1170 /* keep compiler from complaining about missing declarations */ 1171 #define lba_pat_port_ops lba_astro_port_ops 1172 #define lba_pat_resources(pa_dev, lba_dev) 1173 #endif /* CONFIG_64BIT */ 1174 1175 1176 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *); 1177 extern void sba_directed_lmmio(struct parisc_device *, struct resource *); 1178 1179 1180 static void 1181 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1182 { 1183 struct resource *r; 1184 int lba_num; 1185 1186 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; 1187 1188 /* 1189 ** With "legacy" firmware, the lowest byte of FW_SCRATCH 1190 ** represents bus->secondary and the second byte represents 1191 ** bus->subsidiary (i.e. highest PPB programmed by firmware). 1192 ** PCI bus walk *should* end up with the same result. 1193 ** FIXME: But we don't have sanity checks in PCI or LBA. 1194 */ 1195 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); 1196 r = &(lba_dev->hba.bus_num); 1197 r->name = "LBA PCI Busses"; 1198 r->start = lba_num & 0xff; 1199 r->end = (lba_num>>8) & 0xff; 1200 1201 /* Set up local PCI Bus resources - we don't need them for 1202 ** Legacy boxes but it's nice to see in /proc/iomem. 1203 */ 1204 r = &(lba_dev->hba.lmmio_space); 1205 sprintf(lba_dev->hba.lmmio_name, "PCI%02lx LMMIO", 1206 lba_dev->hba.bus_num.start); 1207 r->name = lba_dev->hba.lmmio_name; 1208 1209 #if 1 1210 /* We want the CPU -> IO routing of addresses. 1211 * The SBA BASE/MASK registers control CPU -> IO routing. 1212 * Ask SBA what is routed to this rope/LBA. 1213 */ 1214 sba_distributed_lmmio(pa_dev, r); 1215 #else 1216 /* 1217 * The LBA BASE/MASK registers control IO -> System routing. 1218 * 1219 * The following code works but doesn't get us what we want. 1220 * Well, only because firmware (v5.0) on C3000 doesn't program 1221 * the LBA BASE/MASE registers to be the exact inverse of 1222 * the corresponding SBA registers. Other Astro/Pluto 1223 * based platform firmware may do it right. 1224 * 1225 * Should someone want to mess with MSI, they may need to 1226 * reprogram LBA BASE/MASK registers. Thus preserve the code 1227 * below until MSI is known to work on C3000/A500/N4000/RP3440. 1228 * 1229 * Using the code below, /proc/iomem shows: 1230 * ... 1231 * f0000000-f0ffffff : PCI00 LMMIO 1232 * f05d0000-f05d0000 : lcd_data 1233 * f05d0008-f05d0008 : lcd_cmd 1234 * f1000000-f1ffffff : PCI01 LMMIO 1235 * f4000000-f4ffffff : PCI02 LMMIO 1236 * f4000000-f4001fff : sym53c8xx 1237 * f4002000-f4003fff : sym53c8xx 1238 * f4004000-f40043ff : sym53c8xx 1239 * f4005000-f40053ff : sym53c8xx 1240 * f4007000-f4007fff : ohci_hcd 1241 * f4008000-f40083ff : tulip 1242 * f6000000-f6ffffff : PCI03 LMMIO 1243 * f8000000-fbffffff : PCI00 ELMMIO 1244 * fa100000-fa4fffff : stifb mmio 1245 * fb000000-fb1fffff : stifb fb 1246 * 1247 * But everything listed under PCI02 actually lives under PCI00. 1248 * This is clearly wrong. 1249 * 1250 * Asking SBA how things are routed tells the correct story: 1251 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000 1252 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006 1253 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004 1254 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000 1255 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000 1256 * 1257 * Which looks like this in /proc/iomem: 1258 * f4000000-f47fffff : PCI00 LMMIO 1259 * f4000000-f4001fff : sym53c8xx 1260 * ...[deteled core devices - same as above]... 1261 * f4008000-f40083ff : tulip 1262 * f4800000-f4ffffff : PCI01 LMMIO 1263 * f6000000-f67fffff : PCI02 LMMIO 1264 * f7000000-f77fffff : PCI03 LMMIO 1265 * f9000000-f9ffffff : PCI02 ELMMIO 1266 * fa000000-fbffffff : PCI03 ELMMIO 1267 * fa100000-fa4fffff : stifb mmio 1268 * fb000000-fb1fffff : stifb fb 1269 * 1270 * ie all Built-in core are under now correctly under PCI00. 1271 * The "PCI02 ELMMIO" directed range is for: 1272 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2 1273 * 1274 * All is well now. 1275 */ 1276 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); 1277 if (r->start & 1) { 1278 unsigned long rsize; 1279 1280 r->flags = IORESOURCE_MEM; 1281 /* mmio_mask also clears Enable bit */ 1282 r->start &= mmio_mask; 1283 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); 1284 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); 1285 1286 /* 1287 ** Each rope only gets part of the distributed range. 1288 ** Adjust "window" for this rope. 1289 */ 1290 rsize /= ROPES_PER_IOC; 1291 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start); 1292 r->end = r->start + rsize; 1293 } else { 1294 r->end = r->start = 0; /* Not enabled. */ 1295 } 1296 #endif 1297 1298 /* 1299 ** "Directed" ranges are used when the "distributed range" isn't 1300 ** sufficient for all devices below a given LBA. Typically devices 1301 ** like graphics cards or X25 may need a directed range when the 1302 ** bus has multiple slots (ie multiple devices) or the device 1303 ** needs more than the typical 4 or 8MB a distributed range offers. 1304 ** 1305 ** The main reason for ignoring it now frigging complications. 1306 ** Directed ranges may overlap (and have precedence) over 1307 ** distributed ranges. Or a distributed range assigned to a unused 1308 ** rope may be used by a directed range on a different rope. 1309 ** Support for graphics devices may require fixing this 1310 ** since they may be assigned a directed range which overlaps 1311 ** an existing (but unused portion of) distributed range. 1312 */ 1313 r = &(lba_dev->hba.elmmio_space); 1314 sprintf(lba_dev->hba.elmmio_name, "PCI%02lx ELMMIO", 1315 lba_dev->hba.bus_num.start); 1316 r->name = lba_dev->hba.elmmio_name; 1317 1318 #if 1 1319 /* See comment which precedes call to sba_directed_lmmio() */ 1320 sba_directed_lmmio(pa_dev, r); 1321 #else 1322 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); 1323 1324 if (r->start & 1) { 1325 unsigned long rsize; 1326 r->flags = IORESOURCE_MEM; 1327 /* mmio_mask also clears Enable bit */ 1328 r->start &= mmio_mask; 1329 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); 1330 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); 1331 r->end = r->start + ~rsize; 1332 } 1333 #endif 1334 1335 r = &(lba_dev->hba.io_space); 1336 sprintf(lba_dev->hba.io_name, "PCI%02lx Ports", 1337 lba_dev->hba.bus_num.start); 1338 r->name = lba_dev->hba.io_name; 1339 r->flags = IORESOURCE_IO; 1340 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; 1341 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); 1342 1343 /* Virtualize the I/O Port space ranges */ 1344 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); 1345 r->start |= lba_num; 1346 r->end |= lba_num; 1347 } 1348 1349 1350 /************************************************************************** 1351 ** 1352 ** LBA initialization code (HW and SW) 1353 ** 1354 ** o identify LBA chip itself 1355 ** o initialize LBA chip modes (HardFail) 1356 ** o FIXME: initialize DMA hints for reasonable defaults 1357 ** o enable configuration functions 1358 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked) 1359 ** 1360 **************************************************************************/ 1361 1362 static int __init 1363 lba_hw_init(struct lba_device *d) 1364 { 1365 u32 stat; 1366 u32 bus_reset; /* PDC_PAT_BUG */ 1367 1368 #if 0 1369 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n", 1370 d->hba.base_addr, 1371 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), 1372 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), 1373 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), 1374 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); 1375 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n", 1376 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), 1377 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), 1378 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), 1379 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); 1380 printk(KERN_DEBUG " HINT cfg 0x%Lx\n", 1381 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); 1382 printk(KERN_DEBUG " HINT reg "); 1383 { int i; 1384 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8) 1385 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); 1386 } 1387 printk("\n"); 1388 #endif /* DEBUG_LBA_PAT */ 1389 1390 #ifdef CONFIG_64BIT 1391 /* 1392 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support 1393 * Only N-Class and up can really make use of Get slot status. 1394 * maybe L-class too but I've never played with it there. 1395 */ 1396 #endif 1397 1398 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */ 1399 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; 1400 if (bus_reset) { 1401 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n"); 1402 } 1403 1404 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); 1405 if (stat & LBA_SMART_MODE) { 1406 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n"); 1407 stat &= ~LBA_SMART_MODE; 1408 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); 1409 } 1410 1411 /* Set HF mode as the default (vs. -1 mode). */ 1412 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); 1413 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); 1414 1415 /* 1416 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal 1417 ** if it's not already set. If we just cleared the PCI Bus Reset 1418 ** signal, wait a bit for the PCI devices to recover and setup. 1419 */ 1420 if (bus_reset) 1421 mdelay(pci_post_reset_delay); 1422 1423 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { 1424 /* 1425 ** PDC_PAT_BUG: PDC rev 40.48 on L2000. 1426 ** B2000/C3600/J6000 also have this problem? 1427 ** 1428 ** Elroys with hot pluggable slots don't get configured 1429 ** correctly if the slot is empty. ARB_MASK is set to 0 1430 ** and we can't master transactions on the bus if it's 1431 ** not at least one. 0x3 enables elroy and first slot. 1432 */ 1433 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n"); 1434 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); 1435 } 1436 1437 /* 1438 ** FIXME: Hint registers are programmed with default hint 1439 ** values by firmware. Hints should be sane even if we 1440 ** can't reprogram them the way drivers want. 1441 */ 1442 return 0; 1443 } 1444 1445 1446 1447 /* 1448 ** Determine if lba should claim this chip (return 0) or not (return 1). 1449 ** If so, initialize the chip and tell other partners in crime they 1450 ** have work to do. 1451 */ 1452 static int __init 1453 lba_driver_probe(struct parisc_device *dev) 1454 { 1455 struct lba_device *lba_dev; 1456 struct pci_bus *lba_bus; 1457 struct pci_ops *cfg_ops; 1458 u32 func_class; 1459 void *tmp_obj; 1460 char *version; 1461 void __iomem *addr = ioremap(dev->hpa.start, 4096); 1462 1463 /* Read HW Rev First */ 1464 func_class = READ_REG32(addr + LBA_FCLASS); 1465 1466 if (IS_ELROY(dev)) { 1467 func_class &= 0xf; 1468 switch (func_class) { 1469 case 0: version = "TR1.0"; break; 1470 case 1: version = "TR2.0"; break; 1471 case 2: version = "TR2.1"; break; 1472 case 3: version = "TR2.2"; break; 1473 case 4: version = "TR3.0"; break; 1474 case 5: version = "TR4.0"; break; 1475 default: version = "TR4+"; 1476 } 1477 1478 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n", 1479 MODULE_NAME, version, func_class & 0xf, dev->hpa.start); 1480 1481 if (func_class < 2) { 1482 printk(KERN_WARNING "Can't support LBA older than " 1483 "TR2.1 - continuing under adversity.\n"); 1484 } 1485 1486 #if 0 1487 /* Elroy TR4.0 should work with simple algorithm. 1488 But it doesn't. Still missing something. *sigh* 1489 */ 1490 if (func_class > 4) { 1491 cfg_ops = &mercury_cfg_ops; 1492 } else 1493 #endif 1494 { 1495 cfg_ops = &elroy_cfg_ops; 1496 } 1497 1498 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) { 1499 func_class &= 0xff; 1500 version = kmalloc(6, GFP_KERNEL); 1501 sprintf(version,"TR%d.%d",(func_class >> 4),(func_class & 0xf)); 1502 /* We could use one printk for both Elroy and Mercury, 1503 * but for the mask for func_class. 1504 */ 1505 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n", 1506 MODULE_NAME, version, func_class & 0xff, dev->hpa.start); 1507 cfg_ops = &mercury_cfg_ops; 1508 } else { 1509 printk(KERN_ERR "Unknown LBA found at 0x%lx\n", dev->hpa.start); 1510 return -ENODEV; 1511 } 1512 1513 /* 1514 ** Tell I/O SAPIC driver we have a IRQ handler/region. 1515 */ 1516 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE); 1517 1518 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't 1519 ** have an IRT entry will get NULL back from iosapic code. 1520 */ 1521 1522 lba_dev = kmalloc(sizeof(struct lba_device), GFP_KERNEL); 1523 if (!lba_dev) { 1524 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n"); 1525 return(1); 1526 } 1527 1528 memset(lba_dev, 0, sizeof(struct lba_device)); 1529 1530 1531 /* ---------- First : initialize data we already have --------- */ 1532 1533 lba_dev->hw_rev = func_class; 1534 lba_dev->hba.base_addr = addr; 1535 lba_dev->hba.dev = dev; 1536 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ 1537 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ 1538 1539 /* ------------ Second : initialize common stuff ---------- */ 1540 pci_bios = &lba_bios_ops; 1541 pcibios_register_hba(HBA_DATA(lba_dev)); 1542 spin_lock_init(&lba_dev->lba_lock); 1543 1544 if (lba_hw_init(lba_dev)) 1545 return(1); 1546 1547 /* ---------- Third : setup I/O Port and MMIO resources --------- */ 1548 1549 if (is_pdc_pat()) { 1550 /* PDC PAT firmware uses PIOP region of GMMIO space. */ 1551 pci_port = &lba_pat_port_ops; 1552 /* Go ask PDC PAT what resources this LBA has */ 1553 lba_pat_resources(dev, lba_dev); 1554 } else { 1555 if (!astro_iop_base) { 1556 /* Sprockets PDC uses NPIOP region */ 1557 astro_iop_base = ioremap(LBA_PORT_BASE, 64 * 1024); 1558 pci_port = &lba_astro_port_ops; 1559 } 1560 1561 /* Poke the chip a bit for /proc output */ 1562 lba_legacy_resources(dev, lba_dev); 1563 } 1564 1565 /* 1566 ** Tell PCI support another PCI bus was found. 1567 ** Walks PCI bus for us too. 1568 */ 1569 dev->dev.platform_data = lba_dev; 1570 lba_bus = lba_dev->hba.hba_bus = 1571 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start, 1572 cfg_ops, NULL); 1573 if (lba_bus) 1574 pci_bus_add_devices(lba_bus); 1575 1576 /* This is in lieu of calling pci_assign_unassigned_resources() */ 1577 if (is_pdc_pat()) { 1578 /* assign resources to un-initialized devices */ 1579 1580 DBG_PAT("LBA pci_bus_size_bridges()\n"); 1581 pci_bus_size_bridges(lba_bus); 1582 1583 DBG_PAT("LBA pci_bus_assign_resources()\n"); 1584 pci_bus_assign_resources(lba_bus); 1585 1586 #ifdef DEBUG_LBA_PAT 1587 DBG_PAT("\nLBA PIOP resource tree\n"); 1588 lba_dump_res(&lba_dev->hba.io_space, 2); 1589 DBG_PAT("\nLBA LMMIO resource tree\n"); 1590 lba_dump_res(&lba_dev->hba.lmmio_space, 2); 1591 #endif 1592 } 1593 pci_enable_bridges(lba_bus); 1594 1595 1596 /* 1597 ** Once PCI register ops has walked the bus, access to config 1598 ** space is restricted. Avoids master aborts on config cycles. 1599 ** Early LBA revs go fatal on *any* master abort. 1600 */ 1601 if (cfg_ops == &elroy_cfg_ops) { 1602 lba_dev->flags |= LBA_FLAG_SKIP_PROBE; 1603 } 1604 1605 /* Whew! Finally done! Tell services we got this one covered. */ 1606 return 0; 1607 } 1608 1609 static struct parisc_device_id lba_tbl[] = { 1610 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa }, 1611 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa }, 1612 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa }, 1613 { 0, } 1614 }; 1615 1616 static struct parisc_driver lba_driver = { 1617 .name = MODULE_NAME, 1618 .id_table = lba_tbl, 1619 .probe = lba_driver_probe, 1620 }; 1621 1622 /* 1623 ** One time initialization to let the world know the LBA was found. 1624 ** Must be called exactly once before pci_init(). 1625 */ 1626 void __init lba_init(void) 1627 { 1628 register_parisc_driver(&lba_driver); 1629 } 1630 1631 /* 1632 ** Initialize the IBASE/IMASK registers for LBA (Elroy). 1633 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA). 1634 ** sba_iommu is responsible for locking (none needed at init time). 1635 */ 1636 void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) 1637 { 1638 void __iomem * base_addr = ioremap(lba->hpa.start, 4096); 1639 1640 imask <<= 2; /* adjust for hints - 2 more bits */ 1641 1642 /* Make sure we aren't trying to set bits that aren't writeable. */ 1643 WARN_ON((ibase & 0x001fffff) != 0); 1644 WARN_ON((imask & 0x001fffff) != 0); 1645 1646 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask); 1647 WRITE_REG32( imask, base_addr + LBA_IMASK); 1648 WRITE_REG32( ibase, base_addr + LBA_IBASE); 1649 iounmap(base_addr); 1650 } 1651 1652