1 /* 2 ** 3 ** PCI Lower Bus Adapter (LBA) manager 4 ** 5 ** (c) Copyright 1999,2000 Grant Grundler 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** 8 ** This program is free software; you can redistribute it and/or modify 9 ** it under the terms of the GNU General Public License as published by 10 ** the Free Software Foundation; either version 2 of the License, or 11 ** (at your option) any later version. 12 ** 13 ** 14 ** This module primarily provides access to PCI bus (config/IOport 15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class 16 ** with 4 digit model numbers - eg C3000 (and A400...sigh). 17 ** 18 ** LBA driver isn't as simple as the Dino driver because: 19 ** (a) this chip has substantial bug fixes between revisions 20 ** (Only one Dino bug has a software workaround :^( ) 21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD) 22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver) 23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC). 24 ** (dino only deals with "Legacy" PDC) 25 ** 26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver. 27 ** (I/O SAPIC is integratd in the LBA chip). 28 ** 29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets 30 ** FIXME: Add support for PCI card hot-plug (OLARD). 31 */ 32 33 #include <linux/delay.h> 34 #include <linux/types.h> 35 #include <linux/kernel.h> 36 #include <linux/spinlock.h> 37 #include <linux/init.h> /* for __init */ 38 #include <linux/pci.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 42 #include <asm/byteorder.h> 43 #include <asm/pdc.h> 44 #include <asm/pdcpat.h> 45 #include <asm/page.h> 46 47 #include <asm/ropes.h> 48 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 49 #include <asm/parisc-device.h> 50 #include <asm/io.h> /* read/write stuff */ 51 52 #include "iommu.h" 53 54 #undef DEBUG_LBA /* general stuff */ 55 #undef DEBUG_LBA_PORT /* debug I/O Port access */ 56 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */ 57 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */ 58 59 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */ 60 61 62 #ifdef DEBUG_LBA 63 #define DBG(x...) printk(x) 64 #else 65 #define DBG(x...) 66 #endif 67 68 #ifdef DEBUG_LBA_PORT 69 #define DBG_PORT(x...) printk(x) 70 #else 71 #define DBG_PORT(x...) 72 #endif 73 74 #ifdef DEBUG_LBA_CFG 75 #define DBG_CFG(x...) printk(x) 76 #else 77 #define DBG_CFG(x...) 78 #endif 79 80 #ifdef DEBUG_LBA_PAT 81 #define DBG_PAT(x...) printk(x) 82 #else 83 #define DBG_PAT(x...) 84 #endif 85 86 87 /* 88 ** Config accessor functions only pass in the 8-bit bus number and not 89 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus 90 ** number based on what firmware wrote into the scratch register. 91 ** 92 ** The "secondary" bus number is set to this before calling 93 ** pci_register_ops(). If any PPB's are present, the scan will 94 ** discover them and update the "secondary" and "subordinate" 95 ** fields in the pci_bus structure. 96 ** 97 ** Changes in the configuration *may* result in a different 98 ** bus number for each LBA depending on what firmware does. 99 */ 100 101 #define MODULE_NAME "LBA" 102 103 /* non-postable I/O port space, densely packed */ 104 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) 105 static void __iomem *astro_iop_base __read_mostly; 106 107 static u32 lba_t32; 108 109 /* lba flags */ 110 #define LBA_FLAG_SKIP_PROBE 0x10 111 112 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE) 113 114 static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba) 115 { 116 return container_of(hba, struct lba_device, hba); 117 } 118 119 /* 120 ** Only allow 8 subsidiary busses per LBA 121 ** Problem is the PCI bus numbering is globally shared. 122 */ 123 #define LBA_MAX_NUM_BUSES 8 124 125 /************************************ 126 * LBA register read and write support 127 * 128 * BE WARNED: register writes are posted. 129 * (ie follow writes which must reach HW with a read) 130 */ 131 #define READ_U8(addr) __raw_readb(addr) 132 #define READ_U16(addr) __raw_readw(addr) 133 #define READ_U32(addr) __raw_readl(addr) 134 #define WRITE_U8(value, addr) __raw_writeb(value, addr) 135 #define WRITE_U16(value, addr) __raw_writew(value, addr) 136 #define WRITE_U32(value, addr) __raw_writel(value, addr) 137 138 #define READ_REG8(addr) readb(addr) 139 #define READ_REG16(addr) readw(addr) 140 #define READ_REG32(addr) readl(addr) 141 #define READ_REG64(addr) readq(addr) 142 #define WRITE_REG8(value, addr) writeb(value, addr) 143 #define WRITE_REG16(value, addr) writew(value, addr) 144 #define WRITE_REG32(value, addr) writel(value, addr) 145 146 147 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8)) 148 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16)) 149 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f) 150 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7) 151 152 153 /* 154 ** Extract LBA (Rope) number from HPA 155 ** REVISIT: 16 ropes for Stretch/Ike? 156 */ 157 #define ROPES_PER_IOC 8 158 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1)) 159 160 161 static void 162 lba_dump_res(struct resource *r, int d) 163 { 164 int i; 165 166 if (NULL == r) 167 return; 168 169 printk(KERN_DEBUG "(%p)", r->parent); 170 for (i = d; i ; --i) printk(" "); 171 printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r, 172 (long)r->start, (long)r->end, r->flags); 173 lba_dump_res(r->child, d+2); 174 lba_dump_res(r->sibling, d); 175 } 176 177 178 /* 179 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex 180 ** workaround for cfg cycles: 181 ** -- preserve LBA state 182 ** -- prevent any DMA from occurring 183 ** -- turn on smart mode 184 ** -- probe with config writes before doing config reads 185 ** -- check ERROR_STATUS 186 ** -- clear ERROR_STATUS 187 ** -- restore LBA state 188 ** 189 ** The workaround is only used for device discovery. 190 */ 191 192 static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d) 193 { 194 u8 first_bus = d->hba.hba_bus->busn_res.start; 195 u8 last_sub_bus = d->hba.hba_bus->busn_res.end; 196 197 if ((bus < first_bus) || 198 (bus > last_sub_bus) || 199 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) { 200 return 0; 201 } 202 203 return 1; 204 } 205 206 207 208 #define LBA_CFG_SETUP(d, tok) { \ 209 /* Save contents of error config register. */ \ 210 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \ 211 \ 212 /* Save contents of status control register. */ \ 213 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \ 214 \ 215 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \ 216 ** arbitration for full bus walks. \ 217 */ \ 218 /* Save contents of arb mask register. */ \ 219 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \ 220 \ 221 /* \ 222 * Turn off all device arbitration bits (i.e. everything \ 223 * except arbitration enable bit). \ 224 */ \ 225 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \ 226 \ 227 /* \ 228 * Set the smart mode bit so that master aborts don't cause \ 229 * LBA to go into PCI fatal mode (required). \ 230 */ \ 231 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \ 232 } 233 234 235 #define LBA_CFG_PROBE(d, tok) { \ 236 /* \ 237 * Setup Vendor ID write and read back the address register \ 238 * to make sure that LBA is the bus master. \ 239 */ \ 240 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\ 241 /* \ 242 * Read address register to ensure that LBA is the bus master, \ 243 * which implies that DMA traffic has stopped when DMA arb is off. \ 244 */ \ 245 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 246 /* \ 247 * Generate a cfg write cycle (will have no affect on \ 248 * Vendor ID register since read-only). \ 249 */ \ 250 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \ 251 /* \ 252 * Make sure write has completed before proceeding further, \ 253 * i.e. before setting clear enable. \ 254 */ \ 255 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 256 } 257 258 259 /* 260 * HPREVISIT: 261 * -- Can't tell if config cycle got the error. 262 * 263 * OV bit is broken until rev 4.0, so can't use OV bit and 264 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle. 265 * 266 * As of rev 4.0, no longer need the error check. 267 * 268 * -- Even if we could tell, we still want to return -1 269 * for **ANY** error (not just master abort). 270 * 271 * -- Only clear non-fatal errors (we don't want to bring 272 * LBA out of pci-fatal mode). 273 * 274 * Actually, there is still a race in which 275 * we could be clearing a fatal error. We will 276 * live with this during our initial bus walk 277 * until rev 4.0 (no driver activity during 278 * initial bus walk). The initial bus walk 279 * has race conditions concerning the use of 280 * smart mode as well. 281 */ 282 283 #define LBA_MASTER_ABORT_ERROR 0xc 284 #define LBA_FATAL_ERROR 0x10 285 286 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ 287 u32 error_status = 0; \ 288 /* \ 289 * Set clear enable (CE) bit. Unset by HW when new \ 290 * errors are logged -- LBA HW ERS section 14.3.3). \ 291 */ \ 292 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \ 293 error_status = READ_REG32(base + LBA_ERROR_STATUS); \ 294 if ((error_status & 0x1f) != 0) { \ 295 /* \ 296 * Fail the config read request. \ 297 */ \ 298 error = 1; \ 299 if ((error_status & LBA_FATAL_ERROR) == 0) { \ 300 /* \ 301 * Clear error status (if fatal bit not set) by setting \ 302 * clear error log bit (CL). \ 303 */ \ 304 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \ 305 } \ 306 } \ 307 } 308 309 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \ 310 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); 311 312 #define LBA_CFG_ADDR_SETUP(d, addr) { \ 313 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 314 /* \ 315 * Read address register to ensure that LBA is the bus master, \ 316 * which implies that DMA traffic has stopped when DMA arb is off. \ 317 */ \ 318 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 319 } 320 321 322 #define LBA_CFG_RESTORE(d, base) { \ 323 /* \ 324 * Restore status control register (turn off clear enable). \ 325 */ \ 326 WRITE_REG32(status_control, base + LBA_STAT_CTL); \ 327 /* \ 328 * Restore error config register (turn off smart mode). \ 329 */ \ 330 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \ 331 /* \ 332 * Restore arb mask register (reenables DMA arbitration). \ 333 */ \ 334 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \ 335 } 336 337 338 339 static unsigned int 340 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) 341 { 342 u32 data = ~0U; 343 int error = 0; 344 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */ 345 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */ 346 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */ 347 348 LBA_CFG_SETUP(d, tok); 349 LBA_CFG_PROBE(d, tok); 350 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 351 if (!error) { 352 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 353 354 LBA_CFG_ADDR_SETUP(d, tok | reg); 355 switch (size) { 356 case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; 357 case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; 358 case 4: data = READ_REG32(data_reg); break; 359 } 360 } 361 LBA_CFG_RESTORE(d, d->hba.base_addr); 362 return(data); 363 } 364 365 366 static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 367 { 368 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 369 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; 370 u32 tok = LBA_CFG_TOK(local_bus, devfn); 371 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 372 373 if ((pos > 255) || (devfn > 255)) 374 return -EINVAL; 375 376 /* FIXME: B2K/C3600 workaround is always use old method... */ 377 /* if (!LBA_SKIP_PROBE(d)) */ { 378 /* original - Generate config cycle on broken elroy 379 with risk we will miss PCI bus errors. */ 380 *data = lba_rd_cfg(d, tok, pos, size); 381 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data); 382 return 0; 383 } 384 385 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) { 386 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos); 387 /* either don't want to look or know device isn't present. */ 388 *data = ~0U; 389 return(0); 390 } 391 392 /* Basic Algorithm 393 ** Should only get here on fully working LBA rev. 394 ** This is how simple the code should have been. 395 */ 396 LBA_CFG_ADDR_SETUP(d, tok | pos); 397 switch(size) { 398 case 1: *data = READ_REG8 (data_reg + (pos & 3)); break; 399 case 2: *data = READ_REG16(data_reg + (pos & 2)); break; 400 case 4: *data = READ_REG32(data_reg); break; 401 } 402 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data); 403 return 0; 404 } 405 406 407 static void 408 lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) 409 { 410 int error = 0; 411 u32 arb_mask = 0; 412 u32 error_config = 0; 413 u32 status_control = 0; 414 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 415 416 LBA_CFG_SETUP(d, tok); 417 LBA_CFG_ADDR_SETUP(d, tok | reg); 418 switch (size) { 419 case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; 420 case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; 421 case 4: WRITE_REG32(data, data_reg); break; 422 } 423 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 424 LBA_CFG_RESTORE(d, d->hba.base_addr); 425 } 426 427 428 /* 429 * LBA 4.0 config write code implements non-postable semantics 430 * by doing a read of CONFIG ADDR after the write. 431 */ 432 433 static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 434 { 435 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 436 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; 437 u32 tok = LBA_CFG_TOK(local_bus,devfn); 438 439 if ((pos > 255) || (devfn > 255)) 440 return -EINVAL; 441 442 if (!LBA_SKIP_PROBE(d)) { 443 /* Original Workaround */ 444 lba_wr_cfg(d, tok, pos, (u32) data, size); 445 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data); 446 return 0; 447 } 448 449 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) { 450 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data); 451 return 1; /* New Workaround */ 452 } 453 454 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data); 455 456 /* Basic Algorithm */ 457 LBA_CFG_ADDR_SETUP(d, tok | pos); 458 switch(size) { 459 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); 460 break; 461 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); 462 break; 463 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); 464 break; 465 } 466 /* flush posted write */ 467 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 468 return 0; 469 } 470 471 472 static struct pci_ops elroy_cfg_ops = { 473 .read = elroy_cfg_read, 474 .write = elroy_cfg_write, 475 }; 476 477 /* 478 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy 479 * TR4.0 as no additional bugs were found in this areea between Elroy and 480 * Mercury 481 */ 482 483 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 484 { 485 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 486 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; 487 u32 tok = LBA_CFG_TOK(local_bus, devfn); 488 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 489 490 if ((pos > 255) || (devfn > 255)) 491 return -EINVAL; 492 493 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 494 switch(size) { 495 case 1: 496 *data = READ_REG8(data_reg + (pos & 3)); 497 break; 498 case 2: 499 *data = READ_REG16(data_reg + (pos & 2)); 500 break; 501 case 4: 502 *data = READ_REG32(data_reg); break; 503 break; 504 } 505 506 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data); 507 return 0; 508 } 509 510 /* 511 * LBA 4.0 config write code implements non-postable semantics 512 * by doing a read of CONFIG ADDR after the write. 513 */ 514 515 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 516 { 517 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 518 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 519 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; 520 u32 tok = LBA_CFG_TOK(local_bus,devfn); 521 522 if ((pos > 255) || (devfn > 255)) 523 return -EINVAL; 524 525 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data); 526 527 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 528 switch(size) { 529 case 1: 530 WRITE_REG8 (data, data_reg + (pos & 3)); 531 break; 532 case 2: 533 WRITE_REG16(data, data_reg + (pos & 2)); 534 break; 535 case 4: 536 WRITE_REG32(data, data_reg); 537 break; 538 } 539 540 /* flush posted write */ 541 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 542 return 0; 543 } 544 545 static struct pci_ops mercury_cfg_ops = { 546 .read = mercury_cfg_read, 547 .write = mercury_cfg_write, 548 }; 549 550 551 static void 552 lba_bios_init(void) 553 { 554 DBG(MODULE_NAME ": lba_bios_init\n"); 555 } 556 557 558 #ifdef CONFIG_64BIT 559 560 /* 561 * truncate_pat_collision: Deal with overlaps or outright collisions 562 * between PAT PDC reported ranges. 563 * 564 * Broken PA8800 firmware will report lmmio range that 565 * overlaps with CPU HPA. Just truncate the lmmio range. 566 * 567 * BEWARE: conflicts with this lmmio range may be an 568 * elmmio range which is pointing down another rope. 569 * 570 * FIXME: only deals with one collision per range...theoretically we 571 * could have several. Supporting more than one collision will get messy. 572 */ 573 static unsigned long 574 truncate_pat_collision(struct resource *root, struct resource *new) 575 { 576 unsigned long start = new->start; 577 unsigned long end = new->end; 578 struct resource *tmp = root->child; 579 580 if (end <= start || start < root->start || !tmp) 581 return 0; 582 583 /* find first overlap */ 584 while (tmp && tmp->end < start) 585 tmp = tmp->sibling; 586 587 /* no entries overlap */ 588 if (!tmp) return 0; 589 590 /* found one that starts behind the new one 591 ** Don't need to do anything. 592 */ 593 if (tmp->start >= end) return 0; 594 595 if (tmp->start <= start) { 596 /* "front" of new one overlaps */ 597 new->start = tmp->end + 1; 598 599 if (tmp->end >= end) { 600 /* AACCKK! totally overlaps! drop this range. */ 601 return 1; 602 } 603 } 604 605 if (tmp->end < end ) { 606 /* "end" of new one overlaps */ 607 new->end = tmp->start - 1; 608 } 609 610 printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] " 611 "to [%lx,%lx]\n", 612 start, end, 613 (long)new->start, (long)new->end ); 614 615 return 0; /* truncation successful */ 616 } 617 618 /* 619 * extend_lmmio_len: extend lmmio range to maximum length 620 * 621 * This is needed at least on C8000 systems to get the ATI FireGL card 622 * working. On other systems we will currently not extend the lmmio space. 623 */ 624 static unsigned long 625 extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len) 626 { 627 struct resource *tmp; 628 629 /* exit if not a C8000 */ 630 if (boot_cpu_data.cpu_type < mako) 631 return end; 632 633 pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n", 634 end - start, lba_len); 635 636 lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */ 637 638 pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end); 639 640 641 end += lba_len; 642 if (end < start) /* fix overflow */ 643 end = -1ULL; 644 645 pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end); 646 647 /* first overlap */ 648 for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { 649 pr_debug("LBA: testing %pR\n", tmp); 650 if (tmp->start == start) 651 continue; /* ignore ourself */ 652 if (tmp->end < start) 653 continue; 654 if (tmp->start > end) 655 continue; 656 if (end >= tmp->start) 657 end = tmp->start - 1; 658 } 659 660 pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end); 661 662 /* return new end */ 663 return end; 664 } 665 666 #else 667 #define truncate_pat_collision(r,n) (0) 668 #endif 669 670 static void pcibios_allocate_bridge_resources(struct pci_dev *dev) 671 { 672 int idx; 673 struct resource *r; 674 675 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) { 676 r = &dev->resource[idx]; 677 if (!r->flags) 678 continue; 679 if (r->parent) /* Already allocated */ 680 continue; 681 if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) { 682 /* 683 * Something is wrong with the region. 684 * Invalidate the resource to prevent 685 * child resource allocations in this 686 * range. 687 */ 688 r->start = r->end = 0; 689 r->flags = 0; 690 } 691 } 692 } 693 694 static void pcibios_allocate_bus_resources(struct pci_bus *bus) 695 { 696 struct pci_bus *child; 697 698 /* Depth-First Search on bus tree */ 699 if (bus->self) 700 pcibios_allocate_bridge_resources(bus->self); 701 list_for_each_entry(child, &bus->children, node) 702 pcibios_allocate_bus_resources(child); 703 } 704 705 706 /* 707 ** The algorithm is generic code. 708 ** But it needs to access local data structures to get the IRQ base. 709 ** Could make this a "pci_fixup_irq(bus, region)" but not sure 710 ** it's worth it. 711 ** 712 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked. 713 ** Resources aren't allocated until recursive buswalk below HBA is completed. 714 */ 715 static void 716 lba_fixup_bus(struct pci_bus *bus) 717 { 718 struct pci_dev *dev; 719 #ifdef FBB_SUPPORT 720 u16 status; 721 #endif 722 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); 723 724 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n", 725 bus, (int)bus->busn_res.start, bus->bridge->platform_data); 726 727 /* 728 ** Properly Setup MMIO resources for this bus. 729 ** pci_alloc_primary_bus() mangles this. 730 */ 731 if (bus->parent) { 732 /* PCI-PCI Bridge */ 733 pci_read_bridge_bases(bus); 734 735 /* check and allocate bridge resources */ 736 pcibios_allocate_bus_resources(bus); 737 } else { 738 /* Host-PCI Bridge */ 739 int err; 740 741 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 742 ldev->hba.io_space.name, 743 ldev->hba.io_space.start, ldev->hba.io_space.end, 744 ldev->hba.io_space.flags); 745 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 746 ldev->hba.lmmio_space.name, 747 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, 748 ldev->hba.lmmio_space.flags); 749 750 err = request_resource(&ioport_resource, &(ldev->hba.io_space)); 751 if (err < 0) { 752 lba_dump_res(&ioport_resource, 2); 753 BUG(); 754 } 755 756 if (ldev->hba.elmmio_space.flags) { 757 err = request_resource(&iomem_resource, 758 &(ldev->hba.elmmio_space)); 759 if (err < 0) { 760 761 printk("FAILED: lba_fixup_bus() request for " 762 "elmmio_space [%lx/%lx]\n", 763 (long)ldev->hba.elmmio_space.start, 764 (long)ldev->hba.elmmio_space.end); 765 766 /* lba_dump_res(&iomem_resource, 2); */ 767 /* BUG(); */ 768 } 769 } 770 771 if (ldev->hba.lmmio_space.flags) { 772 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); 773 if (err < 0) { 774 printk(KERN_ERR "FAILED: lba_fixup_bus() request for " 775 "lmmio_space [%lx/%lx]\n", 776 (long)ldev->hba.lmmio_space.start, 777 (long)ldev->hba.lmmio_space.end); 778 } 779 } 780 781 #ifdef CONFIG_64BIT 782 /* GMMIO is distributed range. Every LBA/Rope gets part it. */ 783 if (ldev->hba.gmmio_space.flags) { 784 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); 785 if (err < 0) { 786 printk("FAILED: lba_fixup_bus() request for " 787 "gmmio_space [%lx/%lx]\n", 788 (long)ldev->hba.gmmio_space.start, 789 (long)ldev->hba.gmmio_space.end); 790 lba_dump_res(&iomem_resource, 2); 791 BUG(); 792 } 793 } 794 #endif 795 796 } 797 798 list_for_each_entry(dev, &bus->devices, bus_list) { 799 int i; 800 801 DBG("lba_fixup_bus() %s\n", pci_name(dev)); 802 803 /* Virtualize Device/Bridge Resources. */ 804 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 805 struct resource *res = &dev->resource[i]; 806 807 /* If resource not allocated - skip it */ 808 if (!res->start) 809 continue; 810 811 /* 812 ** FIXME: this will result in whinging for devices 813 ** that share expansion ROMs (think quad tulip), but 814 ** isn't harmful. 815 */ 816 pci_claim_resource(dev, i); 817 } 818 819 #ifdef FBB_SUPPORT 820 /* 821 ** If one device does not support FBB transfers, 822 ** No one on the bus can be allowed to use them. 823 */ 824 (void) pci_read_config_word(dev, PCI_STATUS, &status); 825 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK); 826 #endif 827 828 /* 829 ** P2PB's have no IRQs. ignore them. 830 */ 831 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 832 pcibios_init_bridge(dev); 833 continue; 834 } 835 836 /* Adjust INTERRUPT_LINE for this dev */ 837 iosapic_fixup_irq(ldev->iosapic_obj, dev); 838 } 839 840 #ifdef FBB_SUPPORT 841 /* FIXME/REVISIT - finish figuring out to set FBB on both 842 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL. 843 ** Can't fixup here anyway....garr... 844 */ 845 if (fbb_enable) { 846 if (bus->parent) { 847 u8 control; 848 /* enable on PPB */ 849 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); 850 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK); 851 852 } else { 853 /* enable on LBA */ 854 } 855 fbb_enable = PCI_COMMAND_FAST_BACK; 856 } 857 858 /* Lastly enable FBB/PERR/SERR on all devices too */ 859 list_for_each_entry(dev, &bus->devices, bus_list) { 860 (void) pci_read_config_word(dev, PCI_COMMAND, &status); 861 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable; 862 (void) pci_write_config_word(dev, PCI_COMMAND, status); 863 } 864 #endif 865 } 866 867 868 static struct pci_bios_ops lba_bios_ops = { 869 .init = lba_bios_init, 870 .fixup_bus = lba_fixup_bus, 871 }; 872 873 874 875 876 /******************************************************* 877 ** 878 ** LBA Sprockets "I/O Port" Space Accessor Functions 879 ** 880 ** This set of accessor functions is intended for use with 881 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes). 882 ** 883 ** Many PCI devices don't require use of I/O port space (eg Tulip, 884 ** NCR720) since they export the same registers to both MMIO and 885 ** I/O port space. In general I/O port space is slower than 886 ** MMIO since drivers are designed so PIO writes can be posted. 887 ** 888 ********************************************************/ 889 890 #define LBA_PORT_IN(size, mask) \ 891 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \ 892 { \ 893 u##size t; \ 894 t = READ_REG##size(astro_iop_base + addr); \ 895 DBG_PORT(" 0x%x\n", t); \ 896 return (t); \ 897 } 898 899 LBA_PORT_IN( 8, 3) 900 LBA_PORT_IN(16, 2) 901 LBA_PORT_IN(32, 0) 902 903 904 905 /* 906 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR 907 ** 908 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is 909 ** guarantee non-postable completion semantics - not avoid X4107. 910 ** The READ_U32 only guarantees the write data gets to elroy but 911 ** out to the PCI bus. We can't read stuff from I/O port space 912 ** since we don't know what has side-effects. Attempting to read 913 ** from configuration space would be suicidal given the number of 914 ** bugs in that elroy functionality. 915 ** 916 ** Description: 917 ** DMA read results can improperly pass PIO writes (X4107). The 918 ** result of this bug is that if a processor modifies a location in 919 ** memory after having issued PIO writes, the PIO writes are not 920 ** guaranteed to be completed before a PCI device is allowed to see 921 ** the modified data in a DMA read. 922 ** 923 ** Note that IKE bug X3719 in TR1 IKEs will result in the same 924 ** symptom. 925 ** 926 ** Workaround: 927 ** The workaround for this bug is to always follow a PIO write with 928 ** a PIO read to the same bus before starting DMA on that PCI bus. 929 ** 930 */ 931 #define LBA_PORT_OUT(size, mask) \ 932 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 933 { \ 934 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \ 935 WRITE_REG##size(val, astro_iop_base + addr); \ 936 if (LBA_DEV(d)->hw_rev < 3) \ 937 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \ 938 } 939 940 LBA_PORT_OUT( 8, 3) 941 LBA_PORT_OUT(16, 2) 942 LBA_PORT_OUT(32, 0) 943 944 945 static struct pci_port_ops lba_astro_port_ops = { 946 .inb = lba_astro_in8, 947 .inw = lba_astro_in16, 948 .inl = lba_astro_in32, 949 .outb = lba_astro_out8, 950 .outw = lba_astro_out16, 951 .outl = lba_astro_out32 952 }; 953 954 955 #ifdef CONFIG_64BIT 956 #define PIOP_TO_GMMIO(lba, addr) \ 957 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3)) 958 959 /******************************************************* 960 ** 961 ** LBA PAT "I/O Port" Space Accessor Functions 962 ** 963 ** This set of accessor functions is intended for use with 964 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes). 965 ** 966 ** This uses the PIOP space located in the first 64MB of GMMIO. 967 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way. 968 ** bits 1:0 stay the same. bits 15:2 become 25:12. 969 ** Then add the base and we can generate an I/O Port cycle. 970 ********************************************************/ 971 #undef LBA_PORT_IN 972 #define LBA_PORT_IN(size, mask) \ 973 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \ 974 { \ 975 u##size t; \ 976 DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \ 977 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \ 978 DBG_PORT(" 0x%x\n", t); \ 979 return (t); \ 980 } 981 982 LBA_PORT_IN( 8, 3) 983 LBA_PORT_IN(16, 2) 984 LBA_PORT_IN(32, 0) 985 986 987 #undef LBA_PORT_OUT 988 #define LBA_PORT_OUT(size, mask) \ 989 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \ 990 { \ 991 void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \ 992 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \ 993 WRITE_REG##size(val, where); \ 994 /* flush the I/O down to the elroy at least */ \ 995 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \ 996 } 997 998 LBA_PORT_OUT( 8, 3) 999 LBA_PORT_OUT(16, 2) 1000 LBA_PORT_OUT(32, 0) 1001 1002 1003 static struct pci_port_ops lba_pat_port_ops = { 1004 .inb = lba_pat_in8, 1005 .inw = lba_pat_in16, 1006 .inl = lba_pat_in32, 1007 .outb = lba_pat_out8, 1008 .outw = lba_pat_out16, 1009 .outl = lba_pat_out32 1010 }; 1011 1012 1013 1014 /* 1015 ** make range information from PDC available to PCI subsystem. 1016 ** We make the PDC call here in order to get the PCI bus range 1017 ** numbers. The rest will get forwarded in pcibios_fixup_bus(). 1018 ** We don't have a struct pci_bus assigned to us yet. 1019 */ 1020 static void 1021 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1022 { 1023 unsigned long bytecnt; 1024 long io_count; 1025 long status; /* PDC return status */ 1026 long pa_count; 1027 pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell; /* PA_VIEW */ 1028 pdc_pat_cell_mod_maddr_block_t *io_pdc_cell; /* IO_VIEW */ 1029 int i; 1030 1031 pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL); 1032 if (!pa_pdc_cell) 1033 return; 1034 1035 io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL); 1036 if (!io_pdc_cell) { 1037 kfree(pa_pdc_cell); 1038 return; 1039 } 1040 1041 /* return cell module (IO view) */ 1042 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 1043 PA_VIEW, pa_pdc_cell); 1044 pa_count = pa_pdc_cell->mod[1]; 1045 1046 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 1047 IO_VIEW, io_pdc_cell); 1048 io_count = io_pdc_cell->mod[1]; 1049 1050 /* We've already done this once for device discovery...*/ 1051 if (status != PDC_OK) { 1052 panic("pdc_pat_cell_module() call failed for LBA!\n"); 1053 } 1054 1055 if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) { 1056 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n"); 1057 } 1058 1059 /* 1060 ** Inspect the resources PAT tells us about 1061 */ 1062 for (i = 0; i < pa_count; i++) { 1063 struct { 1064 unsigned long type; 1065 unsigned long start; 1066 unsigned long end; /* aka finish */ 1067 } *p, *io; 1068 struct resource *r; 1069 1070 p = (void *) &(pa_pdc_cell->mod[2+i*3]); 1071 io = (void *) &(io_pdc_cell->mod[2+i*3]); 1072 1073 /* Convert the PAT range data to PCI "struct resource" */ 1074 switch(p->type & 0xff) { 1075 case PAT_PBNUM: 1076 lba_dev->hba.bus_num.start = p->start; 1077 lba_dev->hba.bus_num.end = p->end; 1078 lba_dev->hba.bus_num.flags = IORESOURCE_BUS; 1079 break; 1080 1081 case PAT_LMMIO: 1082 /* used to fix up pre-initialized MEM BARs */ 1083 if (!lba_dev->hba.lmmio_space.flags) { 1084 unsigned long lba_len; 1085 1086 lba_len = ~READ_REG32(lba_dev->hba.base_addr 1087 + LBA_LMMIO_MASK); 1088 if ((p->end - p->start) != lba_len) 1089 p->end = extend_lmmio_len(p->start, 1090 p->end, lba_len); 1091 1092 sprintf(lba_dev->hba.lmmio_name, 1093 "PCI%02x LMMIO", 1094 (int)lba_dev->hba.bus_num.start); 1095 lba_dev->hba.lmmio_space_offset = p->start - 1096 io->start; 1097 r = &lba_dev->hba.lmmio_space; 1098 r->name = lba_dev->hba.lmmio_name; 1099 } else if (!lba_dev->hba.elmmio_space.flags) { 1100 sprintf(lba_dev->hba.elmmio_name, 1101 "PCI%02x ELMMIO", 1102 (int)lba_dev->hba.bus_num.start); 1103 r = &lba_dev->hba.elmmio_space; 1104 r->name = lba_dev->hba.elmmio_name; 1105 } else { 1106 printk(KERN_WARNING MODULE_NAME 1107 " only supports 2 LMMIO resources!\n"); 1108 break; 1109 } 1110 1111 r->start = p->start; 1112 r->end = p->end; 1113 r->flags = IORESOURCE_MEM; 1114 r->parent = r->sibling = r->child = NULL; 1115 break; 1116 1117 case PAT_GMMIO: 1118 /* MMIO space > 4GB phys addr; for 64-bit BAR */ 1119 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", 1120 (int)lba_dev->hba.bus_num.start); 1121 r = &lba_dev->hba.gmmio_space; 1122 r->name = lba_dev->hba.gmmio_name; 1123 r->start = p->start; 1124 r->end = p->end; 1125 r->flags = IORESOURCE_MEM; 1126 r->parent = r->sibling = r->child = NULL; 1127 break; 1128 1129 case PAT_NPIOP: 1130 printk(KERN_WARNING MODULE_NAME 1131 " range[%d] : ignoring NPIOP (0x%lx)\n", 1132 i, p->start); 1133 break; 1134 1135 case PAT_PIOP: 1136 /* 1137 ** Postable I/O port space is per PCI host adapter. 1138 ** base of 64MB PIOP region 1139 */ 1140 lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024); 1141 1142 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1143 (int)lba_dev->hba.bus_num.start); 1144 r = &lba_dev->hba.io_space; 1145 r->name = lba_dev->hba.io_name; 1146 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); 1147 r->end = r->start + HBA_PORT_SPACE_SIZE - 1; 1148 r->flags = IORESOURCE_IO; 1149 r->parent = r->sibling = r->child = NULL; 1150 break; 1151 1152 default: 1153 printk(KERN_WARNING MODULE_NAME 1154 " range[%d] : unknown pat range type (0x%lx)\n", 1155 i, p->type & 0xff); 1156 break; 1157 } 1158 } 1159 1160 kfree(pa_pdc_cell); 1161 kfree(io_pdc_cell); 1162 } 1163 #else 1164 /* keep compiler from complaining about missing declarations */ 1165 #define lba_pat_port_ops lba_astro_port_ops 1166 #define lba_pat_resources(pa_dev, lba_dev) 1167 #endif /* CONFIG_64BIT */ 1168 1169 1170 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *); 1171 extern void sba_directed_lmmio(struct parisc_device *, struct resource *); 1172 1173 1174 static void 1175 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 1176 { 1177 struct resource *r; 1178 int lba_num; 1179 1180 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; 1181 1182 /* 1183 ** With "legacy" firmware, the lowest byte of FW_SCRATCH 1184 ** represents bus->secondary and the second byte represents 1185 ** bus->subsidiary (i.e. highest PPB programmed by firmware). 1186 ** PCI bus walk *should* end up with the same result. 1187 ** FIXME: But we don't have sanity checks in PCI or LBA. 1188 */ 1189 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); 1190 r = &(lba_dev->hba.bus_num); 1191 r->name = "LBA PCI Busses"; 1192 r->start = lba_num & 0xff; 1193 r->end = (lba_num>>8) & 0xff; 1194 r->flags = IORESOURCE_BUS; 1195 1196 /* Set up local PCI Bus resources - we don't need them for 1197 ** Legacy boxes but it's nice to see in /proc/iomem. 1198 */ 1199 r = &(lba_dev->hba.lmmio_space); 1200 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", 1201 (int)lba_dev->hba.bus_num.start); 1202 r->name = lba_dev->hba.lmmio_name; 1203 1204 #if 1 1205 /* We want the CPU -> IO routing of addresses. 1206 * The SBA BASE/MASK registers control CPU -> IO routing. 1207 * Ask SBA what is routed to this rope/LBA. 1208 */ 1209 sba_distributed_lmmio(pa_dev, r); 1210 #else 1211 /* 1212 * The LBA BASE/MASK registers control IO -> System routing. 1213 * 1214 * The following code works but doesn't get us what we want. 1215 * Well, only because firmware (v5.0) on C3000 doesn't program 1216 * the LBA BASE/MASE registers to be the exact inverse of 1217 * the corresponding SBA registers. Other Astro/Pluto 1218 * based platform firmware may do it right. 1219 * 1220 * Should someone want to mess with MSI, they may need to 1221 * reprogram LBA BASE/MASK registers. Thus preserve the code 1222 * below until MSI is known to work on C3000/A500/N4000/RP3440. 1223 * 1224 * Using the code below, /proc/iomem shows: 1225 * ... 1226 * f0000000-f0ffffff : PCI00 LMMIO 1227 * f05d0000-f05d0000 : lcd_data 1228 * f05d0008-f05d0008 : lcd_cmd 1229 * f1000000-f1ffffff : PCI01 LMMIO 1230 * f4000000-f4ffffff : PCI02 LMMIO 1231 * f4000000-f4001fff : sym53c8xx 1232 * f4002000-f4003fff : sym53c8xx 1233 * f4004000-f40043ff : sym53c8xx 1234 * f4005000-f40053ff : sym53c8xx 1235 * f4007000-f4007fff : ohci_hcd 1236 * f4008000-f40083ff : tulip 1237 * f6000000-f6ffffff : PCI03 LMMIO 1238 * f8000000-fbffffff : PCI00 ELMMIO 1239 * fa100000-fa4fffff : stifb mmio 1240 * fb000000-fb1fffff : stifb fb 1241 * 1242 * But everything listed under PCI02 actually lives under PCI00. 1243 * This is clearly wrong. 1244 * 1245 * Asking SBA how things are routed tells the correct story: 1246 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000 1247 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006 1248 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004 1249 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000 1250 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000 1251 * 1252 * Which looks like this in /proc/iomem: 1253 * f4000000-f47fffff : PCI00 LMMIO 1254 * f4000000-f4001fff : sym53c8xx 1255 * ...[deteled core devices - same as above]... 1256 * f4008000-f40083ff : tulip 1257 * f4800000-f4ffffff : PCI01 LMMIO 1258 * f6000000-f67fffff : PCI02 LMMIO 1259 * f7000000-f77fffff : PCI03 LMMIO 1260 * f9000000-f9ffffff : PCI02 ELMMIO 1261 * fa000000-fbffffff : PCI03 ELMMIO 1262 * fa100000-fa4fffff : stifb mmio 1263 * fb000000-fb1fffff : stifb fb 1264 * 1265 * ie all Built-in core are under now correctly under PCI00. 1266 * The "PCI02 ELMMIO" directed range is for: 1267 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2 1268 * 1269 * All is well now. 1270 */ 1271 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); 1272 if (r->start & 1) { 1273 unsigned long rsize; 1274 1275 r->flags = IORESOURCE_MEM; 1276 /* mmio_mask also clears Enable bit */ 1277 r->start &= mmio_mask; 1278 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); 1279 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); 1280 1281 /* 1282 ** Each rope only gets part of the distributed range. 1283 ** Adjust "window" for this rope. 1284 */ 1285 rsize /= ROPES_PER_IOC; 1286 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start); 1287 r->end = r->start + rsize; 1288 } else { 1289 r->end = r->start = 0; /* Not enabled. */ 1290 } 1291 #endif 1292 1293 /* 1294 ** "Directed" ranges are used when the "distributed range" isn't 1295 ** sufficient for all devices below a given LBA. Typically devices 1296 ** like graphics cards or X25 may need a directed range when the 1297 ** bus has multiple slots (ie multiple devices) or the device 1298 ** needs more than the typical 4 or 8MB a distributed range offers. 1299 ** 1300 ** The main reason for ignoring it now frigging complications. 1301 ** Directed ranges may overlap (and have precedence) over 1302 ** distributed ranges. Or a distributed range assigned to a unused 1303 ** rope may be used by a directed range on a different rope. 1304 ** Support for graphics devices may require fixing this 1305 ** since they may be assigned a directed range which overlaps 1306 ** an existing (but unused portion of) distributed range. 1307 */ 1308 r = &(lba_dev->hba.elmmio_space); 1309 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", 1310 (int)lba_dev->hba.bus_num.start); 1311 r->name = lba_dev->hba.elmmio_name; 1312 1313 #if 1 1314 /* See comment which precedes call to sba_directed_lmmio() */ 1315 sba_directed_lmmio(pa_dev, r); 1316 #else 1317 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); 1318 1319 if (r->start & 1) { 1320 unsigned long rsize; 1321 r->flags = IORESOURCE_MEM; 1322 /* mmio_mask also clears Enable bit */ 1323 r->start &= mmio_mask; 1324 r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start); 1325 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); 1326 r->end = r->start + ~rsize; 1327 } 1328 #endif 1329 1330 r = &(lba_dev->hba.io_space); 1331 sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1332 (int)lba_dev->hba.bus_num.start); 1333 r->name = lba_dev->hba.io_name; 1334 r->flags = IORESOURCE_IO; 1335 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; 1336 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); 1337 1338 /* Virtualize the I/O Port space ranges */ 1339 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); 1340 r->start |= lba_num; 1341 r->end |= lba_num; 1342 } 1343 1344 1345 /************************************************************************** 1346 ** 1347 ** LBA initialization code (HW and SW) 1348 ** 1349 ** o identify LBA chip itself 1350 ** o initialize LBA chip modes (HardFail) 1351 ** o FIXME: initialize DMA hints for reasonable defaults 1352 ** o enable configuration functions 1353 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked) 1354 ** 1355 **************************************************************************/ 1356 1357 static int __init 1358 lba_hw_init(struct lba_device *d) 1359 { 1360 u32 stat; 1361 u32 bus_reset; /* PDC_PAT_BUG */ 1362 1363 #if 0 1364 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n", 1365 d->hba.base_addr, 1366 READ_REG64(d->hba.base_addr + LBA_STAT_CTL), 1367 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), 1368 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), 1369 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); 1370 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n", 1371 READ_REG64(d->hba.base_addr + LBA_ARB_MASK), 1372 READ_REG64(d->hba.base_addr + LBA_ARB_PRI), 1373 READ_REG64(d->hba.base_addr + LBA_ARB_MODE), 1374 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); 1375 printk(KERN_DEBUG " HINT cfg 0x%Lx\n", 1376 READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); 1377 printk(KERN_DEBUG " HINT reg "); 1378 { int i; 1379 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8) 1380 printk(" %Lx", READ_REG64(d->hba.base_addr + i)); 1381 } 1382 printk("\n"); 1383 #endif /* DEBUG_LBA_PAT */ 1384 1385 #ifdef CONFIG_64BIT 1386 /* 1387 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support 1388 * Only N-Class and up can really make use of Get slot status. 1389 * maybe L-class too but I've never played with it there. 1390 */ 1391 #endif 1392 1393 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */ 1394 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; 1395 if (bus_reset) { 1396 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n"); 1397 } 1398 1399 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); 1400 if (stat & LBA_SMART_MODE) { 1401 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n"); 1402 stat &= ~LBA_SMART_MODE; 1403 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); 1404 } 1405 1406 1407 /* 1408 * Hard Fail vs. Soft Fail on PCI "Master Abort". 1409 * 1410 * "Master Abort" means the MMIO transaction timed out - usually due to 1411 * the device not responding to an MMIO read. We would like HF to be 1412 * enabled to find driver problems, though it means the system will 1413 * crash with a HPMC. 1414 * 1415 * In SoftFail mode "~0L" is returned as a result of a timeout on the 1416 * pci bus. This is like how PCI busses on x86 and most other 1417 * architectures behave. In order to increase compatibility with 1418 * existing (x86) PCI hardware and existing Linux drivers we enable 1419 * Soft Faul mode on PA-RISC now too. 1420 */ 1421 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); 1422 #if defined(ENABLE_HARDFAIL) 1423 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); 1424 #else 1425 WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); 1426 #endif 1427 1428 /* 1429 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal 1430 ** if it's not already set. If we just cleared the PCI Bus Reset 1431 ** signal, wait a bit for the PCI devices to recover and setup. 1432 */ 1433 if (bus_reset) 1434 mdelay(pci_post_reset_delay); 1435 1436 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { 1437 /* 1438 ** PDC_PAT_BUG: PDC rev 40.48 on L2000. 1439 ** B2000/C3600/J6000 also have this problem? 1440 ** 1441 ** Elroys with hot pluggable slots don't get configured 1442 ** correctly if the slot is empty. ARB_MASK is set to 0 1443 ** and we can't master transactions on the bus if it's 1444 ** not at least one. 0x3 enables elroy and first slot. 1445 */ 1446 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n"); 1447 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); 1448 } 1449 1450 /* 1451 ** FIXME: Hint registers are programmed with default hint 1452 ** values by firmware. Hints should be sane even if we 1453 ** can't reprogram them the way drivers want. 1454 */ 1455 return 0; 1456 } 1457 1458 /* 1459 * Unfortunately, when firmware numbers busses, it doesn't take into account 1460 * Cardbus bridges. So we have to renumber the busses to suit ourselves. 1461 * Elroy/Mercury don't actually know what bus number they're attached to; 1462 * we use bus 0 to indicate the directly attached bus and any other bus 1463 * number will be taken care of by the PCI-PCI bridge. 1464 */ 1465 static unsigned int lba_next_bus = 0; 1466 1467 /* 1468 * Determine if lba should claim this chip (return 0) or not (return 1). 1469 * If so, initialize the chip and tell other partners in crime they 1470 * have work to do. 1471 */ 1472 static int __init 1473 lba_driver_probe(struct parisc_device *dev) 1474 { 1475 struct lba_device *lba_dev; 1476 LIST_HEAD(resources); 1477 struct pci_bus *lba_bus; 1478 struct pci_ops *cfg_ops; 1479 u32 func_class; 1480 void *tmp_obj; 1481 char *version; 1482 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096); 1483 int max; 1484 1485 /* Read HW Rev First */ 1486 func_class = READ_REG32(addr + LBA_FCLASS); 1487 1488 if (IS_ELROY(dev)) { 1489 func_class &= 0xf; 1490 switch (func_class) { 1491 case 0: version = "TR1.0"; break; 1492 case 1: version = "TR2.0"; break; 1493 case 2: version = "TR2.1"; break; 1494 case 3: version = "TR2.2"; break; 1495 case 4: version = "TR3.0"; break; 1496 case 5: version = "TR4.0"; break; 1497 default: version = "TR4+"; 1498 } 1499 1500 printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n", 1501 version, func_class & 0xf, (long)dev->hpa.start); 1502 1503 if (func_class < 2) { 1504 printk(KERN_WARNING "Can't support LBA older than " 1505 "TR2.1 - continuing under adversity.\n"); 1506 } 1507 1508 #if 0 1509 /* Elroy TR4.0 should work with simple algorithm. 1510 But it doesn't. Still missing something. *sigh* 1511 */ 1512 if (func_class > 4) { 1513 cfg_ops = &mercury_cfg_ops; 1514 } else 1515 #endif 1516 { 1517 cfg_ops = &elroy_cfg_ops; 1518 } 1519 1520 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) { 1521 int major, minor; 1522 1523 func_class &= 0xff; 1524 major = func_class >> 4, minor = func_class & 0xf; 1525 1526 /* We could use one printk for both Elroy and Mercury, 1527 * but for the mask for func_class. 1528 */ 1529 printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n", 1530 IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major, 1531 minor, func_class, (long)dev->hpa.start); 1532 1533 cfg_ops = &mercury_cfg_ops; 1534 } else { 1535 printk(KERN_ERR "Unknown LBA found at 0x%lx\n", 1536 (long)dev->hpa.start); 1537 return -ENODEV; 1538 } 1539 1540 /* Tell I/O SAPIC driver we have a IRQ handler/region. */ 1541 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE); 1542 1543 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't 1544 ** have an IRT entry will get NULL back from iosapic code. 1545 */ 1546 1547 lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL); 1548 if (!lba_dev) { 1549 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n"); 1550 return(1); 1551 } 1552 1553 1554 /* ---------- First : initialize data we already have --------- */ 1555 1556 lba_dev->hw_rev = func_class; 1557 lba_dev->hba.base_addr = addr; 1558 lba_dev->hba.dev = dev; 1559 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ 1560 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ 1561 parisc_set_drvdata(dev, lba_dev); 1562 1563 /* ------------ Second : initialize common stuff ---------- */ 1564 pci_bios = &lba_bios_ops; 1565 pcibios_register_hba(&lba_dev->hba); 1566 spin_lock_init(&lba_dev->lba_lock); 1567 1568 if (lba_hw_init(lba_dev)) 1569 return(1); 1570 1571 /* ---------- Third : setup I/O Port and MMIO resources --------- */ 1572 1573 if (is_pdc_pat()) { 1574 /* PDC PAT firmware uses PIOP region of GMMIO space. */ 1575 pci_port = &lba_pat_port_ops; 1576 /* Go ask PDC PAT what resources this LBA has */ 1577 lba_pat_resources(dev, lba_dev); 1578 } else { 1579 if (!astro_iop_base) { 1580 /* Sprockets PDC uses NPIOP region */ 1581 astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024); 1582 pci_port = &lba_astro_port_ops; 1583 } 1584 1585 /* Poke the chip a bit for /proc output */ 1586 lba_legacy_resources(dev, lba_dev); 1587 } 1588 1589 if (lba_dev->hba.bus_num.start < lba_next_bus) 1590 lba_dev->hba.bus_num.start = lba_next_bus; 1591 1592 /* Overlaps with elmmio can (and should) fail here. 1593 * We will prune (or ignore) the distributed range. 1594 * 1595 * FIXME: SBA code should register all elmmio ranges first. 1596 * that would take care of elmmio ranges routed 1597 * to a different rope (already discovered) from 1598 * getting registered *after* LBA code has already 1599 * registered it's distributed lmmio range. 1600 */ 1601 if (truncate_pat_collision(&iomem_resource, 1602 &(lba_dev->hba.lmmio_space))) { 1603 printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n", 1604 (long)lba_dev->hba.lmmio_space.start, 1605 (long)lba_dev->hba.lmmio_space.end); 1606 lba_dev->hba.lmmio_space.flags = 0; 1607 } 1608 1609 pci_add_resource_offset(&resources, &lba_dev->hba.io_space, 1610 HBA_PORT_BASE(lba_dev->hba.hba_num)); 1611 if (lba_dev->hba.elmmio_space.flags) 1612 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space, 1613 lba_dev->hba.lmmio_space_offset); 1614 if (lba_dev->hba.lmmio_space.flags) 1615 pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space, 1616 lba_dev->hba.lmmio_space_offset); 1617 if (lba_dev->hba.gmmio_space.flags) { 1618 /* Not registering GMMIO space - according to docs it's not 1619 * even used on HP-UX. */ 1620 /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */ 1621 } 1622 1623 pci_add_resource(&resources, &lba_dev->hba.bus_num); 1624 1625 dev->dev.platform_data = lba_dev; 1626 lba_bus = lba_dev->hba.hba_bus = 1627 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start, 1628 cfg_ops, NULL, &resources); 1629 if (!lba_bus) { 1630 pci_free_resource_list(&resources); 1631 return 0; 1632 } 1633 1634 max = pci_scan_child_bus(lba_bus); 1635 1636 /* This is in lieu of calling pci_assign_unassigned_resources() */ 1637 if (is_pdc_pat()) { 1638 /* assign resources to un-initialized devices */ 1639 1640 DBG_PAT("LBA pci_bus_size_bridges()\n"); 1641 pci_bus_size_bridges(lba_bus); 1642 1643 DBG_PAT("LBA pci_bus_assign_resources()\n"); 1644 pci_bus_assign_resources(lba_bus); 1645 1646 #ifdef DEBUG_LBA_PAT 1647 DBG_PAT("\nLBA PIOP resource tree\n"); 1648 lba_dump_res(&lba_dev->hba.io_space, 2); 1649 DBG_PAT("\nLBA LMMIO resource tree\n"); 1650 lba_dump_res(&lba_dev->hba.lmmio_space, 2); 1651 #endif 1652 } 1653 1654 /* 1655 ** Once PCI register ops has walked the bus, access to config 1656 ** space is restricted. Avoids master aborts on config cycles. 1657 ** Early LBA revs go fatal on *any* master abort. 1658 */ 1659 if (cfg_ops == &elroy_cfg_ops) { 1660 lba_dev->flags |= LBA_FLAG_SKIP_PROBE; 1661 } 1662 1663 lba_next_bus = max + 1; 1664 pci_bus_add_devices(lba_bus); 1665 1666 /* Whew! Finally done! Tell services we got this one covered. */ 1667 return 0; 1668 } 1669 1670 static const struct parisc_device_id lba_tbl[] __initconst = { 1671 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa }, 1672 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa }, 1673 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa }, 1674 { 0, } 1675 }; 1676 1677 static struct parisc_driver lba_driver __refdata = { 1678 .name = MODULE_NAME, 1679 .id_table = lba_tbl, 1680 .probe = lba_driver_probe, 1681 }; 1682 1683 /* 1684 ** One time initialization to let the world know the LBA was found. 1685 ** Must be called exactly once before pci_init(). 1686 */ 1687 void __init lba_init(void) 1688 { 1689 register_parisc_driver(&lba_driver); 1690 } 1691 1692 /* 1693 ** Initialize the IBASE/IMASK registers for LBA (Elroy). 1694 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA). 1695 ** sba_iommu is responsible for locking (none needed at init time). 1696 */ 1697 void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) 1698 { 1699 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096); 1700 1701 imask <<= 2; /* adjust for hints - 2 more bits */ 1702 1703 /* Make sure we aren't trying to set bits that aren't writeable. */ 1704 WARN_ON((ibase & 0x001fffff) != 0); 1705 WARN_ON((imask & 0x001fffff) != 0); 1706 1707 DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask); 1708 WRITE_REG32( imask, base_addr + LBA_IMASK); 1709 WRITE_REG32( ibase, base_addr + LBA_IBASE); 1710 iounmap(base_addr); 1711 } 1712 1713 1714 /* 1715 * The design of the Diva management card in rp34x0 machines (rp3410, rp3440) 1716 * seems rushed, so that many built-in components simply don't work. 1717 * The following quirks disable the serial AUX port and the built-in ATI RV100 1718 * Radeon 7000 graphics card which both don't have any external connectors and 1719 * thus are useless, and even worse, e.g. the AUX port occupies ttyS0 and as 1720 * such makes those machines the only PARISC machines on which we can't use 1721 * ttyS0 as boot console. 1722 */ 1723 static void quirk_diva_ati_card(struct pci_dev *dev) 1724 { 1725 if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || 1726 dev->subsystem_device != 0x1292) 1727 return; 1728 1729 dev_info(&dev->dev, "Hiding Diva built-in ATI card"); 1730 dev->device = 0; 1731 } 1732 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, 1733 quirk_diva_ati_card); 1734 1735 static void quirk_diva_aux_disable(struct pci_dev *dev) 1736 { 1737 if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || 1738 dev->subsystem_device != 0x1291) 1739 return; 1740 1741 dev_info(&dev->dev, "Hiding Diva built-in AUX serial device"); 1742 dev->device = 0; 1743 } 1744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 1745 quirk_diva_aux_disable); 1746 1747 static void quirk_tosca_aux_disable(struct pci_dev *dev) 1748 { 1749 if (dev->subsystem_vendor != PCI_VENDOR_ID_HP || 1750 dev->subsystem_device != 0x104a) 1751 return; 1752 1753 dev_info(&dev->dev, "Hiding Tosca secondary built-in AUX serial device"); 1754 dev->device = 0; 1755 } 1756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 1757 quirk_tosca_aux_disable); 1758