1 /* 2 ** I/O Sapic Driver - PCI interrupt line support 3 ** 4 ** (c) Copyright 1999 Grant Grundler 5 ** (c) Copyright 1999 Hewlett-Packard Company 6 ** 7 ** This program is free software; you can redistribute it and/or modify 8 ** it under the terms of the GNU General Public License as published by 9 ** the Free Software Foundation; either version 2 of the License, or 10 ** (at your option) any later version. 11 ** 12 ** The I/O sapic driver manages the Interrupt Redirection Table which is 13 ** the control logic to convert PCI line based interrupts into a Message 14 ** Signaled Interrupt (aka Transaction Based Interrupt, TBI). 15 ** 16 ** Acronyms 17 ** -------- 18 ** HPA Hard Physical Address (aka MMIO address) 19 ** IRQ Interrupt ReQuest. Implies Line based interrupt. 20 ** IRT Interrupt Routing Table (provided by PAT firmware) 21 ** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA 22 ** table which is implemented in I/O SAPIC. 23 ** ISR Interrupt Service Routine. aka Interrupt handler. 24 ** MSI Message Signaled Interrupt. PCI 2.2 functionality. 25 ** aka Transaction Based Interrupt (or TBI). 26 ** PA Precision Architecture. HP's RISC architecture. 27 ** RISC Reduced Instruction Set Computer. 28 ** 29 ** 30 ** What's a Message Signalled Interrupt? 31 ** ------------------------------------- 32 ** MSI is a write transaction which targets a processor and is similar 33 ** to a processor write to memory or MMIO. MSIs can be generated by I/O 34 ** devices as well as processors and require *architecture* to work. 35 ** 36 ** PA only supports MSI. So I/O subsystems must either natively generate 37 ** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs 38 ** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which 39 ** acts on behalf of a processor. 40 ** 41 ** MSI allows any I/O device to interrupt any processor. This makes 42 ** load balancing of the interrupt processing possible on an SMP platform. 43 ** Interrupts are also ordered WRT to DMA data. It's possible on I/O 44 ** coherent systems to completely eliminate PIO reads from the interrupt 45 ** path. The device and driver must be designed and implemented to 46 ** guarantee all DMA has been issued (issues about atomicity here) 47 ** before the MSI is issued. I/O status can then safely be read from 48 ** DMA'd data by the ISR. 49 ** 50 ** 51 ** PA Firmware 52 ** ----------- 53 ** PA-RISC platforms have two fundamentally different types of firmware. 54 ** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register 55 ** and BARs similar to a traditional PC BIOS. 56 ** The newer "PAT" firmware supports PDC calls which return tables. 57 ** PAT firmware only initializes the PCI Console and Boot interface. 58 ** With these tables, the OS can program all other PCI devices. 59 ** 60 ** One such PAT PDC call returns the "Interrupt Routing Table" (IRT). 61 ** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC 62 ** input line. If the IRT is not available, this driver assumes 63 ** INTERRUPT_LINE register has been programmed by firmware. The latter 64 ** case also means online addition of PCI cards can NOT be supported 65 ** even if HW support is present. 66 ** 67 ** All platforms with PAT firmware to date (Oct 1999) use one Interrupt 68 ** Routing Table for the entire platform. 69 ** 70 ** Where's the iosapic? 71 ** -------------------- 72 ** I/O sapic is part of the "Core Electronics Complex". And on HP platforms 73 ** it's integrated as part of the PCI bus adapter, "lba". So no bus walk 74 ** will discover I/O Sapic. I/O Sapic driver learns about each device 75 ** when lba driver advertises the presence of the I/O sapic by calling 76 ** iosapic_register(). 77 ** 78 ** 79 ** IRQ handling notes 80 ** ------------------ 81 ** The IO-SAPIC can indicate to the CPU which interrupt was asserted. 82 ** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per 83 ** IO-SAPIC interrupt and call the device driver's handler directly. 84 ** The IO-SAPIC driver hijacks the CPU interrupt handler so it can 85 ** issue the End Of Interrupt command to the IO-SAPIC. 86 ** 87 ** Overview of exported iosapic functions 88 ** -------------------------------------- 89 ** (caveat: code isn't finished yet - this is just the plan) 90 ** 91 ** iosapic_init: 92 ** o initialize globals (lock, etc) 93 ** o try to read IRT. Presence of IRT determines if this is 94 ** a PAT platform or not. 95 ** 96 ** iosapic_register(): 97 ** o create iosapic_info instance data structure 98 ** o allocate vector_info array for this iosapic 99 ** o initialize vector_info - read corresponding IRdT? 100 ** 101 ** iosapic_xlate_pin: (only called by fixup_irq for PAT platform) 102 ** o intr_pin = read cfg (INTERRUPT_PIN); 103 ** o if (device under PCI-PCI bridge) 104 ** translate slot/pin 105 ** 106 ** iosapic_fixup_irq: 107 ** o if PAT platform (IRT present) 108 ** intr_pin = iosapic_xlate_pin(isi,pcidev): 109 ** intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin) 110 ** save IRT entry into vector_info later 111 ** write cfg INTERRUPT_LINE (with intr_line)? 112 ** else 113 ** intr_line = pcidev->irq 114 ** IRT pointer = NULL 115 ** endif 116 ** o locate vector_info (needs: isi, intr_line) 117 ** o allocate processor "irq" and get txn_addr/data 118 ** o request_irq(processor_irq, iosapic_interrupt, vector_info,...) 119 ** 120 ** iosapic_enable_irq: 121 ** o clear any pending IRQ on that line 122 ** o enable IRdT - call enable_irq(vector[line]->processor_irq) 123 ** o write EOI in case line is already asserted. 124 ** 125 ** iosapic_disable_irq: 126 ** o disable IRdT - call disable_irq(vector[line]->processor_irq) 127 */ 128 129 #include <linux/pci.h> 130 131 #include <asm/pdc.h> 132 #include <asm/pdcpat.h> 133 #ifdef CONFIG_SUPERIO 134 #include <asm/superio.h> 135 #endif 136 137 #include <asm/ropes.h> 138 #include "iosapic_private.h" 139 140 #define MODULE_NAME "iosapic" 141 142 /* "local" compile flags */ 143 #undef PCI_BRIDGE_FUNCS 144 #undef DEBUG_IOSAPIC 145 #undef DEBUG_IOSAPIC_IRT 146 147 148 #ifdef DEBUG_IOSAPIC 149 #define DBG(x...) printk(x) 150 #else /* DEBUG_IOSAPIC */ 151 #define DBG(x...) 152 #endif /* DEBUG_IOSAPIC */ 153 154 #ifdef DEBUG_IOSAPIC_IRT 155 #define DBG_IRT(x...) printk(x) 156 #else 157 #define DBG_IRT(x...) 158 #endif 159 160 #ifdef CONFIG_64BIT 161 #define COMPARE_IRTE_ADDR(irte, hpa) ((irte)->dest_iosapic_addr == (hpa)) 162 #else 163 #define COMPARE_IRTE_ADDR(irte, hpa) \ 164 ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL)) 165 #endif 166 167 #define IOSAPIC_REG_SELECT 0x00 168 #define IOSAPIC_REG_WINDOW 0x10 169 #define IOSAPIC_REG_EOI 0x40 170 171 #define IOSAPIC_REG_VERSION 0x1 172 173 #define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2) 174 #define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2) 175 176 static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg) 177 { 178 writel(reg, iosapic + IOSAPIC_REG_SELECT); 179 return readl(iosapic + IOSAPIC_REG_WINDOW); 180 } 181 182 static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val) 183 { 184 writel(reg, iosapic + IOSAPIC_REG_SELECT); 185 writel(val, iosapic + IOSAPIC_REG_WINDOW); 186 } 187 188 #define IOSAPIC_VERSION_MASK 0x000000ff 189 #define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK)) 190 191 #define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000 192 #define IOSAPIC_MAX_ENTRY_SHIFT 0x10 193 #define IOSAPIC_IRDT_MAX_ENTRY(ver) \ 194 (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT) 195 196 /* bits in the "low" I/O Sapic IRdT entry */ 197 #define IOSAPIC_IRDT_ENABLE 0x10000 198 #define IOSAPIC_IRDT_PO_LOW 0x02000 199 #define IOSAPIC_IRDT_LEVEL_TRIG 0x08000 200 #define IOSAPIC_IRDT_MODE_LPRI 0x00100 201 202 /* bits in the "high" I/O Sapic IRdT entry */ 203 #define IOSAPIC_IRDT_ID_EID_SHIFT 0x10 204 205 206 static DEFINE_SPINLOCK(iosapic_lock); 207 208 static inline void iosapic_eoi(void __iomem *addr, unsigned int data) 209 { 210 __raw_writel(data, addr); 211 } 212 213 /* 214 ** REVISIT: future platforms may have more than one IRT. 215 ** If so, the following three fields form a structure which 216 ** then be linked into a list. Names are chosen to make searching 217 ** for them easy - not necessarily accurate (eg "cell"). 218 ** 219 ** Alternative: iosapic_info could point to the IRT it's in. 220 ** iosapic_register() could search a list of IRT's. 221 */ 222 static struct irt_entry *irt_cell; 223 static size_t irt_num_entry; 224 225 static struct irt_entry *iosapic_alloc_irt(int num_entries) 226 { 227 unsigned long a; 228 229 /* The IRT needs to be 8-byte aligned for the PDC call. 230 * Normally kmalloc would guarantee larger alignment, but 231 * if CONFIG_DEBUG_SLAB is enabled, then we can get only 232 * 4-byte alignment on 32-bit kernels 233 */ 234 a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL); 235 a = (a + 7UL) & ~7UL; 236 return (struct irt_entry *)a; 237 } 238 239 /** 240 * iosapic_load_irt - Fill in the interrupt routing table 241 * @cell_num: The cell number of the CPU we're currently executing on 242 * @irt: The address to place the new IRT at 243 * @return The number of entries found 244 * 245 * The "Get PCI INT Routing Table Size" option returns the number of 246 * entries in the PCI interrupt routing table for the cell specified 247 * in the cell_number argument. The cell number must be for a cell 248 * within the caller's protection domain. 249 * 250 * The "Get PCI INT Routing Table" option returns, for the cell 251 * specified in the cell_number argument, the PCI interrupt routing 252 * table in the caller allocated memory pointed to by mem_addr. 253 * We assume the IRT only contains entries for I/O SAPIC and 254 * calculate the size based on the size of I/O sapic entries. 255 * 256 * The PCI interrupt routing table entry format is derived from the 257 * IA64 SAL Specification 2.4. The PCI interrupt routing table defines 258 * the routing of PCI interrupt signals between the PCI device output 259 * "pins" and the IO SAPICs' input "lines" (including core I/O PCI 260 * devices). This table does NOT include information for devices/slots 261 * behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec. 262 * for the architected method of routing of IRQ's behind PPB's. 263 */ 264 265 266 static int __init 267 iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt) 268 { 269 long status; /* PDC return value status */ 270 struct irt_entry *table; /* start of interrupt routing tbl */ 271 unsigned long num_entries = 0UL; 272 273 BUG_ON(!irt); 274 275 if (is_pdc_pat()) { 276 /* Use pat pdc routine to get interrupt routing table size */ 277 DBG("calling get_irt_size (cell %ld)\n", cell_num); 278 status = pdc_pat_get_irt_size(&num_entries, cell_num); 279 DBG("get_irt_size: %ld\n", status); 280 281 BUG_ON(status != PDC_OK); 282 BUG_ON(num_entries == 0); 283 284 /* 285 ** allocate memory for interrupt routing table 286 ** This interface isn't really right. We are assuming 287 ** the contents of the table are exclusively 288 ** for I/O sapic devices. 289 */ 290 table = iosapic_alloc_irt(num_entries); 291 if (table == NULL) { 292 printk(KERN_WARNING MODULE_NAME ": read_irt : can " 293 "not alloc mem for IRT\n"); 294 return 0; 295 } 296 297 /* get PCI INT routing table */ 298 status = pdc_pat_get_irt(table, cell_num); 299 DBG("pdc_pat_get_irt: %ld\n", status); 300 WARN_ON(status != PDC_OK); 301 } else { 302 /* 303 ** C3000/J5000 (and similar) platforms with Sprockets PDC 304 ** will return exactly one IRT for all iosapics. 305 ** So if we have one, don't need to get it again. 306 */ 307 if (irt_cell) 308 return 0; 309 310 /* Should be using the Elroy's HPA, but it's ignored anyway */ 311 status = pdc_pci_irt_size(&num_entries, 0); 312 DBG("pdc_pci_irt_size: %ld\n", status); 313 314 if (status != PDC_OK) { 315 /* Not a "legacy" system with I/O SAPIC either */ 316 return 0; 317 } 318 319 BUG_ON(num_entries == 0); 320 321 table = iosapic_alloc_irt(num_entries); 322 if (!table) { 323 printk(KERN_WARNING MODULE_NAME ": read_irt : can " 324 "not alloc mem for IRT\n"); 325 return 0; 326 } 327 328 /* HPA ignored by this call too. */ 329 status = pdc_pci_irt(num_entries, 0, table); 330 BUG_ON(status != PDC_OK); 331 } 332 333 /* return interrupt table address */ 334 *irt = table; 335 336 #ifdef DEBUG_IOSAPIC_IRT 337 { 338 struct irt_entry *p = table; 339 int i; 340 341 printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num); 342 printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n", 343 table, 344 num_entries, 345 (int) sizeof(struct irt_entry)); 346 347 for (i = 0 ; i < num_entries ; i++, p++) { 348 printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n", 349 p->entry_type, p->entry_length, p->interrupt_type, 350 p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id, 351 p->src_seg_id, p->dest_iosapic_intin, 352 ((u32 *) p)[2], 353 ((u32 *) p)[3] 354 ); 355 } 356 } 357 #endif /* DEBUG_IOSAPIC_IRT */ 358 359 return num_entries; 360 } 361 362 363 364 void __init iosapic_init(void) 365 { 366 unsigned long cell = 0; 367 368 DBG("iosapic_init()\n"); 369 370 #ifdef __LP64__ 371 if (is_pdc_pat()) { 372 int status; 373 struct pdc_pat_cell_num cell_info; 374 375 status = pdc_pat_cell_get_number(&cell_info); 376 if (status == PDC_OK) { 377 cell = cell_info.cell_num; 378 } 379 } 380 #endif 381 382 /* get interrupt routing table for this cell */ 383 irt_num_entry = iosapic_load_irt(cell, &irt_cell); 384 if (irt_num_entry == 0) 385 irt_cell = NULL; /* old PDC w/o iosapic */ 386 } 387 388 389 /* 390 ** Return the IRT entry in case we need to look something else up. 391 */ 392 static struct irt_entry * 393 irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin) 394 { 395 struct irt_entry *i = irt_cell; 396 int cnt; /* track how many entries we've looked at */ 397 u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1); 398 399 DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin); 400 401 for (cnt=0; cnt < irt_num_entry; cnt++, i++) { 402 403 /* 404 ** Validate: entry_type, entry_length, interrupt_type 405 ** 406 ** Difference between validate vs compare is the former 407 ** should print debug info and is not expected to "fail" 408 ** on current platforms. 409 */ 410 if (i->entry_type != IRT_IOSAPIC_TYPE) { 411 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type); 412 continue; 413 } 414 415 if (i->entry_length != IRT_IOSAPIC_LENGTH) { 416 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length); 417 continue; 418 } 419 420 if (i->interrupt_type != IRT_VECTORED_INTR) { 421 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type); 422 continue; 423 } 424 425 if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa)) 426 continue; 427 428 if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno) 429 continue; 430 431 /* 432 ** Ignore: src_bus_id and rc_seg_id correlate with 433 ** iosapic_info->isi_hpa on HP platforms. 434 ** If needed, pass in "PFA" (aka config space addr) 435 ** instead of slot. 436 */ 437 438 /* Found it! */ 439 return i; 440 } 441 442 printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n", 443 isi->isi_hpa, slot, intr_pin); 444 return NULL; 445 } 446 447 448 /* 449 ** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges. 450 ** Legacy PDC already does this translation for us and stores it in INTR_LINE. 451 ** 452 ** PAT PDC needs to basically do what legacy PDC does: 453 ** o read PIN 454 ** o adjust PIN in case device is "behind" a PPB 455 ** (eg 4-port 100BT and SCSI/LAN "Combo Card") 456 ** o convert slot/pin to I/O SAPIC input line. 457 ** 458 ** HP platforms only support: 459 ** o one level of skewing for any number of PPBs 460 ** o only support PCI-PCI Bridges. 461 */ 462 static struct irt_entry * 463 iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev) 464 { 465 u8 intr_pin, intr_slot; 466 467 pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin); 468 469 DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n", 470 pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin); 471 472 if (intr_pin == 0) { 473 /* The device does NOT support/use IRQ lines. */ 474 return NULL; 475 } 476 477 /* Check if pcidev behind a PPB */ 478 if (pcidev->bus->parent) { 479 /* Convert pcidev INTR_PIN into something we 480 ** can lookup in the IRT. 481 */ 482 #ifdef PCI_BRIDGE_FUNCS 483 /* 484 ** Proposal #1: 485 ** 486 ** call implementation specific translation function 487 ** This is architecturally "cleaner". HP-UX doesn't 488 ** support other secondary bus types (eg. E/ISA) directly. 489 ** May be needed for other processor (eg IA64) architectures 490 ** or by some ambitous soul who wants to watch TV. 491 */ 492 if (pci_bridge_funcs->xlate_intr_line) { 493 intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev); 494 } 495 #else /* PCI_BRIDGE_FUNCS */ 496 struct pci_bus *p = pcidev->bus; 497 /* 498 ** Proposal #2: 499 ** The "pin" is skewed ((pin + dev - 1) % 4). 500 ** 501 ** This isn't very clean since I/O SAPIC must assume: 502 ** - all platforms only have PCI busses. 503 ** - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA) 504 ** - IRQ routing is only skewed once regardless of 505 ** the number of PPB's between iosapic and device. 506 ** (Bit3 expansion chassis follows this rule) 507 ** 508 ** Advantage is it's really easy to implement. 509 */ 510 intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin); 511 #endif /* PCI_BRIDGE_FUNCS */ 512 513 /* 514 * Locate the host slot of the PPB. 515 */ 516 while (p->parent->parent) 517 p = p->parent; 518 519 intr_slot = PCI_SLOT(p->self->devfn); 520 } else { 521 intr_slot = PCI_SLOT(pcidev->devfn); 522 } 523 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n", 524 pcidev->bus->busn_res.start, intr_slot, intr_pin); 525 526 return irt_find_irqline(isi, intr_slot, intr_pin); 527 } 528 529 static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1) 530 { 531 struct iosapic_info *isp = vi->iosapic; 532 u8 idx = vi->irqline; 533 534 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx)); 535 *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx)); 536 } 537 538 539 static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1) 540 { 541 struct iosapic_info *isp = vi->iosapic; 542 543 DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n", 544 vi->irqline, isp->isi_hpa, dp0, dp1); 545 546 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0); 547 548 /* Read the window register to flush the writes down to HW */ 549 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW); 550 551 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1); 552 553 /* Read the window register to flush the writes down to HW */ 554 dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW); 555 } 556 557 /* 558 ** set_irt prepares the data (dp0, dp1) according to the vector_info 559 ** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC 560 ** IRdT for the given "vector" (aka IRQ line). 561 */ 562 static void 563 iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1) 564 { 565 u32 mode = 0; 566 struct irt_entry *p = vi->irte; 567 568 if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO) 569 mode |= IOSAPIC_IRDT_PO_LOW; 570 571 if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG) 572 mode |= IOSAPIC_IRDT_LEVEL_TRIG; 573 574 /* 575 ** IA64 REVISIT 576 ** PA doesn't support EXTINT or LPRIO bits. 577 */ 578 579 *dp0 = mode | (u32) vi->txn_data; 580 581 /* 582 ** Extracting id_eid isn't a real clean way of getting it. 583 ** But the encoding is the same for both PA and IA64 platforms. 584 */ 585 if (is_pdc_pat()) { 586 /* 587 ** PAT PDC just hands it to us "right". 588 ** txn_addr comes from cpu_data[x].txn_addr. 589 */ 590 *dp1 = (u32) (vi->txn_addr); 591 } else { 592 /* 593 ** eg if base_addr == 0xfffa0000), 594 ** we want to get 0xa0ff0000. 595 ** 596 ** eid 0x0ff00000 -> 0x00ff0000 597 ** id 0x000ff000 -> 0xff000000 598 */ 599 *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) | 600 (((u32)vi->txn_addr & 0x000ff000) << 12); 601 } 602 DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1); 603 } 604 605 606 static void iosapic_mask_irq(struct irq_data *d) 607 { 608 unsigned long flags; 609 struct vector_info *vi = irq_data_get_irq_chip_data(d); 610 u32 d0, d1; 611 612 spin_lock_irqsave(&iosapic_lock, flags); 613 iosapic_rd_irt_entry(vi, &d0, &d1); 614 d0 |= IOSAPIC_IRDT_ENABLE; 615 iosapic_wr_irt_entry(vi, d0, d1); 616 spin_unlock_irqrestore(&iosapic_lock, flags); 617 } 618 619 static void iosapic_unmask_irq(struct irq_data *d) 620 { 621 struct vector_info *vi = irq_data_get_irq_chip_data(d); 622 u32 d0, d1; 623 624 /* data is initialized by fixup_irq */ 625 WARN_ON(vi->txn_irq == 0); 626 627 iosapic_set_irt_data(vi, &d0, &d1); 628 iosapic_wr_irt_entry(vi, d0, d1); 629 630 #ifdef DEBUG_IOSAPIC_IRT 631 { 632 u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL); 633 printk("iosapic_enable_irq(): regs %p", vi->eoi_addr); 634 for ( ; t < vi->eoi_addr; t++) 635 printk(" %x", readl(t)); 636 printk("\n"); 637 } 638 639 printk("iosapic_enable_irq(): sel "); 640 { 641 struct iosapic_info *isp = vi->iosapic; 642 643 for (d0=0x10; d0<0x1e; d0++) { 644 d1 = iosapic_read(isp->addr, d0); 645 printk(" %x", d1); 646 } 647 } 648 printk("\n"); 649 #endif 650 651 /* 652 * Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is 653 * asserted. IRQ generally should not be asserted when a driver 654 * enables their IRQ. It can lead to "interesting" race conditions 655 * in the driver initialization sequence. 656 */ 657 DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", d->irq, 658 vi->eoi_addr, vi->eoi_data); 659 iosapic_eoi(vi->eoi_addr, vi->eoi_data); 660 } 661 662 static void iosapic_eoi_irq(struct irq_data *d) 663 { 664 struct vector_info *vi = irq_data_get_irq_chip_data(d); 665 666 iosapic_eoi(vi->eoi_addr, vi->eoi_data); 667 cpu_eoi_irq(d); 668 } 669 670 #ifdef CONFIG_SMP 671 static int iosapic_set_affinity_irq(struct irq_data *d, 672 const struct cpumask *dest, bool force) 673 { 674 struct vector_info *vi = irq_data_get_irq_chip_data(d); 675 u32 d0, d1, dummy_d0; 676 unsigned long flags; 677 int dest_cpu; 678 679 dest_cpu = cpu_check_affinity(d, dest); 680 if (dest_cpu < 0) 681 return -1; 682 683 cpumask_copy(irq_data_get_affinity_mask(d), cpumask_of(dest_cpu)); 684 vi->txn_addr = txn_affinity_addr(d->irq, dest_cpu); 685 686 spin_lock_irqsave(&iosapic_lock, flags); 687 /* d1 contains the destination CPU, so only want to set that 688 * entry */ 689 iosapic_rd_irt_entry(vi, &d0, &d1); 690 iosapic_set_irt_data(vi, &dummy_d0, &d1); 691 iosapic_wr_irt_entry(vi, d0, d1); 692 spin_unlock_irqrestore(&iosapic_lock, flags); 693 694 return 0; 695 } 696 #endif 697 698 static struct irq_chip iosapic_interrupt_type = { 699 .name = "IO-SAPIC-level", 700 .irq_unmask = iosapic_unmask_irq, 701 .irq_mask = iosapic_mask_irq, 702 .irq_ack = cpu_ack_irq, 703 .irq_eoi = iosapic_eoi_irq, 704 #ifdef CONFIG_SMP 705 .irq_set_affinity = iosapic_set_affinity_irq, 706 #endif 707 }; 708 709 int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev) 710 { 711 struct iosapic_info *isi = isi_obj; 712 struct irt_entry *irte = NULL; /* only used if PAT PDC */ 713 struct vector_info *vi; 714 int isi_line; /* line used by device */ 715 716 if (!isi) { 717 printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n", 718 pci_name(pcidev)); 719 return -1; 720 } 721 722 #ifdef CONFIG_SUPERIO 723 /* 724 * HACK ALERT! (non-compliant PCI device support) 725 * 726 * All SuckyIO interrupts are routed through the PIC's on function 1. 727 * But SuckyIO OHCI USB controller gets an IRT entry anyway because 728 * it advertises INT D for INT_PIN. Use that IRT entry to get the 729 * SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*). 730 */ 731 if (is_superio_device(pcidev)) { 732 /* We must call superio_fixup_irq() to register the pdev */ 733 pcidev->irq = superio_fixup_irq(pcidev); 734 735 /* Don't return if need to program the IOSAPIC's IRT... */ 736 if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN) 737 return pcidev->irq; 738 } 739 #endif /* CONFIG_SUPERIO */ 740 741 /* lookup IRT entry for isi/slot/pin set */ 742 irte = iosapic_xlate_pin(isi, pcidev); 743 if (!irte) { 744 printk("iosapic: no IRTE for %s (IRQ not connected?)\n", 745 pci_name(pcidev)); 746 return -1; 747 } 748 DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n", 749 irte, 750 irte->entry_type, 751 irte->entry_length, 752 irte->polarity_trigger, 753 irte->src_bus_irq_devno, 754 irte->src_bus_id, 755 irte->src_seg_id, 756 irte->dest_iosapic_intin, 757 (u32) irte->dest_iosapic_addr); 758 isi_line = irte->dest_iosapic_intin; 759 760 /* get vector info for this input line */ 761 vi = isi->isi_vector + isi_line; 762 DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi); 763 764 /* If this IRQ line has already been setup, skip it */ 765 if (vi->irte) 766 goto out; 767 768 vi->irte = irte; 769 770 /* 771 * Allocate processor IRQ 772 * 773 * XXX/FIXME The txn_alloc_irq() code and related code should be 774 * moved to enable_irq(). That way we only allocate processor IRQ 775 * bits for devices that actually have drivers claiming them. 776 * Right now we assign an IRQ to every PCI device present, 777 * regardless of whether it's used or not. 778 */ 779 vi->txn_irq = txn_alloc_irq(8); 780 781 if (vi->txn_irq < 0) 782 panic("I/O sapic: couldn't get TXN IRQ\n"); 783 784 /* enable_irq() will use txn_* to program IRdT */ 785 vi->txn_addr = txn_alloc_addr(vi->txn_irq); 786 vi->txn_data = txn_alloc_data(vi->txn_irq); 787 788 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI; 789 vi->eoi_data = cpu_to_le32(vi->txn_data); 790 791 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi); 792 793 out: 794 pcidev->irq = vi->txn_irq; 795 796 DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n", 797 PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn), 798 pcidev->vendor, pcidev->device, isi_line, pcidev->irq); 799 800 return pcidev->irq; 801 } 802 803 static struct iosapic_info *iosapic_list; 804 805 #ifdef CONFIG_64BIT 806 int iosapic_serial_irq(struct parisc_device *dev) 807 { 808 struct iosapic_info *isi; 809 struct irt_entry *irte; 810 struct vector_info *vi; 811 int cnt; 812 int intin; 813 814 intin = (dev->mod_info >> 24) & 15; 815 816 /* lookup IRT entry for isi/slot/pin set */ 817 for (cnt = 0; cnt < irt_num_entry; cnt++) { 818 irte = &irt_cell[cnt]; 819 if (COMPARE_IRTE_ADDR(irte, dev->mod0) && 820 irte->dest_iosapic_intin == intin) 821 break; 822 } 823 if (cnt >= irt_num_entry) 824 return 0; /* no irq found, force polling */ 825 826 DBG_IRT("iosapic_serial_irq(): irte %p %x %x %x %x %x %x %x %x\n", 827 irte, 828 irte->entry_type, 829 irte->entry_length, 830 irte->polarity_trigger, 831 irte->src_bus_irq_devno, 832 irte->src_bus_id, 833 irte->src_seg_id, 834 irte->dest_iosapic_intin, 835 (u32) irte->dest_iosapic_addr); 836 837 /* search for iosapic */ 838 for (isi = iosapic_list; isi; isi = isi->isi_next) 839 if (isi->isi_hpa == dev->mod0) 840 break; 841 if (!isi) 842 return 0; /* no iosapic found, force polling */ 843 844 /* get vector info for this input line */ 845 vi = isi->isi_vector + intin; 846 DBG_IRT("iosapic_serial_irq: line %d vi 0x%p\n", iosapic_intin, vi); 847 848 /* If this IRQ line has already been setup, skip it */ 849 if (vi->irte) 850 goto out; 851 852 vi->irte = irte; 853 854 /* 855 * Allocate processor IRQ 856 * 857 * XXX/FIXME The txn_alloc_irq() code and related code should be 858 * moved to enable_irq(). That way we only allocate processor IRQ 859 * bits for devices that actually have drivers claiming them. 860 * Right now we assign an IRQ to every PCI device present, 861 * regardless of whether it's used or not. 862 */ 863 vi->txn_irq = txn_alloc_irq(8); 864 865 if (vi->txn_irq < 0) 866 panic("I/O sapic: couldn't get TXN IRQ\n"); 867 868 /* enable_irq() will use txn_* to program IRdT */ 869 vi->txn_addr = txn_alloc_addr(vi->txn_irq); 870 vi->txn_data = txn_alloc_data(vi->txn_irq); 871 872 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI; 873 vi->eoi_data = cpu_to_le32(vi->txn_data); 874 875 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi); 876 877 out: 878 879 return vi->txn_irq; 880 } 881 #endif 882 883 884 /* 885 ** squirrel away the I/O Sapic Version 886 */ 887 static unsigned int 888 iosapic_rd_version(struct iosapic_info *isi) 889 { 890 return iosapic_read(isi->addr, IOSAPIC_REG_VERSION); 891 } 892 893 894 /* 895 ** iosapic_register() is called by "drivers" with an integrated I/O SAPIC. 896 ** Caller must be certain they have an I/O SAPIC and know its MMIO address. 897 ** 898 ** o allocate iosapic_info and add it to the list 899 ** o read iosapic version and squirrel that away 900 ** o read size of IRdT. 901 ** o allocate and initialize isi_vector[] 902 ** o allocate irq region 903 */ 904 void *iosapic_register(unsigned long hpa) 905 { 906 struct iosapic_info *isi = NULL; 907 struct irt_entry *irte = irt_cell; 908 struct vector_info *vip; 909 int cnt; /* track how many entries we've looked at */ 910 911 /* 912 * Astro based platforms can only support PCI OLARD if they implement 913 * PAT PDC. Legacy PDC omits LBAs with no PCI devices from the IRT. 914 * Search the IRT and ignore iosapic's which aren't in the IRT. 915 */ 916 for (cnt=0; cnt < irt_num_entry; cnt++, irte++) { 917 WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type); 918 if (COMPARE_IRTE_ADDR(irte, hpa)) 919 break; 920 } 921 922 if (cnt >= irt_num_entry) { 923 DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa); 924 return NULL; 925 } 926 927 isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL); 928 if (!isi) { 929 BUG(); 930 return NULL; 931 } 932 933 isi->addr = ioremap_nocache(hpa, 4096); 934 isi->isi_hpa = hpa; 935 isi->isi_version = iosapic_rd_version(isi); 936 isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1; 937 938 vip = isi->isi_vector = kcalloc(isi->isi_num_vectors, 939 sizeof(struct vector_info), GFP_KERNEL); 940 if (vip == NULL) { 941 kfree(isi); 942 return NULL; 943 } 944 945 for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) { 946 vip->irqline = (unsigned char) cnt; 947 vip->iosapic = isi; 948 } 949 isi->isi_next = iosapic_list; 950 iosapic_list = isi; 951 return isi; 952 } 953 954 955 #ifdef DEBUG_IOSAPIC 956 957 static void 958 iosapic_prt_irt(void *irt, long num_entry) 959 { 960 unsigned int i, *irp = (unsigned int *) irt; 961 962 963 printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry); 964 965 for (i=0; i<num_entry; i++, irp += 4) { 966 printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n", 967 irp, i, irp[0], irp[1], irp[2], irp[3]); 968 } 969 } 970 971 972 static void 973 iosapic_prt_vi(struct vector_info *vi) 974 { 975 printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi); 976 printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status); 977 printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq); 978 printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr); 979 printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data); 980 printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr); 981 printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data); 982 } 983 984 985 static void 986 iosapic_prt_isi(struct iosapic_info *isi) 987 { 988 printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi); 989 printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa); 990 printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status); 991 printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version); 992 printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector); 993 } 994 #endif /* DEBUG_IOSAPIC */ 995