1 /* 2 ** DINO manager 3 ** 4 ** (c) Copyright 1999 Red Hat Software 5 ** (c) Copyright 1999 SuSE GmbH 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** (c) Copyright 2000 Grant Grundler 8 ** (c) Copyright 2006 Helge Deller 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** This module provides access to Dino PCI bus (config/IOport spaces) 16 ** and helps manage Dino IRQ lines. 17 ** 18 ** Dino interrupt handling is a bit complicated. 19 ** Dino always writes to the broadcast EIR via irr0 for now. 20 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) 21 ** Only one processor interrupt is used for the 11 IRQ line 22 ** inputs to dino. 23 ** 24 ** The different between Built-in Dino and Card-Mode 25 ** dino is in chip initialization and pci device initialization. 26 ** 27 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port 28 ** BARs are configured and used by the driver. Programming MMIO address 29 ** requires substantial knowledge of available Host I/O address ranges 30 ** is currently not supported. Port/Config accessor functions are the 31 ** same. "BIOS" differences are handled within the existing routines. 32 */ 33 34 /* Changes : 35 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) 36 ** - added support for the integrated RS232. 37 */ 38 39 /* 40 ** TODO: create a virtual address for each Dino HPA. 41 ** GSC code might be able to do this since IODC data tells us 42 ** how many pages are used. PCI subsystem could (must?) do this 43 ** for PCI drivers devices which implement/use MMIO registers. 44 */ 45 46 #include <linux/delay.h> 47 #include <linux/types.h> 48 #include <linux/kernel.h> 49 #include <linux/pci.h> 50 #include <linux/init.h> 51 #include <linux/ioport.h> 52 #include <linux/slab.h> 53 #include <linux/interrupt.h> /* for struct irqaction */ 54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */ 55 56 #include <asm/pdc.h> 57 #include <asm/page.h> 58 #include <asm/io.h> 59 #include <asm/hardware.h> 60 61 #include "gsc.h" 62 63 #undef DINO_DEBUG 64 65 #ifdef DINO_DEBUG 66 #define DBG(x...) printk(x) 67 #else 68 #define DBG(x...) 69 #endif 70 71 /* 72 ** Config accessor functions only pass in the 8-bit bus number 73 ** and not the 8-bit "PCI Segment" number. Each Dino will be 74 ** assigned a PCI bus number based on "when" it's discovered. 75 ** 76 ** The "secondary" bus number is set to this before calling 77 ** pci_scan_bus(). If any PPB's are present, the scan will 78 ** discover them and update the "secondary" and "subordinate" 79 ** fields in Dino's pci_bus structure. 80 ** 81 ** Changes in the configuration *will* result in a different 82 ** bus number for each dino. 83 */ 84 85 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) 86 #define is_cujo(id) ((id)->hversion == 0x682) 87 88 #define DINO_IAR0 0x004 89 #define DINO_IODC_ADDR 0x008 90 #define DINO_IODC_DATA_0 0x008 91 #define DINO_IODC_DATA_1 0x008 92 #define DINO_IRR0 0x00C 93 #define DINO_IAR1 0x010 94 #define DINO_IRR1 0x014 95 #define DINO_IMR 0x018 96 #define DINO_IPR 0x01C 97 #define DINO_TOC_ADDR 0x020 98 #define DINO_ICR 0x024 99 #define DINO_ILR 0x028 100 #define DINO_IO_COMMAND 0x030 101 #define DINO_IO_STATUS 0x034 102 #define DINO_IO_CONTROL 0x038 103 #define DINO_IO_GSC_ERR_RESP 0x040 104 #define DINO_IO_ERR_INFO 0x044 105 #define DINO_IO_PCI_ERR_RESP 0x048 106 #define DINO_IO_FBB_EN 0x05c 107 #define DINO_IO_ADDR_EN 0x060 108 #define DINO_PCI_ADDR 0x064 109 #define DINO_CONFIG_DATA 0x068 110 #define DINO_IO_DATA 0x06c 111 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */ 112 #define DINO_GSC2X_CONFIG 0x7b4 113 #define DINO_GMASK 0x800 114 #define DINO_PAMR 0x804 115 #define DINO_PAPR 0x808 116 #define DINO_DAMODE 0x80c 117 #define DINO_PCICMD 0x810 118 #define DINO_PCISTS 0x814 119 #define DINO_MLTIM 0x81c 120 #define DINO_BRDG_FEAT 0x820 121 #define DINO_PCIROR 0x824 122 #define DINO_PCIWOR 0x828 123 #define DINO_TLTIM 0x830 124 125 #define DINO_IRQS 11 /* bits 0-10 are architected */ 126 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 127 #define DINO_LOCAL_IRQS (DINO_IRQS+1) 128 129 #define DINO_MASK_IRQ(x) (1<<(x)) 130 131 #define PCIINTA 0x001 132 #define PCIINTB 0x002 133 #define PCIINTC 0x004 134 #define PCIINTD 0x008 135 #define PCIINTE 0x010 136 #define PCIINTF 0x020 137 #define GSCEXTINT 0x040 138 /* #define xxx 0x080 - bit 7 is "default" */ 139 /* #define xxx 0x100 - bit 8 not used */ 140 /* #define xxx 0x200 - bit 9 not used */ 141 #define RS232INT 0x400 142 143 struct dino_device 144 { 145 struct pci_hba_data hba; /* 'C' inheritance - must be first */ 146 spinlock_t dinosaur_pen; 147 unsigned long txn_addr; /* EIR addr to generate interrupt */ 148 u32 txn_data; /* EIR data assign to each dino */ 149 u32 imr; /* IRQ's which are enabled */ 150 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ 151 #ifdef DINO_DEBUG 152 unsigned int dino_irr0; /* save most recent IRQ line stat */ 153 #endif 154 }; 155 156 /* Looks nice and keeps the compiler happy */ 157 #define DINO_DEV(d) ({ \ 158 void *__pdata = d; \ 159 BUG_ON(!__pdata); \ 160 (struct dino_device *)__pdata; }) 161 162 163 /* 164 * Dino Configuration Space Accessor Functions 165 */ 166 167 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) 168 169 /* 170 * keep the current highest bus count to assist in allocating busses. This 171 * tries to keep a global bus count total so that when we discover an 172 * entirely new bus, it can be given a unique bus number. 173 */ 174 static int dino_current_bus = 0; 175 176 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, 177 int size, u32 *val) 178 { 179 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 180 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; 181 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 182 void __iomem *base_addr = d->hba.base_addr; 183 unsigned long flags; 184 185 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, 186 size); 187 spin_lock_irqsave(&d->dinosaur_pen, flags); 188 189 /* tell HW which CFG address */ 190 __raw_writel(v, base_addr + DINO_PCI_ADDR); 191 192 /* generate cfg read cycle */ 193 if (size == 1) { 194 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); 195 } else if (size == 2) { 196 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); 197 } else if (size == 4) { 198 *val = readl(base_addr + DINO_CONFIG_DATA); 199 } 200 201 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 202 return 0; 203 } 204 205 /* 206 * Dino address stepping "feature": 207 * When address stepping, Dino attempts to drive the bus one cycle too soon 208 * even though the type of cycle (config vs. MMIO) might be different. 209 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. 210 */ 211 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, 212 int size, u32 val) 213 { 214 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 215 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start; 216 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 217 void __iomem *base_addr = d->hba.base_addr; 218 unsigned long flags; 219 220 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, 221 size); 222 spin_lock_irqsave(&d->dinosaur_pen, flags); 223 224 /* avoid address stepping feature */ 225 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); 226 __raw_readl(base_addr + DINO_CONFIG_DATA); 227 228 /* tell HW which CFG address */ 229 __raw_writel(v, base_addr + DINO_PCI_ADDR); 230 /* generate cfg read cycle */ 231 if (size == 1) { 232 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); 233 } else if (size == 2) { 234 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); 235 } else if (size == 4) { 236 writel(val, base_addr + DINO_CONFIG_DATA); 237 } 238 239 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 240 return 0; 241 } 242 243 static struct pci_ops dino_cfg_ops = { 244 .read = dino_cfg_read, 245 .write = dino_cfg_write, 246 }; 247 248 249 /* 250 * Dino "I/O Port" Space Accessor Functions 251 * 252 * Many PCI devices don't require use of I/O port space (eg Tulip, 253 * NCR720) since they export the same registers to both MMIO and 254 * I/O port space. Performance is going to stink if drivers use 255 * I/O port instead of MMIO. 256 */ 257 258 #define DINO_PORT_IN(type, size, mask) \ 259 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ 260 { \ 261 u##size v; \ 262 unsigned long flags; \ 263 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 264 /* tell HW which IO Port address */ \ 265 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 266 /* generate I/O PORT read cycle */ \ 267 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ 268 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 269 return v; \ 270 } 271 272 DINO_PORT_IN(b, 8, 3) 273 DINO_PORT_IN(w, 16, 2) 274 DINO_PORT_IN(l, 32, 0) 275 276 #define DINO_PORT_OUT(type, size, mask) \ 277 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 278 { \ 279 unsigned long flags; \ 280 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 281 /* tell HW which IO port address */ \ 282 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 283 /* generate cfg write cycle */ \ 284 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ 285 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 286 } 287 288 DINO_PORT_OUT(b, 8, 3) 289 DINO_PORT_OUT(w, 16, 2) 290 DINO_PORT_OUT(l, 32, 0) 291 292 static struct pci_port_ops dino_port_ops = { 293 .inb = dino_in8, 294 .inw = dino_in16, 295 .inl = dino_in32, 296 .outb = dino_out8, 297 .outw = dino_out16, 298 .outl = dino_out32 299 }; 300 301 static void dino_mask_irq(struct irq_data *d) 302 { 303 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); 304 int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 305 306 DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq); 307 308 /* Clear the matching bit in the IMR register */ 309 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); 310 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 311 } 312 313 static void dino_unmask_irq(struct irq_data *d) 314 { 315 struct dino_device *dino_dev = irq_data_get_irq_chip_data(d); 316 int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 317 u32 tmp; 318 319 DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq); 320 321 /* 322 ** clear pending IRQ bits 323 ** 324 ** This does NOT change ILR state! 325 ** See comment below for ILR usage. 326 */ 327 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); 328 329 /* set the matching bit in the IMR register */ 330 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ 331 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 332 333 /* Emulate "Level Triggered" Interrupt 334 ** Basically, a driver is blowing it if the IRQ line is asserted 335 ** while the IRQ is disabled. But tulip.c seems to do that.... 336 ** Give 'em a kluge award and a nice round of applause! 337 ** 338 ** The gsc_write will generate an interrupt which invokes dino_isr(). 339 ** dino_isr() will read IPR and find nothing. But then catch this 340 ** when it also checks ILR. 341 */ 342 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); 343 if (tmp & DINO_MASK_IRQ(local_irq)) { 344 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", 345 __func__, tmp); 346 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); 347 } 348 } 349 350 static struct irq_chip dino_interrupt_type = { 351 .name = "GSC-PCI", 352 .irq_unmask = dino_unmask_irq, 353 .irq_mask = dino_mask_irq, 354 }; 355 356 357 /* 358 * Handle a Processor interrupt generated by Dino. 359 * 360 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from 361 * wedging the CPU. Could be removed or made optional at some point. 362 */ 363 static irqreturn_t dino_isr(int irq, void *intr_dev) 364 { 365 struct dino_device *dino_dev = intr_dev; 366 u32 mask; 367 int ilr_loop = 100; 368 369 /* read and acknowledge pending interrupts */ 370 #ifdef DINO_DEBUG 371 dino_dev->dino_irr0 = 372 #endif 373 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; 374 375 if (mask == 0) 376 return IRQ_NONE; 377 378 ilr_again: 379 do { 380 int local_irq = __ffs(mask); 381 int irq = dino_dev->global_irq[local_irq]; 382 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", 383 __func__, irq, intr_dev, mask); 384 generic_handle_irq(irq); 385 mask &= ~DINO_MASK_IRQ(local_irq); 386 } while (mask); 387 388 /* Support for level triggered IRQ lines. 389 ** 390 ** Dropping this support would make this routine *much* faster. 391 ** But since PCI requires level triggered IRQ line to share lines... 392 ** device drivers may assume lines are level triggered (and not 393 ** edge triggered like EISA/ISA can be). 394 */ 395 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; 396 if (mask) { 397 if (--ilr_loop > 0) 398 goto ilr_again; 399 pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n", 400 dino_dev->hba.base_addr, mask); 401 } 402 return IRQ_HANDLED; 403 } 404 405 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) 406 { 407 int irq = gsc_assign_irq(&dino_interrupt_type, dino); 408 if (irq == NO_IRQ) 409 return; 410 411 *irqp = irq; 412 dino->global_irq[local_irq] = irq; 413 } 414 415 static void dino_choose_irq(struct parisc_device *dev, void *ctrl) 416 { 417 int irq; 418 struct dino_device *dino = ctrl; 419 420 switch (dev->id.sversion) { 421 case 0x00084: irq = 8; break; /* PS/2 */ 422 case 0x0008c: irq = 10; break; /* RS232 */ 423 case 0x00096: irq = 8; break; /* PS/2 */ 424 default: return; /* Unknown */ 425 } 426 427 dino_assign_irq(dino, irq, &dev->irq); 428 } 429 430 431 /* 432 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de) 433 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) 434 */ 435 static void quirk_cirrus_cardbus(struct pci_dev *dev) 436 { 437 u8 new_irq = dev->irq - 1; 438 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n", 439 pci_name(dev), dev->irq, new_irq); 440 dev->irq = new_irq; 441 } 442 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); 443 444 445 static void __init 446 dino_bios_init(void) 447 { 448 DBG("dino_bios_init\n"); 449 } 450 451 /* 452 * dino_card_setup - Set up the memory space for a Dino in card mode. 453 * @bus: the bus under this dino 454 * 455 * Claim an 8MB chunk of unused IO space and call the generic PCI routines 456 * to set up the addresses of the devices on this bus. 457 */ 458 #define _8MB 0x00800000UL 459 static void __init 460 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) 461 { 462 int i; 463 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 464 struct resource *res; 465 char name[128]; 466 int size; 467 468 res = &dino_dev->hba.lmmio_space; 469 res->flags = IORESOURCE_MEM; 470 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 471 dev_name(bus->bridge)); 472 res->name = kmalloc(size+1, GFP_KERNEL); 473 if(res->name) 474 strcpy((char *)res->name, name); 475 else 476 res->name = dino_dev->hba.lmmio_space.name; 477 478 479 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, 480 F_EXTEND(0xf0000000UL) | _8MB, 481 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { 482 struct pci_dev *dev, *tmp; 483 484 printk(KERN_ERR "Dino: cannot attach bus %s\n", 485 dev_name(bus->bridge)); 486 /* kill the bus, we can't do anything with it */ 487 list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) { 488 list_del(&dev->bus_list); 489 } 490 491 return; 492 } 493 bus->resource[1] = res; 494 bus->resource[0] = &(dino_dev->hba.io_space); 495 496 /* Now tell dino what range it has */ 497 for (i = 1; i < 31; i++) { 498 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) 499 break; 500 } 501 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n", 502 i, res->start, base_addr + DINO_IO_ADDR_EN); 503 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); 504 } 505 506 static void __init 507 dino_card_fixup(struct pci_dev *dev) 508 { 509 u32 irq_pin; 510 511 /* 512 ** REVISIT: card-mode PCI-PCI expansion chassis do exist. 513 ** Not sure they were ever productized. 514 ** Die here since we'll die later in dino_inb() anyway. 515 */ 516 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 517 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); 518 } 519 520 /* 521 ** Set Latency Timer to 0xff (not a shared bus) 522 ** Set CACHELINE_SIZE. 523 */ 524 dino_cfg_write(dev->bus, dev->devfn, 525 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 526 527 /* 528 ** Program INT_LINE for card-mode devices. 529 ** The cards are hardwired according to this algorithm. 530 ** And it doesn't matter if PPB's are present or not since 531 ** the IRQ lines bypass the PPB. 532 ** 533 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. 534 ** The additional "-1" adjusts for skewing the IRQ<->slot. 535 */ 536 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 537 dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1; 538 539 /* Shouldn't really need to do this but it's in case someone tries 540 ** to bypass PCI services and look at the card themselves. 541 */ 542 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 543 } 544 545 /* The alignment contraints for PCI bridges under dino */ 546 #define DINO_BRIDGE_ALIGN 0x100000 547 548 549 static void __init 550 dino_fixup_bus(struct pci_bus *bus) 551 { 552 struct pci_dev *dev; 553 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 554 555 DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n", 556 __func__, bus, bus->busn_res.start, 557 bus->bridge->platform_data); 558 559 /* Firmware doesn't set up card-mode dino, so we have to */ 560 if (is_card_dino(&dino_dev->hba.dev->id)) { 561 dino_card_setup(bus, dino_dev->hba.base_addr); 562 } else if (bus->parent) { 563 int i; 564 565 pci_read_bridge_bases(bus); 566 567 568 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 569 if((bus->self->resource[i].flags & 570 (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 571 continue; 572 573 if(bus->self->resource[i].flags & IORESOURCE_MEM) { 574 /* There's a quirk to alignment of 575 * bridge memory resources: the start 576 * is the alignment and start-end is 577 * the size. However, firmware will 578 * have assigned start and end, so we 579 * need to take this into account */ 580 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; 581 bus->self->resource[i].start = DINO_BRIDGE_ALIGN; 582 583 } 584 585 DBG("DEBUG %s assigning %d [%pR]\n", 586 dev_name(&bus->self->dev), i, 587 &bus->self->resource[i]); 588 WARN_ON(pci_assign_resource(bus->self, i)); 589 DBG("DEBUG %s after assign %d [%pR]\n", 590 dev_name(&bus->self->dev), i, 591 &bus->self->resource[i]); 592 } 593 } 594 595 596 list_for_each_entry(dev, &bus->devices, bus_list) { 597 if (is_card_dino(&dino_dev->hba.dev->id)) 598 dino_card_fixup(dev); 599 600 /* 601 ** P2PB's only have 2 BARs, no IRQs. 602 ** I'd like to just ignore them for now. 603 */ 604 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 605 pcibios_init_bridge(dev); 606 continue; 607 } 608 609 /* null out the ROM resource if there is one (we don't 610 * care about an expansion rom on parisc, since it 611 * usually contains (x86) bios code) */ 612 dev->resource[PCI_ROM_RESOURCE].flags = 0; 613 614 if(dev->irq == 255) { 615 616 #define DINO_FIX_UNASSIGNED_INTERRUPTS 617 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS 618 619 /* This code tries to assign an unassigned 620 * interrupt. Leave it disabled unless you 621 * *really* know what you're doing since the 622 * pin<->interrupt line mapping varies by bus 623 * and machine */ 624 625 u32 irq_pin; 626 627 dino_cfg_read(dev->bus, dev->devfn, 628 PCI_INTERRUPT_PIN, 1, &irq_pin); 629 irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1; 630 printk(KERN_WARNING "Device %s has undefined IRQ, " 631 "setting to %d\n", pci_name(dev), irq_pin); 632 dino_cfg_write(dev->bus, dev->devfn, 633 PCI_INTERRUPT_LINE, 1, irq_pin); 634 dino_assign_irq(dino_dev, irq_pin, &dev->irq); 635 #else 636 dev->irq = 65535; 637 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); 638 #endif 639 } else { 640 /* Adjust INT_LINE for that busses region */ 641 dino_assign_irq(dino_dev, dev->irq, &dev->irq); 642 } 643 } 644 } 645 646 647 static struct pci_bios_ops dino_bios_ops = { 648 .init = dino_bios_init, 649 .fixup_bus = dino_fixup_bus 650 }; 651 652 653 /* 654 * Initialise a DINO controller chip 655 */ 656 static void __init 657 dino_card_init(struct dino_device *dino_dev) 658 { 659 u32 brdg_feat = 0x00784e05; 660 unsigned long status; 661 662 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); 663 if (status & 0x0000ff80) { 664 __raw_writel(0x00000005, 665 dino_dev->hba.base_addr+DINO_IO_COMMAND); 666 udelay(1); 667 } 668 669 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); 670 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); 671 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); 672 673 #if 1 674 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ 675 /* 676 ** PCX-L processors don't support XQL like Dino wants it. 677 ** PCX-L2 ignore XQL signal and it doesn't matter. 678 */ 679 brdg_feat &= ~0x4; /* UXQL */ 680 #endif 681 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); 682 683 /* 684 ** Don't enable address decoding until we know which I/O range 685 ** currently is available from the host. Only affects MMIO 686 ** and not I/O port space. 687 */ 688 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); 689 690 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); 691 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); 692 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); 693 694 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); 695 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); 696 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); 697 698 /* Disable PAMR before writing PAPR */ 699 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); 700 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); 701 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); 702 703 /* 704 ** Dino ERS encourages enabling FBB (0x6f). 705 ** We can't until we know *all* devices below us can support it. 706 ** (Something in device configuration header tells us). 707 */ 708 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); 709 710 /* Somewhere, the PCI spec says give devices 1 second 711 ** to recover from the #RESET being de-asserted. 712 ** Experience shows most devices only need 10ms. 713 ** This short-cut speeds up booting significantly. 714 */ 715 mdelay(pci_post_reset_delay); 716 } 717 718 static int __init 719 dino_bridge_init(struct dino_device *dino_dev, const char *name) 720 { 721 unsigned long io_addr; 722 int result, i, count=0; 723 struct resource *res, *prevres = NULL; 724 /* 725 * Decoding IO_ADDR_EN only works for Built-in Dino 726 * since PDC has already initialized this. 727 */ 728 729 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); 730 if (io_addr == 0) { 731 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); 732 return -ENODEV; 733 } 734 735 res = &dino_dev->hba.lmmio_space; 736 for (i = 0; i < 32; i++) { 737 unsigned long start, end; 738 739 if((io_addr & (1 << i)) == 0) 740 continue; 741 742 start = F_EXTEND(0xf0000000UL) | (i << 23); 743 end = start + 8 * 1024 * 1024 - 1; 744 745 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, 746 start, end); 747 748 if(prevres && prevres->end + 1 == start) { 749 prevres->end = end; 750 } else { 751 if(count >= DINO_MAX_LMMIO_RESOURCES) { 752 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); 753 break; 754 } 755 prevres = res; 756 res->start = start; 757 res->end = end; 758 res->flags = IORESOURCE_MEM; 759 res->name = kmalloc(64, GFP_KERNEL); 760 if(res->name) 761 snprintf((char *)res->name, 64, "%s LMMIO %d", 762 name, count); 763 res++; 764 count++; 765 } 766 } 767 768 res = &dino_dev->hba.lmmio_space; 769 770 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 771 if(res[i].flags == 0) 772 break; 773 774 result = ccio_request_resource(dino_dev->hba.dev, &res[i]); 775 if (result < 0) { 776 printk(KERN_ERR "%s: failed to claim PCI Bus address " 777 "space %d (%pR)!\n", name, i, &res[i]); 778 return result; 779 } 780 } 781 return 0; 782 } 783 784 static int __init dino_common_init(struct parisc_device *dev, 785 struct dino_device *dino_dev, const char *name) 786 { 787 int status; 788 u32 eim; 789 struct gsc_irq gsc_irq; 790 struct resource *res; 791 792 pcibios_register_hba(&dino_dev->hba); 793 794 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ 795 pci_port = &dino_port_ops; 796 797 /* 798 ** Note: SMP systems can make use of IRR1/IAR1 registers 799 ** But it won't buy much performance except in very 800 ** specific applications/configurations. Note Dino 801 ** still only has 11 IRQ input lines - just map some of them 802 ** to a different processor. 803 */ 804 dev->irq = gsc_alloc_irq(&gsc_irq); 805 dino_dev->txn_addr = gsc_irq.txn_addr; 806 dino_dev->txn_data = gsc_irq.txn_data; 807 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; 808 809 /* 810 ** Dino needs a PA "IRQ" to get a processor's attention. 811 ** arch/parisc/kernel/irq.c returns an EIRR bit. 812 */ 813 if (dev->irq < 0) { 814 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); 815 return 1; 816 } 817 818 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); 819 if (status) { 820 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 821 name, status); 822 return 1; 823 } 824 825 /* Support the serial port which is sometimes attached on built-in 826 * Dino / Cujo chips. 827 */ 828 829 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); 830 831 /* 832 ** This enables DINO to generate interrupts when it sees 833 ** any of its inputs *change*. Just asserting an IRQ 834 ** before it's enabled (ie unmasked) isn't good enough. 835 */ 836 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); 837 838 /* 839 ** Some platforms don't clear Dino's IRR0 register at boot time. 840 ** Reading will clear it now. 841 */ 842 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); 843 844 /* allocate I/O Port resource region */ 845 res = &dino_dev->hba.io_space; 846 if (!is_cujo(&dev->id)) { 847 res->name = "Dino I/O Port"; 848 } else { 849 res->name = "Cujo I/O Port"; 850 } 851 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); 852 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); 853 res->flags = IORESOURCE_IO; /* do not mark it busy ! */ 854 if (request_resource(&ioport_resource, res) < 0) { 855 printk(KERN_ERR "%s: request I/O Port region failed " 856 "0x%lx/%lx (hpa 0x%px)\n", 857 name, (unsigned long)res->start, (unsigned long)res->end, 858 dino_dev->hba.base_addr); 859 return 1; 860 } 861 862 return 0; 863 } 864 865 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) 866 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) 867 #define CUJO_RAVEN_BADPAGE 0x01003000UL 868 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL 869 870 static const char *dino_vers[] = { 871 "2.0", 872 "2.1", 873 "3.0", 874 "3.1" 875 }; 876 877 static const char *cujo_vers[] = { 878 "1.0", 879 "2.0" 880 }; 881 882 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); 883 884 /* 885 ** Determine if dino should claim this chip (return 0) or not (return 1). 886 ** If so, initialize the chip appropriately (card-mode vs bridge mode). 887 ** Much of the initialization is common though. 888 */ 889 static int __init dino_probe(struct parisc_device *dev) 890 { 891 struct dino_device *dino_dev; // Dino specific control struct 892 const char *version = "unknown"; 893 char *name; 894 int is_cujo = 0; 895 LIST_HEAD(resources); 896 struct pci_bus *bus; 897 unsigned long hpa = dev->hpa.start; 898 int max; 899 900 name = "Dino"; 901 if (is_card_dino(&dev->id)) { 902 version = "3.x (card mode)"; 903 } else { 904 if (!is_cujo(&dev->id)) { 905 if (dev->id.hversion_rev < 4) { 906 version = dino_vers[dev->id.hversion_rev]; 907 } 908 } else { 909 name = "Cujo"; 910 is_cujo = 1; 911 if (dev->id.hversion_rev < 2) { 912 version = cujo_vers[dev->id.hversion_rev]; 913 } 914 } 915 } 916 917 printk("%s version %s found at 0x%lx\n", name, version, hpa); 918 919 if (!request_mem_region(hpa, PAGE_SIZE, name)) { 920 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n", 921 hpa); 922 return 1; 923 } 924 925 /* Check for bugs */ 926 if (is_cujo && dev->id.hversion_rev == 1) { 927 #ifdef CONFIG_IOMMU_CCIO 928 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); 929 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { 930 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); 931 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { 932 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); 933 } else { 934 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa); 935 } 936 #endif 937 } else if (!is_cujo && !is_card_dino(&dev->id) && 938 dev->id.hversion_rev < 3) { 939 printk(KERN_WARNING 940 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" 941 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" 942 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" 943 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", 944 dev->id.hversion_rev); 945 /* REVISIT: why are C200/C240 listed in the README table but not 946 ** "Models affected"? Could be an omission in the original literature. 947 */ 948 } 949 950 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL); 951 if (!dino_dev) { 952 printk("dino_init_chip - couldn't alloc dino_device\n"); 953 return 1; 954 } 955 956 dino_dev->hba.dev = dev; 957 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096); 958 dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND; 959 spin_lock_init(&dino_dev->dinosaur_pen); 960 dino_dev->hba.iommu = ccio_get_iommu(dev); 961 962 if (is_card_dino(&dev->id)) { 963 dino_card_init(dino_dev); 964 } else { 965 dino_bridge_init(dino_dev, name); 966 } 967 968 if (dino_common_init(dev, dino_dev, name)) 969 return 1; 970 971 dev->dev.platform_data = dino_dev; 972 973 pci_add_resource_offset(&resources, &dino_dev->hba.io_space, 974 HBA_PORT_BASE(dino_dev->hba.hba_num)); 975 if (dino_dev->hba.lmmio_space.flags) 976 pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space, 977 dino_dev->hba.lmmio_space_offset); 978 if (dino_dev->hba.elmmio_space.flags) 979 pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space, 980 dino_dev->hba.lmmio_space_offset); 981 if (dino_dev->hba.gmmio_space.flags) 982 pci_add_resource(&resources, &dino_dev->hba.gmmio_space); 983 984 dino_dev->hba.bus_num.start = dino_current_bus; 985 dino_dev->hba.bus_num.end = 255; 986 dino_dev->hba.bus_num.flags = IORESOURCE_BUS; 987 pci_add_resource(&resources, &dino_dev->hba.bus_num); 988 /* 989 ** It's not used to avoid chicken/egg problems 990 ** with configuration accessor functions. 991 */ 992 dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev, 993 dino_current_bus, &dino_cfg_ops, NULL, &resources); 994 if (!bus) { 995 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n", 996 dev_name(&dev->dev), dino_current_bus); 997 pci_free_resource_list(&resources); 998 /* increment the bus number in case of duplicates */ 999 dino_current_bus++; 1000 return 0; 1001 } 1002 1003 max = pci_scan_child_bus(bus); 1004 pci_bus_update_busn_res_end(bus, max); 1005 1006 /* This code *depends* on scanning being single threaded 1007 * if it isn't, this global bus number count will fail 1008 */ 1009 dino_current_bus = max + 1; 1010 pci_bus_assign_resources(bus); 1011 pci_bus_add_devices(bus); 1012 return 0; 1013 } 1014 1015 /* 1016 * Normally, we would just test sversion. But the Elroy PCI adapter has 1017 * the same sversion as Dino, so we have to check hversion as well. 1018 * Unfortunately, the J2240 PDC reports the wrong hversion for the first 1019 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. 1020 * For card-mode Dino, most machines report an sversion of 9D. But 715 1021 * and 725 firmware misreport it as 0x08080 for no adequately explained 1022 * reason. 1023 */ 1024 static const struct parisc_device_id dino_tbl[] __initconst = { 1025 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ 1026 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */ 1027 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ 1028 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ 1029 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ 1030 { 0, } 1031 }; 1032 1033 static struct parisc_driver dino_driver __refdata = { 1034 .name = "dino", 1035 .id_table = dino_tbl, 1036 .probe = dino_probe, 1037 }; 1038 1039 /* 1040 * One time initialization to let the world know Dino is here. 1041 * This is the only routine which is NOT static. 1042 * Must be called exactly once before pci_init(). 1043 */ 1044 int __init dino_init(void) 1045 { 1046 register_parisc_driver(&dino_driver); 1047 return 0; 1048 } 1049 1050