1 /* 2 ** DINO manager 3 ** 4 ** (c) Copyright 1999 Red Hat Software 5 ** (c) Copyright 1999 SuSE GmbH 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** (c) Copyright 2000 Grant Grundler 8 ** (c) Copyright 2006 Helge Deller 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** This module provides access to Dino PCI bus (config/IOport spaces) 16 ** and helps manage Dino IRQ lines. 17 ** 18 ** Dino interrupt handling is a bit complicated. 19 ** Dino always writes to the broadcast EIR via irr0 for now. 20 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) 21 ** Only one processor interrupt is used for the 11 IRQ line 22 ** inputs to dino. 23 ** 24 ** The different between Built-in Dino and Card-Mode 25 ** dino is in chip initialization and pci device initialization. 26 ** 27 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port 28 ** BARs are configured and used by the driver. Programming MMIO address 29 ** requires substantial knowledge of available Host I/O address ranges 30 ** is currently not supported. Port/Config accessor functions are the 31 ** same. "BIOS" differences are handled within the existing routines. 32 */ 33 34 /* Changes : 35 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) 36 ** - added support for the integrated RS232. 37 */ 38 39 /* 40 ** TODO: create a virtual address for each Dino HPA. 41 ** GSC code might be able to do this since IODC data tells us 42 ** how many pages are used. PCI subsystem could (must?) do this 43 ** for PCI drivers devices which implement/use MMIO registers. 44 */ 45 46 #include <linux/delay.h> 47 #include <linux/types.h> 48 #include <linux/kernel.h> 49 #include <linux/pci.h> 50 #include <linux/init.h> 51 #include <linux/ioport.h> 52 #include <linux/slab.h> 53 #include <linux/interrupt.h> /* for struct irqaction */ 54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */ 55 56 #include <asm/pdc.h> 57 #include <asm/page.h> 58 #include <asm/system.h> 59 #include <asm/io.h> 60 #include <asm/hardware.h> 61 62 #include "gsc.h" 63 64 #undef DINO_DEBUG 65 66 #ifdef DINO_DEBUG 67 #define DBG(x...) printk(x) 68 #else 69 #define DBG(x...) 70 #endif 71 72 /* 73 ** Config accessor functions only pass in the 8-bit bus number 74 ** and not the 8-bit "PCI Segment" number. Each Dino will be 75 ** assigned a PCI bus number based on "when" it's discovered. 76 ** 77 ** The "secondary" bus number is set to this before calling 78 ** pci_scan_bus(). If any PPB's are present, the scan will 79 ** discover them and update the "secondary" and "subordinate" 80 ** fields in Dino's pci_bus structure. 81 ** 82 ** Changes in the configuration *will* result in a different 83 ** bus number for each dino. 84 */ 85 86 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) 87 #define is_cujo(id) ((id)->hversion == 0x682) 88 89 #define DINO_IAR0 0x004 90 #define DINO_IODC_ADDR 0x008 91 #define DINO_IODC_DATA_0 0x008 92 #define DINO_IODC_DATA_1 0x008 93 #define DINO_IRR0 0x00C 94 #define DINO_IAR1 0x010 95 #define DINO_IRR1 0x014 96 #define DINO_IMR 0x018 97 #define DINO_IPR 0x01C 98 #define DINO_TOC_ADDR 0x020 99 #define DINO_ICR 0x024 100 #define DINO_ILR 0x028 101 #define DINO_IO_COMMAND 0x030 102 #define DINO_IO_STATUS 0x034 103 #define DINO_IO_CONTROL 0x038 104 #define DINO_IO_GSC_ERR_RESP 0x040 105 #define DINO_IO_ERR_INFO 0x044 106 #define DINO_IO_PCI_ERR_RESP 0x048 107 #define DINO_IO_FBB_EN 0x05c 108 #define DINO_IO_ADDR_EN 0x060 109 #define DINO_PCI_ADDR 0x064 110 #define DINO_CONFIG_DATA 0x068 111 #define DINO_IO_DATA 0x06c 112 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */ 113 #define DINO_GSC2X_CONFIG 0x7b4 114 #define DINO_GMASK 0x800 115 #define DINO_PAMR 0x804 116 #define DINO_PAPR 0x808 117 #define DINO_DAMODE 0x80c 118 #define DINO_PCICMD 0x810 119 #define DINO_PCISTS 0x814 120 #define DINO_MLTIM 0x81c 121 #define DINO_BRDG_FEAT 0x820 122 #define DINO_PCIROR 0x824 123 #define DINO_PCIWOR 0x828 124 #define DINO_TLTIM 0x830 125 126 #define DINO_IRQS 11 /* bits 0-10 are architected */ 127 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 128 #define DINO_LOCAL_IRQS (DINO_IRQS+1) 129 130 #define DINO_MASK_IRQ(x) (1<<(x)) 131 132 #define PCIINTA 0x001 133 #define PCIINTB 0x002 134 #define PCIINTC 0x004 135 #define PCIINTD 0x008 136 #define PCIINTE 0x010 137 #define PCIINTF 0x020 138 #define GSCEXTINT 0x040 139 /* #define xxx 0x080 - bit 7 is "default" */ 140 /* #define xxx 0x100 - bit 8 not used */ 141 /* #define xxx 0x200 - bit 9 not used */ 142 #define RS232INT 0x400 143 144 struct dino_device 145 { 146 struct pci_hba_data hba; /* 'C' inheritance - must be first */ 147 spinlock_t dinosaur_pen; 148 unsigned long txn_addr; /* EIR addr to generate interrupt */ 149 u32 txn_data; /* EIR data assign to each dino */ 150 u32 imr; /* IRQ's which are enabled */ 151 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ 152 #ifdef DINO_DEBUG 153 unsigned int dino_irr0; /* save most recent IRQ line stat */ 154 #endif 155 }; 156 157 /* Looks nice and keeps the compiler happy */ 158 #define DINO_DEV(d) ((struct dino_device *) d) 159 160 161 /* 162 * Dino Configuration Space Accessor Functions 163 */ 164 165 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) 166 167 /* 168 * keep the current highest bus count to assist in allocating busses. This 169 * tries to keep a global bus count total so that when we discover an 170 * entirely new bus, it can be given a unique bus number. 171 */ 172 static int dino_current_bus = 0; 173 174 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, 175 int size, u32 *val) 176 { 177 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 178 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 179 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 180 void __iomem *base_addr = d->hba.base_addr; 181 unsigned long flags; 182 183 DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where, 184 size); 185 spin_lock_irqsave(&d->dinosaur_pen, flags); 186 187 /* tell HW which CFG address */ 188 __raw_writel(v, base_addr + DINO_PCI_ADDR); 189 190 /* generate cfg read cycle */ 191 if (size == 1) { 192 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); 193 } else if (size == 2) { 194 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); 195 } else if (size == 4) { 196 *val = readl(base_addr + DINO_CONFIG_DATA); 197 } 198 199 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 200 return 0; 201 } 202 203 /* 204 * Dino address stepping "feature": 205 * When address stepping, Dino attempts to drive the bus one cycle too soon 206 * even though the type of cycle (config vs. MMIO) might be different. 207 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. 208 */ 209 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, 210 int size, u32 val) 211 { 212 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 213 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 214 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 215 void __iomem *base_addr = d->hba.base_addr; 216 unsigned long flags; 217 218 DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where, 219 size); 220 spin_lock_irqsave(&d->dinosaur_pen, flags); 221 222 /* avoid address stepping feature */ 223 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); 224 __raw_readl(base_addr + DINO_CONFIG_DATA); 225 226 /* tell HW which CFG address */ 227 __raw_writel(v, base_addr + DINO_PCI_ADDR); 228 /* generate cfg read cycle */ 229 if (size == 1) { 230 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); 231 } else if (size == 2) { 232 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); 233 } else if (size == 4) { 234 writel(val, base_addr + DINO_CONFIG_DATA); 235 } 236 237 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 238 return 0; 239 } 240 241 static struct pci_ops dino_cfg_ops = { 242 .read = dino_cfg_read, 243 .write = dino_cfg_write, 244 }; 245 246 247 /* 248 * Dino "I/O Port" Space Accessor Functions 249 * 250 * Many PCI devices don't require use of I/O port space (eg Tulip, 251 * NCR720) since they export the same registers to both MMIO and 252 * I/O port space. Performance is going to stink if drivers use 253 * I/O port instead of MMIO. 254 */ 255 256 #define DINO_PORT_IN(type, size, mask) \ 257 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ 258 { \ 259 u##size v; \ 260 unsigned long flags; \ 261 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 262 /* tell HW which IO Port address */ \ 263 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 264 /* generate I/O PORT read cycle */ \ 265 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ 266 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 267 return v; \ 268 } 269 270 DINO_PORT_IN(b, 8, 3) 271 DINO_PORT_IN(w, 16, 2) 272 DINO_PORT_IN(l, 32, 0) 273 274 #define DINO_PORT_OUT(type, size, mask) \ 275 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 276 { \ 277 unsigned long flags; \ 278 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 279 /* tell HW which IO port address */ \ 280 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 281 /* generate cfg write cycle */ \ 282 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ 283 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 284 } 285 286 DINO_PORT_OUT(b, 8, 3) 287 DINO_PORT_OUT(w, 16, 2) 288 DINO_PORT_OUT(l, 32, 0) 289 290 struct pci_port_ops dino_port_ops = { 291 .inb = dino_in8, 292 .inw = dino_in16, 293 .inl = dino_in32, 294 .outb = dino_out8, 295 .outw = dino_out16, 296 .outl = dino_out32 297 }; 298 299 static void dino_disable_irq(unsigned int irq) 300 { 301 struct dino_device *dino_dev = irq_desc[irq].chip_data; 302 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 303 304 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq); 305 306 /* Clear the matching bit in the IMR register */ 307 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); 308 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 309 } 310 311 static void dino_enable_irq(unsigned int irq) 312 { 313 struct dino_device *dino_dev = irq_desc[irq].chip_data; 314 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 315 u32 tmp; 316 317 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq); 318 319 /* 320 ** clear pending IRQ bits 321 ** 322 ** This does NOT change ILR state! 323 ** See comment below for ILR usage. 324 */ 325 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); 326 327 /* set the matching bit in the IMR register */ 328 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ 329 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 330 331 /* Emulate "Level Triggered" Interrupt 332 ** Basically, a driver is blowing it if the IRQ line is asserted 333 ** while the IRQ is disabled. But tulip.c seems to do that.... 334 ** Give 'em a kluge award and a nice round of applause! 335 ** 336 ** The gsc_write will generate an interrupt which invokes dino_isr(). 337 ** dino_isr() will read IPR and find nothing. But then catch this 338 ** when it also checks ILR. 339 */ 340 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); 341 if (tmp & DINO_MASK_IRQ(local_irq)) { 342 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", 343 __FUNCTION__, tmp); 344 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); 345 } 346 } 347 348 static unsigned int dino_startup_irq(unsigned int irq) 349 { 350 dino_enable_irq(irq); 351 return 0; 352 } 353 354 static struct hw_interrupt_type dino_interrupt_type = { 355 .typename = "GSC-PCI", 356 .startup = dino_startup_irq, 357 .shutdown = dino_disable_irq, 358 .enable = dino_enable_irq, 359 .disable = dino_disable_irq, 360 .ack = no_ack_irq, 361 .end = no_end_irq, 362 }; 363 364 365 /* 366 * Handle a Processor interrupt generated by Dino. 367 * 368 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from 369 * wedging the CPU. Could be removed or made optional at some point. 370 */ 371 static irqreturn_t dino_isr(int irq, void *intr_dev) 372 { 373 struct dino_device *dino_dev = intr_dev; 374 u32 mask; 375 int ilr_loop = 100; 376 377 /* read and acknowledge pending interrupts */ 378 #ifdef DINO_DEBUG 379 dino_dev->dino_irr0 = 380 #endif 381 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; 382 383 if (mask == 0) 384 return IRQ_NONE; 385 386 ilr_again: 387 do { 388 int local_irq = __ffs(mask); 389 int irq = dino_dev->global_irq[local_irq]; 390 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", 391 __FUNCTION__, irq, intr_dev, mask); 392 __do_IRQ(irq); 393 mask &= ~(1 << local_irq); 394 } while (mask); 395 396 /* Support for level triggered IRQ lines. 397 ** 398 ** Dropping this support would make this routine *much* faster. 399 ** But since PCI requires level triggered IRQ line to share lines... 400 ** device drivers may assume lines are level triggered (and not 401 ** edge triggered like EISA/ISA can be). 402 */ 403 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; 404 if (mask) { 405 if (--ilr_loop > 0) 406 goto ilr_again; 407 printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 408 dino_dev->hba.base_addr, mask); 409 return IRQ_NONE; 410 } 411 return IRQ_HANDLED; 412 } 413 414 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) 415 { 416 int irq = gsc_assign_irq(&dino_interrupt_type, dino); 417 if (irq == NO_IRQ) 418 return; 419 420 *irqp = irq; 421 dino->global_irq[local_irq] = irq; 422 } 423 424 static void dino_choose_irq(struct parisc_device *dev, void *ctrl) 425 { 426 int irq; 427 struct dino_device *dino = ctrl; 428 429 switch (dev->id.sversion) { 430 case 0x00084: irq = 8; break; /* PS/2 */ 431 case 0x0008c: irq = 10; break; /* RS232 */ 432 case 0x00096: irq = 8; break; /* PS/2 */ 433 default: return; /* Unknown */ 434 } 435 436 dino_assign_irq(dino, irq, &dev->irq); 437 } 438 439 440 /* 441 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de) 442 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) 443 */ 444 static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev) 445 { 446 u8 new_irq = dev->irq - 1; 447 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n", 448 pci_name(dev), dev->irq, new_irq); 449 dev->irq = new_irq; 450 } 451 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); 452 453 454 static void __init 455 dino_bios_init(void) 456 { 457 DBG("dino_bios_init\n"); 458 } 459 460 /* 461 * dino_card_setup - Set up the memory space for a Dino in card mode. 462 * @bus: the bus under this dino 463 * 464 * Claim an 8MB chunk of unused IO space and call the generic PCI routines 465 * to set up the addresses of the devices on this bus. 466 */ 467 #define _8MB 0x00800000UL 468 static void __init 469 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) 470 { 471 int i; 472 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 473 struct resource *res; 474 char name[128]; 475 int size; 476 477 res = &dino_dev->hba.lmmio_space; 478 res->flags = IORESOURCE_MEM; 479 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 480 bus->bridge->bus_id); 481 res->name = kmalloc(size+1, GFP_KERNEL); 482 if(res->name) 483 strcpy((char *)res->name, name); 484 else 485 res->name = dino_dev->hba.lmmio_space.name; 486 487 488 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, 489 F_EXTEND(0xf0000000UL) | _8MB, 490 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { 491 struct list_head *ln, *tmp_ln; 492 493 printk(KERN_ERR "Dino: cannot attach bus %s\n", 494 bus->bridge->bus_id); 495 /* kill the bus, we can't do anything with it */ 496 list_for_each_safe(ln, tmp_ln, &bus->devices) { 497 struct pci_dev *dev = pci_dev_b(ln); 498 499 list_del(&dev->global_list); 500 list_del(&dev->bus_list); 501 } 502 503 return; 504 } 505 bus->resource[1] = res; 506 bus->resource[0] = &(dino_dev->hba.io_space); 507 508 /* Now tell dino what range it has */ 509 for (i = 1; i < 31; i++) { 510 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) 511 break; 512 } 513 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n", 514 i, res->start, base_addr + DINO_IO_ADDR_EN); 515 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); 516 } 517 518 static void __init 519 dino_card_fixup(struct pci_dev *dev) 520 { 521 u32 irq_pin; 522 523 /* 524 ** REVISIT: card-mode PCI-PCI expansion chassis do exist. 525 ** Not sure they were ever productized. 526 ** Die here since we'll die later in dino_inb() anyway. 527 */ 528 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 529 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); 530 } 531 532 /* 533 ** Set Latency Timer to 0xff (not a shared bus) 534 ** Set CACHELINE_SIZE. 535 */ 536 dino_cfg_write(dev->bus, dev->devfn, 537 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 538 539 /* 540 ** Program INT_LINE for card-mode devices. 541 ** The cards are hardwired according to this algorithm. 542 ** And it doesn't matter if PPB's are present or not since 543 ** the IRQ lines bypass the PPB. 544 ** 545 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. 546 ** The additional "-1" adjusts for skewing the IRQ<->slot. 547 */ 548 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 549 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 550 551 /* Shouldn't really need to do this but it's in case someone tries 552 ** to bypass PCI services and look at the card themselves. 553 */ 554 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 555 } 556 557 /* The alignment contraints for PCI bridges under dino */ 558 #define DINO_BRIDGE_ALIGN 0x100000 559 560 561 static void __init 562 dino_fixup_bus(struct pci_bus *bus) 563 { 564 struct list_head *ln; 565 struct pci_dev *dev; 566 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 567 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num); 568 569 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n", 570 __FUNCTION__, bus, bus->secondary, 571 bus->bridge->platform_data); 572 573 /* Firmware doesn't set up card-mode dino, so we have to */ 574 if (is_card_dino(&dino_dev->hba.dev->id)) { 575 dino_card_setup(bus, dino_dev->hba.base_addr); 576 } else if(bus->parent == NULL) { 577 /* must have a dino above it, reparent the resources 578 * into the dino window */ 579 int i; 580 struct resource *res = &dino_dev->hba.lmmio_space; 581 582 bus->resource[0] = &(dino_dev->hba.io_space); 583 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 584 if(res[i].flags == 0) 585 break; 586 bus->resource[i+1] = &res[i]; 587 } 588 589 } else if(bus->self) { 590 int i; 591 592 pci_read_bridge_bases(bus); 593 594 595 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 596 if((bus->self->resource[i].flags & 597 (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 598 continue; 599 600 if(bus->self->resource[i].flags & IORESOURCE_MEM) { 601 /* There's a quirk to alignment of 602 * bridge memory resources: the start 603 * is the alignment and start-end is 604 * the size. However, firmware will 605 * have assigned start and end, so we 606 * need to take this into account */ 607 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; 608 bus->self->resource[i].start = DINO_BRIDGE_ALIGN; 609 610 } 611 612 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", 613 bus->self->dev.bus_id, i, 614 bus->self->resource[i].start, 615 bus->self->resource[i].end); 616 pci_assign_resource(bus->self, i); 617 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", 618 bus->self->dev.bus_id, i, 619 bus->self->resource[i].start, 620 bus->self->resource[i].end); 621 } 622 } 623 624 625 list_for_each(ln, &bus->devices) { 626 int i; 627 628 dev = pci_dev_b(ln); 629 if (is_card_dino(&dino_dev->hba.dev->id)) 630 dino_card_fixup(dev); 631 632 /* 633 ** P2PB's only have 2 BARs, no IRQs. 634 ** I'd like to just ignore them for now. 635 */ 636 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 637 continue; 638 639 /* Adjust the I/O Port space addresses */ 640 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 641 struct resource *res = &dev->resource[i]; 642 if (res->flags & IORESOURCE_IO) { 643 res->start |= port_base; 644 res->end |= port_base; 645 } 646 #ifdef __LP64__ 647 /* Sign Extend MMIO addresses */ 648 else if (res->flags & IORESOURCE_MEM) { 649 res->start |= F_EXTEND(0UL); 650 res->end |= F_EXTEND(0UL); 651 } 652 #endif 653 } 654 /* null out the ROM resource if there is one (we don't 655 * care about an expansion rom on parisc, since it 656 * usually contains (x86) bios code) */ 657 dev->resource[PCI_ROM_RESOURCE].flags = 0; 658 659 if(dev->irq == 255) { 660 661 #define DINO_FIX_UNASSIGNED_INTERRUPTS 662 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS 663 664 /* This code tries to assign an unassigned 665 * interrupt. Leave it disabled unless you 666 * *really* know what you're doing since the 667 * pin<->interrupt line mapping varies by bus 668 * and machine */ 669 670 u32 irq_pin; 671 672 dino_cfg_read(dev->bus, dev->devfn, 673 PCI_INTERRUPT_PIN, 1, &irq_pin); 674 irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 675 printk(KERN_WARNING "Device %s has undefined IRQ, " 676 "setting to %d\n", pci_name(dev), irq_pin); 677 dino_cfg_write(dev->bus, dev->devfn, 678 PCI_INTERRUPT_LINE, 1, irq_pin); 679 dino_assign_irq(dino_dev, irq_pin, &dev->irq); 680 #else 681 dev->irq = 65535; 682 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); 683 #endif 684 } else { 685 /* Adjust INT_LINE for that busses region */ 686 dino_assign_irq(dino_dev, dev->irq, &dev->irq); 687 } 688 } 689 } 690 691 692 struct pci_bios_ops dino_bios_ops = { 693 .init = dino_bios_init, 694 .fixup_bus = dino_fixup_bus 695 }; 696 697 698 /* 699 * Initialise a DINO controller chip 700 */ 701 static void __init 702 dino_card_init(struct dino_device *dino_dev) 703 { 704 u32 brdg_feat = 0x00784e05; 705 unsigned long status; 706 707 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); 708 if (status & 0x0000ff80) { 709 __raw_writel(0x00000005, 710 dino_dev->hba.base_addr+DINO_IO_COMMAND); 711 udelay(1); 712 } 713 714 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); 715 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); 716 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); 717 718 #if 1 719 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ 720 /* 721 ** PCX-L processors don't support XQL like Dino wants it. 722 ** PCX-L2 ignore XQL signal and it doesn't matter. 723 */ 724 brdg_feat &= ~0x4; /* UXQL */ 725 #endif 726 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); 727 728 /* 729 ** Don't enable address decoding until we know which I/O range 730 ** currently is available from the host. Only affects MMIO 731 ** and not I/O port space. 732 */ 733 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); 734 735 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); 736 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); 737 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); 738 739 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); 740 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); 741 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); 742 743 /* Disable PAMR before writing PAPR */ 744 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); 745 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); 746 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); 747 748 /* 749 ** Dino ERS encourages enabling FBB (0x6f). 750 ** We can't until we know *all* devices below us can support it. 751 ** (Something in device configuration header tells us). 752 */ 753 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); 754 755 /* Somewhere, the PCI spec says give devices 1 second 756 ** to recover from the #RESET being de-asserted. 757 ** Experience shows most devices only need 10ms. 758 ** This short-cut speeds up booting significantly. 759 */ 760 mdelay(pci_post_reset_delay); 761 } 762 763 static int __init 764 dino_bridge_init(struct dino_device *dino_dev, const char *name) 765 { 766 unsigned long io_addr; 767 int result, i, count=0; 768 struct resource *res, *prevres = NULL; 769 /* 770 * Decoding IO_ADDR_EN only works for Built-in Dino 771 * since PDC has already initialized this. 772 */ 773 774 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); 775 if (io_addr == 0) { 776 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); 777 return -ENODEV; 778 } 779 780 res = &dino_dev->hba.lmmio_space; 781 for (i = 0; i < 32; i++) { 782 unsigned long start, end; 783 784 if((io_addr & (1 << i)) == 0) 785 continue; 786 787 start = F_EXTEND(0xf0000000UL) | (i << 23); 788 end = start + 8 * 1024 * 1024 - 1; 789 790 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, 791 start, end); 792 793 if(prevres && prevres->end + 1 == start) { 794 prevres->end = end; 795 } else { 796 if(count >= DINO_MAX_LMMIO_RESOURCES) { 797 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); 798 break; 799 } 800 prevres = res; 801 res->start = start; 802 res->end = end; 803 res->flags = IORESOURCE_MEM; 804 res->name = kmalloc(64, GFP_KERNEL); 805 if(res->name) 806 snprintf((char *)res->name, 64, "%s LMMIO %d", 807 name, count); 808 res++; 809 count++; 810 } 811 } 812 813 res = &dino_dev->hba.lmmio_space; 814 815 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 816 if(res[i].flags == 0) 817 break; 818 819 result = ccio_request_resource(dino_dev->hba.dev, &res[i]); 820 if (result < 0) { 821 printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end); 822 return result; 823 } 824 } 825 return 0; 826 } 827 828 static int __init dino_common_init(struct parisc_device *dev, 829 struct dino_device *dino_dev, const char *name) 830 { 831 int status; 832 u32 eim; 833 struct gsc_irq gsc_irq; 834 struct resource *res; 835 836 pcibios_register_hba(&dino_dev->hba); 837 838 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ 839 pci_port = &dino_port_ops; 840 841 /* 842 ** Note: SMP systems can make use of IRR1/IAR1 registers 843 ** But it won't buy much performance except in very 844 ** specific applications/configurations. Note Dino 845 ** still only has 11 IRQ input lines - just map some of them 846 ** to a different processor. 847 */ 848 dev->irq = gsc_alloc_irq(&gsc_irq); 849 dino_dev->txn_addr = gsc_irq.txn_addr; 850 dino_dev->txn_data = gsc_irq.txn_data; 851 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; 852 853 /* 854 ** Dino needs a PA "IRQ" to get a processor's attention. 855 ** arch/parisc/kernel/irq.c returns an EIRR bit. 856 */ 857 if (dev->irq < 0) { 858 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); 859 return 1; 860 } 861 862 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); 863 if (status) { 864 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 865 name, status); 866 return 1; 867 } 868 869 /* Support the serial port which is sometimes attached on built-in 870 * Dino / Cujo chips. 871 */ 872 873 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); 874 875 /* 876 ** This enables DINO to generate interrupts when it sees 877 ** any of its inputs *change*. Just asserting an IRQ 878 ** before it's enabled (ie unmasked) isn't good enough. 879 */ 880 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); 881 882 /* 883 ** Some platforms don't clear Dino's IRR0 register at boot time. 884 ** Reading will clear it now. 885 */ 886 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); 887 888 /* allocate I/O Port resource region */ 889 res = &dino_dev->hba.io_space; 890 if (!is_cujo(&dev->id)) { 891 res->name = "Dino I/O Port"; 892 } else { 893 res->name = "Cujo I/O Port"; 894 } 895 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); 896 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); 897 res->flags = IORESOURCE_IO; /* do not mark it busy ! */ 898 if (request_resource(&ioport_resource, res) < 0) { 899 printk(KERN_ERR "%s: request I/O Port region failed " 900 "0x%lx/%lx (hpa 0x%p)\n", 901 name, res->start, res->end, dino_dev->hba.base_addr); 902 return 1; 903 } 904 905 return 0; 906 } 907 908 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) 909 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) 910 #define CUJO_RAVEN_BADPAGE 0x01003000UL 911 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL 912 913 static const char *dino_vers[] = { 914 "2.0", 915 "2.1", 916 "3.0", 917 "3.1" 918 }; 919 920 static const char *cujo_vers[] = { 921 "1.0", 922 "2.0" 923 }; 924 925 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); 926 927 /* 928 ** Determine if dino should claim this chip (return 0) or not (return 1). 929 ** If so, initialize the chip appropriately (card-mode vs bridge mode). 930 ** Much of the initialization is common though. 931 */ 932 static int __init dino_probe(struct parisc_device *dev) 933 { 934 struct dino_device *dino_dev; // Dino specific control struct 935 const char *version = "unknown"; 936 char *name; 937 int is_cujo = 0; 938 struct pci_bus *bus; 939 unsigned long hpa = dev->hpa.start; 940 941 name = "Dino"; 942 if (is_card_dino(&dev->id)) { 943 version = "3.x (card mode)"; 944 } else { 945 if (!is_cujo(&dev->id)) { 946 if (dev->id.hversion_rev < 4) { 947 version = dino_vers[dev->id.hversion_rev]; 948 } 949 } else { 950 name = "Cujo"; 951 is_cujo = 1; 952 if (dev->id.hversion_rev < 2) { 953 version = cujo_vers[dev->id.hversion_rev]; 954 } 955 } 956 } 957 958 printk("%s version %s found at 0x%lx\n", name, version, hpa); 959 960 if (!request_mem_region(hpa, PAGE_SIZE, name)) { 961 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n", 962 hpa); 963 return 1; 964 } 965 966 /* Check for bugs */ 967 if (is_cujo && dev->id.hversion_rev == 1) { 968 #ifdef CONFIG_IOMMU_CCIO 969 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); 970 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { 971 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); 972 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { 973 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); 974 } else { 975 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa); 976 } 977 #endif 978 } else if (!is_cujo && !is_card_dino(&dev->id) && 979 dev->id.hversion_rev < 3) { 980 printk(KERN_WARNING 981 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" 982 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" 983 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" 984 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", 985 dev->id.hversion_rev); 986 /* REVISIT: why are C200/C240 listed in the README table but not 987 ** "Models affected"? Could be an omission in the original literature. 988 */ 989 } 990 991 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL); 992 if (!dino_dev) { 993 printk("dino_init_chip - couldn't alloc dino_device\n"); 994 return 1; 995 } 996 997 dino_dev->hba.dev = dev; 998 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096); 999 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */ 1000 spin_lock_init(&dino_dev->dinosaur_pen); 1001 dino_dev->hba.iommu = ccio_get_iommu(dev); 1002 1003 if (is_card_dino(&dev->id)) { 1004 dino_card_init(dino_dev); 1005 } else { 1006 dino_bridge_init(dino_dev, name); 1007 } 1008 1009 if (dino_common_init(dev, dino_dev, name)) 1010 return 1; 1011 1012 dev->dev.platform_data = dino_dev; 1013 1014 /* 1015 ** It's not used to avoid chicken/egg problems 1016 ** with configuration accessor functions. 1017 */ 1018 bus = pci_scan_bus_parented(&dev->dev, dino_current_bus, 1019 &dino_cfg_ops, NULL); 1020 if(bus) { 1021 pci_bus_add_devices(bus); 1022 /* This code *depends* on scanning being single threaded 1023 * if it isn't, this global bus number count will fail 1024 */ 1025 dino_current_bus = bus->subordinate + 1; 1026 pci_bus_assign_resources(bus); 1027 } else { 1028 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus); 1029 /* increment the bus number in case of duplicates */ 1030 dino_current_bus++; 1031 } 1032 dino_dev->hba.hba_bus = bus; 1033 return 0; 1034 } 1035 1036 /* 1037 * Normally, we would just test sversion. But the Elroy PCI adapter has 1038 * the same sversion as Dino, so we have to check hversion as well. 1039 * Unfortunately, the J2240 PDC reports the wrong hversion for the first 1040 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. 1041 * For card-mode Dino, most machines report an sversion of 9D. But 715 1042 * and 725 firmware misreport it as 0x08080 for no adequately explained 1043 * reason. 1044 */ 1045 static struct parisc_device_id dino_tbl[] = { 1046 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ 1047 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */ 1048 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ 1049 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ 1050 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ 1051 { 0, } 1052 }; 1053 1054 static struct parisc_driver dino_driver = { 1055 .name = "dino", 1056 .id_table = dino_tbl, 1057 .probe = dino_probe, 1058 }; 1059 1060 /* 1061 * One time initialization to let the world know Dino is here. 1062 * This is the only routine which is NOT static. 1063 * Must be called exactly once before pci_init(). 1064 */ 1065 int __init dino_init(void) 1066 { 1067 register_parisc_driver(&dino_driver); 1068 return 0; 1069 } 1070 1071