1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 ** ccio-dma.c: 4 ** DMA management routines for first generation cache-coherent machines. 5 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. 6 ** 7 ** (c) Copyright 2000 Grant Grundler 8 ** (c) Copyright 2000 Ryan Bradetich 9 ** (c) Copyright 2000 Hewlett-Packard Company 10 ** 11 ** 12 ** 13 ** "Real Mode" operation refers to U2/Uturn chip operation. 14 ** U2/Uturn were designed to perform coherency checks w/o using 15 ** the I/O MMU - basically what x86 does. 16 ** 17 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: 18 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc 19 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c 20 ** 21 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. 22 ** 23 ** Drawbacks of using Real Mode are: 24 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal). 25 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute. 26 ** o Ability to do scatter/gather in HW is lost. 27 ** o Doesn't work under PCX-U/U+ machines since they didn't follow 28 ** the coherency design originally worked out. Only PCX-W does. 29 */ 30 31 #include <linux/types.h> 32 #include <linux/kernel.h> 33 #include <linux/init.h> 34 #include <linux/mm.h> 35 #include <linux/spinlock.h> 36 #include <linux/slab.h> 37 #include <linux/string.h> 38 #include <linux/pci.h> 39 #include <linux/reboot.h> 40 #include <linux/proc_fs.h> 41 #include <linux/seq_file.h> 42 #include <linux/scatterlist.h> 43 #include <linux/iommu-helper.h> 44 #include <linux/export.h> 45 46 #include <asm/byteorder.h> 47 #include <asm/cache.h> /* for L1_CACHE_BYTES */ 48 #include <linux/uaccess.h> 49 #include <asm/page.h> 50 #include <asm/dma.h> 51 #include <asm/io.h> 52 #include <asm/hardware.h> /* for register_module() */ 53 #include <asm/parisc-device.h> 54 55 #include "iommu.h" 56 57 /* 58 ** Choose "ccio" since that's what HP-UX calls it. 59 ** Make it easier for folks to migrate from one to the other :^) 60 */ 61 #define MODULE_NAME "ccio" 62 63 #undef DEBUG_CCIO_RES 64 #undef DEBUG_CCIO_RUN 65 #undef DEBUG_CCIO_INIT 66 #undef DEBUG_CCIO_RUN_SG 67 68 #ifdef CONFIG_PROC_FS 69 /* depends on proc fs support. But costs CPU performance. */ 70 #undef CCIO_COLLECT_STATS 71 #endif 72 73 #include <asm/runway.h> /* for proc_runway_root */ 74 75 #ifdef DEBUG_CCIO_INIT 76 #define DBG_INIT(x...) printk(x) 77 #else 78 #define DBG_INIT(x...) 79 #endif 80 81 #ifdef DEBUG_CCIO_RUN 82 #define DBG_RUN(x...) printk(x) 83 #else 84 #define DBG_RUN(x...) 85 #endif 86 87 #ifdef DEBUG_CCIO_RES 88 #define DBG_RES(x...) printk(x) 89 #else 90 #define DBG_RES(x...) 91 #endif 92 93 #ifdef DEBUG_CCIO_RUN_SG 94 #define DBG_RUN_SG(x...) printk(x) 95 #else 96 #define DBG_RUN_SG(x...) 97 #endif 98 99 #define CCIO_INLINE inline 100 #define WRITE_U32(value, addr) __raw_writel(value, addr) 101 #define READ_U32(addr) __raw_readl(addr) 102 103 #define U2_IOA_RUNWAY 0x580 104 #define U2_BC_GSC 0x501 105 #define UTURN_IOA_RUNWAY 0x581 106 #define UTURN_BC_GSC 0x502 107 108 #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */ 109 #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */ 110 #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */ 111 112 struct ioa_registers { 113 /* Runway Supervisory Set */ 114 int32_t unused1[12]; 115 uint32_t io_command; /* Offset 12 */ 116 uint32_t io_status; /* Offset 13 */ 117 uint32_t io_control; /* Offset 14 */ 118 int32_t unused2[1]; 119 120 /* Runway Auxiliary Register Set */ 121 uint32_t io_err_resp; /* Offset 0 */ 122 uint32_t io_err_info; /* Offset 1 */ 123 uint32_t io_err_req; /* Offset 2 */ 124 uint32_t io_err_resp_hi; /* Offset 3 */ 125 uint32_t io_tlb_entry_m; /* Offset 4 */ 126 uint32_t io_tlb_entry_l; /* Offset 5 */ 127 uint32_t unused3[1]; 128 uint32_t io_pdir_base; /* Offset 7 */ 129 uint32_t io_io_low_hv; /* Offset 8 */ 130 uint32_t io_io_high_hv; /* Offset 9 */ 131 uint32_t unused4[1]; 132 uint32_t io_chain_id_mask; /* Offset 11 */ 133 uint32_t unused5[2]; 134 uint32_t io_io_low; /* Offset 14 */ 135 uint32_t io_io_high; /* Offset 15 */ 136 }; 137 138 /* 139 ** IOA Registers 140 ** ------------- 141 ** 142 ** Runway IO_CONTROL Register (+0x38) 143 ** 144 ** The Runway IO_CONTROL register controls the forwarding of transactions. 145 ** 146 ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 | 147 ** | HV | TLB | reserved | HV | mode | reserved | 148 ** 149 ** o mode field indicates the address translation of transactions 150 ** forwarded from Runway to GSC+: 151 ** Mode Name Value Definition 152 ** Off (default) 0 Opaque to matching addresses. 153 ** Include 1 Transparent for matching addresses. 154 ** Peek 3 Map matching addresses. 155 ** 156 ** + "Off" mode: Runway transactions which match the I/O range 157 ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored. 158 ** + "Include" mode: all addresses within the I/O range specified 159 ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently 160 ** forwarded. This is the I/O Adapter's normal operating mode. 161 ** + "Peek" mode: used during system configuration to initialize the 162 ** GSC+ bus. Runway Write_Shorts in the address range specified by 163 ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter 164 ** *AND* the GSC+ address is remapped to the Broadcast Physical 165 ** Address space by setting the 14 high order address bits of the 166 ** 32 bit GSC+ address to ones. 167 ** 168 ** o TLB field affects transactions which are forwarded from GSC+ to Runway. 169 ** "Real" mode is the poweron default. 170 ** 171 ** TLB Mode Value Description 172 ** Real 0 No TLB translation. Address is directly mapped and the 173 ** virtual address is composed of selected physical bits. 174 ** Error 1 Software fills the TLB manually. 175 ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory). 176 ** 177 ** 178 ** IO_IO_LOW_HV +0x60 (HV dependent) 179 ** IO_IO_HIGH_HV +0x64 (HV dependent) 180 ** IO_IO_LOW +0x78 (Architected register) 181 ** IO_IO_HIGH +0x7c (Architected register) 182 ** 183 ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the 184 ** I/O Adapter address space, respectively. 185 ** 186 ** 0 ... 7 | 8 ... 15 | 16 ... 31 | 187 ** 11111111 | 11111111 | address | 188 ** 189 ** Each LOW/HIGH pair describes a disjoint address space region. 190 ** (2 per GSC+ port). Each incoming Runway transaction address is compared 191 ** with both sets of LOW/HIGH registers. If the address is in the range 192 ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction 193 ** for forwarded to the respective GSC+ bus. 194 ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying 195 ** an address space region. 196 ** 197 ** In order for a Runway address to reside within GSC+ extended address space: 198 ** Runway Address [0:7] must identically compare to 8'b11111111 199 ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19] 200 ** Runway Address [12:23] must be greater than or equal to 201 ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31]. 202 ** Runway Address [24:39] is not used in the comparison. 203 ** 204 ** When the Runway transaction is forwarded to GSC+, the GSC+ address is 205 ** as follows: 206 ** GSC+ Address[0:3] 4'b1111 207 ** GSC+ Address[4:29] Runway Address[12:37] 208 ** GSC+ Address[30:31] 2'b00 209 ** 210 ** All 4 Low/High registers must be initialized (by PDC) once the lower bus 211 ** is interrogated and address space is defined. The operating system will 212 ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following 213 ** the PDC initialization. However, the hardware version dependent IO_IO_LOW 214 ** and IO_IO_HIGH registers should not be subsequently altered by the OS. 215 ** 216 ** Writes to both sets of registers will take effect immediately, bypassing 217 ** the queues, which ensures that subsequent Runway transactions are checked 218 ** against the updated bounds values. However reads are queued, introducing 219 ** the possibility of a read being bypassed by a subsequent write to the same 220 ** register. This sequence can be avoided by having software wait for read 221 ** returns before issuing subsequent writes. 222 */ 223 224 struct ioc { 225 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */ 226 u8 *res_map; /* resource map, bit == pdir entry */ 227 u64 *pdir_base; /* physical base address */ 228 u32 pdir_size; /* bytes, function of IOV Space size */ 229 u32 res_hint; /* next available IOVP - 230 circular search */ 231 u32 res_size; /* size of resource map in bytes */ 232 spinlock_t res_lock; 233 234 #ifdef CCIO_COLLECT_STATS 235 #define CCIO_SEARCH_SAMPLE 0x100 236 unsigned long avg_search[CCIO_SEARCH_SAMPLE]; 237 unsigned long avg_idx; /* current index into avg_search */ 238 unsigned long used_pages; 239 unsigned long msingle_calls; 240 unsigned long msingle_pages; 241 unsigned long msg_calls; 242 unsigned long msg_pages; 243 unsigned long usingle_calls; 244 unsigned long usingle_pages; 245 unsigned long usg_calls; 246 unsigned long usg_pages; 247 #endif 248 unsigned short cujo20_bug; 249 250 /* STUFF We don't need in performance path */ 251 u32 chainid_shift; /* specify bit location of chain_id */ 252 struct ioc *next; /* Linked list of discovered iocs */ 253 const char *name; /* device name from firmware */ 254 unsigned int hw_path; /* the hardware path this ioc is associatd with */ 255 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */ 256 struct resource mmio_region[2]; /* The "routed" MMIO regions */ 257 }; 258 259 static struct ioc *ioc_list; 260 static int ioc_count; 261 262 /************************************************************** 263 * 264 * I/O Pdir Resource Management 265 * 266 * Bits set in the resource map are in use. 267 * Each bit can represent a number of pages. 268 * LSbs represent lower addresses (IOVA's). 269 * 270 * This was was copied from sba_iommu.c. Don't try to unify 271 * the two resource managers unless a way to have different 272 * allocation policies is also adjusted. We'd like to avoid 273 * I/O TLB thrashing by having resource allocation policy 274 * match the I/O TLB replacement policy. 275 * 276 ***************************************************************/ 277 #define IOVP_SIZE PAGE_SIZE 278 #define IOVP_SHIFT PAGE_SHIFT 279 #define IOVP_MASK PAGE_MASK 280 281 /* Convert from IOVP to IOVA and vice versa. */ 282 #define CCIO_IOVA(iovp,offset) ((iovp) | (offset)) 283 #define CCIO_IOVP(iova) ((iova) & IOVP_MASK) 284 285 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 286 #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT) 287 #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset) 288 289 /* 290 ** Don't worry about the 150% average search length on a miss. 291 ** If the search wraps around, and passes the res_hint, it will 292 ** cause the kernel to panic anyhow. 293 */ 294 #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ 295 for(; res_ptr < res_end; ++res_ptr) { \ 296 int ret;\ 297 unsigned int idx;\ 298 idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \ 299 ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\ 300 if ((0 == (*res_ptr & mask)) && !ret) { \ 301 *res_ptr |= mask; \ 302 res_idx = idx;\ 303 ioc->res_hint = res_idx + (size >> 3); \ 304 goto resource_found; \ 305 } \ 306 } 307 308 #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ 309 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \ 310 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \ 311 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ 312 res_ptr = (u##size *)&(ioc)->res_map[0]; \ 313 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); 314 315 /* 316 ** Find available bit in this ioa's resource map. 317 ** Use a "circular" search: 318 ** o Most IOVA's are "temporary" - avg search time should be small. 319 ** o keep a history of what happened for debugging 320 ** o KISS. 321 ** 322 ** Perf optimizations: 323 ** o search for log2(size) bits at a time. 324 ** o search for available resource bits using byte/word/whatever. 325 ** o use different search for "large" (eg > 4 pages) or "very large" 326 ** (eg > 16 pages) mappings. 327 */ 328 329 /** 330 * ccio_alloc_range - Allocate pages in the ioc's resource map. 331 * @ioc: The I/O Controller. 332 * @pages_needed: The requested number of pages to be mapped into the 333 * I/O Pdir... 334 * 335 * This function searches the resource map of the ioc to locate a range 336 * of available pages for the requested size. 337 */ 338 static int 339 ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 340 { 341 unsigned int pages_needed = size >> IOVP_SHIFT; 342 unsigned int res_idx; 343 unsigned long boundary_size; 344 #ifdef CCIO_COLLECT_STATS 345 unsigned long cr_start = mfctl(16); 346 #endif 347 348 BUG_ON(pages_needed == 0); 349 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE); 350 351 DBG_RES("%s() size: %d pages_needed %d\n", 352 __func__, size, pages_needed); 353 354 /* 355 ** "seek and ye shall find"...praying never hurts either... 356 ** ggg sacrifices another 710 to the computer gods. 357 */ 358 359 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, 360 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; 361 362 if (pages_needed <= 8) { 363 /* 364 * LAN traffic will not thrash the TLB IFF the same NIC 365 * uses 8 adjacent pages to map separate payload data. 366 * ie the same byte in the resource bit map. 367 */ 368 #if 0 369 /* FIXME: bit search should shift it's way through 370 * an unsigned long - not byte at a time. As it is now, 371 * we effectively allocate this byte to this mapping. 372 */ 373 unsigned long mask = ~(~0UL >> pages_needed); 374 CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8); 375 #else 376 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8); 377 #endif 378 } else if (pages_needed <= 16) { 379 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16); 380 } else if (pages_needed <= 32) { 381 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32); 382 #ifdef __LP64__ 383 } else if (pages_needed <= 64) { 384 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64); 385 #endif 386 } else { 387 panic("%s: %s() Too many pages to map. pages_needed: %u\n", 388 __FILE__, __func__, pages_needed); 389 } 390 391 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__, 392 __func__); 393 394 resource_found: 395 396 DBG_RES("%s() res_idx %d res_hint: %d\n", 397 __func__, res_idx, ioc->res_hint); 398 399 #ifdef CCIO_COLLECT_STATS 400 { 401 unsigned long cr_end = mfctl(16); 402 unsigned long tmp = cr_end - cr_start; 403 /* check for roll over */ 404 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 405 } 406 ioc->avg_search[ioc->avg_idx++] = cr_start; 407 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; 408 ioc->used_pages += pages_needed; 409 #endif 410 /* 411 ** return the bit address. 412 */ 413 return res_idx << 3; 414 } 415 416 #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ 417 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \ 418 BUG_ON((*res_ptr & mask) != mask); \ 419 *res_ptr &= ~(mask); 420 421 /** 422 * ccio_free_range - Free pages from the ioc's resource map. 423 * @ioc: The I/O Controller. 424 * @iova: The I/O Virtual Address. 425 * @pages_mapped: The requested number of pages to be freed from the 426 * I/O Pdir. 427 * 428 * This function frees the resouces allocated for the iova. 429 */ 430 static void 431 ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped) 432 { 433 unsigned long iovp = CCIO_IOVP(iova); 434 unsigned int res_idx = PDIR_INDEX(iovp) >> 3; 435 436 BUG_ON(pages_mapped == 0); 437 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE); 438 BUG_ON(pages_mapped > BITS_PER_LONG); 439 440 DBG_RES("%s(): res_idx: %d pages_mapped %d\n", 441 __func__, res_idx, pages_mapped); 442 443 #ifdef CCIO_COLLECT_STATS 444 ioc->used_pages -= pages_mapped; 445 #endif 446 447 if(pages_mapped <= 8) { 448 #if 0 449 /* see matching comments in alloc_range */ 450 unsigned long mask = ~(~0UL >> pages_mapped); 451 CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8); 452 #else 453 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8); 454 #endif 455 } else if(pages_mapped <= 16) { 456 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16); 457 } else if(pages_mapped <= 32) { 458 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32); 459 #ifdef __LP64__ 460 } else if(pages_mapped <= 64) { 461 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64); 462 #endif 463 } else { 464 panic("%s:%s() Too many pages to unmap.\n", __FILE__, 465 __func__); 466 } 467 } 468 469 /**************************************************************** 470 ** 471 ** CCIO dma_ops support routines 472 ** 473 *****************************************************************/ 474 475 typedef unsigned long space_t; 476 #define KERNEL_SPACE 0 477 478 /* 479 ** DMA "Page Type" and Hints 480 ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be 481 ** set for subcacheline DMA transfers since we don't want to damage the 482 ** other part of a cacheline. 483 ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent(). 484 ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming" 485 ** data can avoid this if the mapping covers full cache lines. 486 ** o STOP_MOST is needed for atomicity across cachelines. 487 ** Apparently only "some EISA devices" need this. 488 ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs 489 ** to use this hint iff the EISA devices needs this feature. 490 ** According to the U2 ERS, STOP_MOST enabled pages hurt performance. 491 ** o PREFETCH should *not* be set for cases like Multiple PCI devices 492 ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC 493 ** device can be fetched and multiply DMA streams will thrash the 494 ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules 495 ** and Invalidation of Prefetch Entries". 496 ** 497 ** FIXME: the default hints need to be per GSC device - not global. 498 ** 499 ** HP-UX dorks: linux device driver programming model is totally different 500 ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers 501 ** do special things to work on non-coherent platforms...linux has to 502 ** be much more careful with this. 503 */ 504 #define IOPDIR_VALID 0x01UL 505 #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */ 506 #ifdef CONFIG_EISA 507 #define HINT_STOP_MOST 0x04UL /* LSL support */ 508 #else 509 #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */ 510 #endif 511 #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */ 512 #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */ 513 514 515 /* 516 ** Use direction (ie PCI_DMA_TODEVICE) to pick hint. 517 ** ccio_alloc_consistent() depends on this to get SAFE_DMA 518 ** when it passes in BIDIRECTIONAL flag. 519 */ 520 static u32 hint_lookup[] = { 521 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID, 522 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID, 523 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID, 524 }; 525 526 /** 527 * ccio_io_pdir_entry - Initialize an I/O Pdir. 528 * @pdir_ptr: A pointer into I/O Pdir. 529 * @sid: The Space Identifier. 530 * @vba: The virtual address. 531 * @hints: The DMA Hint. 532 * 533 * Given a virtual address (vba, arg2) and space id, (sid, arg1), 534 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir 535 * entry consists of 8 bytes as shown below (MSB == bit 0): 536 * 537 * 538 * WORD 0: 539 * +------+----------------+-----------------------------------------------+ 540 * | Phys | Virtual Index | Phys | 541 * | 0:3 | 0:11 | 4:19 | 542 * |4 bits| 12 bits | 16 bits | 543 * +------+----------------+-----------------------------------------------+ 544 * WORD 1: 545 * +-----------------------+-----------------------------------------------+ 546 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid | 547 * | 20:39 | | Enable |Enable | |Enable|DMA | | 548 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit | 549 * +-----------------------+-----------------------------------------------+ 550 * 551 * The virtual index field is filled with the results of the LCI 552 * (Load Coherence Index) instruction. The 8 bits used for the virtual 553 * index are bits 12:19 of the value returned by LCI. 554 */ 555 static void CCIO_INLINE 556 ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 557 unsigned long hints) 558 { 559 register unsigned long pa; 560 register unsigned long ci; /* coherent index */ 561 562 /* We currently only support kernel addresses */ 563 BUG_ON(sid != KERNEL_SPACE); 564 565 mtsp(sid,1); 566 567 /* 568 ** WORD 1 - low order word 569 ** "hints" parm includes the VALID bit! 570 ** "dep" clobbers the physical address offset bits as well. 571 */ 572 pa = virt_to_phys(vba); 573 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints)); 574 ((u32 *)pdir_ptr)[1] = (u32) pa; 575 576 /* 577 ** WORD 0 - high order word 578 */ 579 580 #ifdef __LP64__ 581 /* 582 ** get bits 12:15 of physical address 583 ** shift bits 16:31 of physical address 584 ** and deposit them 585 */ 586 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa)); 587 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa)); 588 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci)); 589 #else 590 pa = 0; 591 #endif 592 /* 593 ** get CPU coherency index bits 594 ** Grab virtual index [0:11] 595 ** Deposit virt_idx bits into I/O PDIR word 596 */ 597 asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 598 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci)); 599 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci)); 600 601 ((u32 *)pdir_ptr)[0] = (u32) pa; 602 603 604 /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) 605 ** PCX-U/U+ do. (eg C200/C240) 606 ** PCX-T'? Don't know. (eg C110 or similar K-class) 607 ** 608 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit". 609 ** 610 ** "Since PCX-U employs an offset hash that is incompatible with 611 ** the real mode coherence index generation of U2, the PDIR entry 612 ** must be flushed to memory to retain coherence." 613 */ 614 asm_io_fdc(pdir_ptr); 615 asm_io_sync(); 616 } 617 618 /** 619 * ccio_clear_io_tlb - Remove stale entries from the I/O TLB. 620 * @ioc: The I/O Controller. 621 * @iovp: The I/O Virtual Page. 622 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. 623 * 624 * Purge invalid I/O PDIR entries from the I/O TLB. 625 * 626 * FIXME: Can we change the byte_cnt to pages_mapped? 627 */ 628 static CCIO_INLINE void 629 ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt) 630 { 631 u32 chain_size = 1 << ioc->chainid_shift; 632 633 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */ 634 byte_cnt += chain_size; 635 636 while(byte_cnt > chain_size) { 637 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); 638 iovp += chain_size; 639 byte_cnt -= chain_size; 640 } 641 } 642 643 /** 644 * ccio_mark_invalid - Mark the I/O Pdir entries invalid. 645 * @ioc: The I/O Controller. 646 * @iova: The I/O Virtual Address. 647 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. 648 * 649 * Mark the I/O Pdir entries invalid and blow away the corresponding I/O 650 * TLB entries. 651 * 652 * FIXME: at some threshold it might be "cheaper" to just blow 653 * away the entire I/O TLB instead of individual entries. 654 * 655 * FIXME: Uturn has 256 TLB entries. We don't need to purge every 656 * PDIR entry - just once for each possible TLB entry. 657 * (We do need to maker I/O PDIR entries invalid regardless). 658 * 659 * FIXME: Can we change byte_cnt to pages_mapped? 660 */ 661 static CCIO_INLINE void 662 ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 663 { 664 u32 iovp = (u32)CCIO_IOVP(iova); 665 size_t saved_byte_cnt; 666 667 /* round up to nearest page size */ 668 saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE); 669 670 while(byte_cnt > 0) { 671 /* invalidate one page at a time */ 672 unsigned int idx = PDIR_INDEX(iovp); 673 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); 674 675 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); 676 pdir_ptr[7] = 0; /* clear only VALID bit */ 677 /* 678 ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) 679 ** PCX-U/U+ do. (eg C200/C240) 680 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit". 681 */ 682 asm_io_fdc(pdir_ptr); 683 684 iovp += IOVP_SIZE; 685 byte_cnt -= IOVP_SIZE; 686 } 687 688 asm_io_sync(); 689 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt); 690 } 691 692 /**************************************************************** 693 ** 694 ** CCIO dma_ops 695 ** 696 *****************************************************************/ 697 698 /** 699 * ccio_dma_supported - Verify the IOMMU supports the DMA address range. 700 * @dev: The PCI device. 701 * @mask: A bit mask describing the DMA address range of the device. 702 */ 703 static int 704 ccio_dma_supported(struct device *dev, u64 mask) 705 { 706 if(dev == NULL) { 707 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 708 BUG(); 709 return 0; 710 } 711 712 /* only support 32-bit or better devices (ie PCI/GSC) */ 713 return (int)(mask >= 0xffffffffUL); 714 } 715 716 /** 717 * ccio_map_single - Map an address range into the IOMMU. 718 * @dev: The PCI device. 719 * @addr: The start address of the DMA region. 720 * @size: The length of the DMA region. 721 * @direction: The direction of the DMA transaction (to/from device). 722 * 723 * This function implements the pci_map_single function. 724 */ 725 static dma_addr_t 726 ccio_map_single(struct device *dev, void *addr, size_t size, 727 enum dma_data_direction direction) 728 { 729 int idx; 730 struct ioc *ioc; 731 unsigned long flags; 732 dma_addr_t iovp; 733 dma_addr_t offset; 734 u64 *pdir_start; 735 unsigned long hint = hint_lookup[(int)direction]; 736 737 BUG_ON(!dev); 738 ioc = GET_IOC(dev); 739 if (!ioc) 740 return DMA_MAPPING_ERROR; 741 742 BUG_ON(size <= 0); 743 744 /* save offset bits */ 745 offset = ((unsigned long) addr) & ~IOVP_MASK; 746 747 /* round up to nearest IOVP_SIZE */ 748 size = ALIGN(size + offset, IOVP_SIZE); 749 spin_lock_irqsave(&ioc->res_lock, flags); 750 751 #ifdef CCIO_COLLECT_STATS 752 ioc->msingle_calls++; 753 ioc->msingle_pages += size >> IOVP_SHIFT; 754 #endif 755 756 idx = ccio_alloc_range(ioc, dev, size); 757 iovp = (dma_addr_t)MKIOVP(idx); 758 759 pdir_start = &(ioc->pdir_base[idx]); 760 761 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", 762 __func__, addr, (long)iovp | offset, size); 763 764 /* If not cacheline aligned, force SAFE_DMA on the whole mess */ 765 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES)) 766 hint |= HINT_SAFE_DMA; 767 768 while(size > 0) { 769 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint); 770 771 DBG_RUN(" pdir %p %08x%08x\n", 772 pdir_start, 773 (u32) (((u32 *) pdir_start)[0]), 774 (u32) (((u32 *) pdir_start)[1])); 775 ++pdir_start; 776 addr += IOVP_SIZE; 777 size -= IOVP_SIZE; 778 } 779 780 spin_unlock_irqrestore(&ioc->res_lock, flags); 781 782 /* form complete address */ 783 return CCIO_IOVA(iovp, offset); 784 } 785 786 787 static dma_addr_t 788 ccio_map_page(struct device *dev, struct page *page, unsigned long offset, 789 size_t size, enum dma_data_direction direction, 790 unsigned long attrs) 791 { 792 return ccio_map_single(dev, page_address(page) + offset, size, 793 direction); 794 } 795 796 797 /** 798 * ccio_unmap_page - Unmap an address range from the IOMMU. 799 * @dev: The PCI device. 800 * @addr: The start address of the DMA region. 801 * @size: The length of the DMA region. 802 * @direction: The direction of the DMA transaction (to/from device). 803 */ 804 static void 805 ccio_unmap_page(struct device *dev, dma_addr_t iova, size_t size, 806 enum dma_data_direction direction, unsigned long attrs) 807 { 808 struct ioc *ioc; 809 unsigned long flags; 810 dma_addr_t offset = iova & ~IOVP_MASK; 811 812 BUG_ON(!dev); 813 ioc = GET_IOC(dev); 814 if (!ioc) { 815 WARN_ON(!ioc); 816 return; 817 } 818 819 DBG_RUN("%s() iovp 0x%lx/%x\n", 820 __func__, (long)iova, size); 821 822 iova ^= offset; /* clear offset bits */ 823 size += offset; 824 size = ALIGN(size, IOVP_SIZE); 825 826 spin_lock_irqsave(&ioc->res_lock, flags); 827 828 #ifdef CCIO_COLLECT_STATS 829 ioc->usingle_calls++; 830 ioc->usingle_pages += size >> IOVP_SHIFT; 831 #endif 832 833 ccio_mark_invalid(ioc, iova, size); 834 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT)); 835 spin_unlock_irqrestore(&ioc->res_lock, flags); 836 } 837 838 /** 839 * ccio_alloc - Allocate a consistent DMA mapping. 840 * @dev: The PCI device. 841 * @size: The length of the DMA region. 842 * @dma_handle: The DMA address handed back to the device (not the cpu). 843 * 844 * This function implements the pci_alloc_consistent function. 845 */ 846 static void * 847 ccio_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag, 848 unsigned long attrs) 849 { 850 void *ret; 851 #if 0 852 /* GRANT Need to establish hierarchy for non-PCI devs as well 853 ** and then provide matching gsc_map_xxx() functions for them as well. 854 */ 855 if(!hwdev) { 856 /* only support PCI */ 857 *dma_handle = 0; 858 return 0; 859 } 860 #endif 861 ret = (void *) __get_free_pages(flag, get_order(size)); 862 863 if (ret) { 864 memset(ret, 0, size); 865 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL); 866 } 867 868 return ret; 869 } 870 871 /** 872 * ccio_free - Free a consistent DMA mapping. 873 * @dev: The PCI device. 874 * @size: The length of the DMA region. 875 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent. 876 * @dma_handle: The device address returned from the ccio_alloc_consistent. 877 * 878 * This function implements the pci_free_consistent function. 879 */ 880 static void 881 ccio_free(struct device *dev, size_t size, void *cpu_addr, 882 dma_addr_t dma_handle, unsigned long attrs) 883 { 884 ccio_unmap_page(dev, dma_handle, size, 0, 0); 885 free_pages((unsigned long)cpu_addr, get_order(size)); 886 } 887 888 /* 889 ** Since 0 is a valid pdir_base index value, can't use that 890 ** to determine if a value is valid or not. Use a flag to indicate 891 ** the SG list entry contains a valid pdir index. 892 */ 893 #define PIDE_FLAG 0x80000000UL 894 895 #ifdef CCIO_COLLECT_STATS 896 #define IOMMU_MAP_STATS 897 #endif 898 #include "iommu-helpers.h" 899 900 /** 901 * ccio_map_sg - Map the scatter/gather list into the IOMMU. 902 * @dev: The PCI device. 903 * @sglist: The scatter/gather list to be mapped in the IOMMU. 904 * @nents: The number of entries in the scatter/gather list. 905 * @direction: The direction of the DMA transaction (to/from device). 906 * 907 * This function implements the pci_map_sg function. 908 */ 909 static int 910 ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 911 enum dma_data_direction direction, unsigned long attrs) 912 { 913 struct ioc *ioc; 914 int coalesced, filled = 0; 915 unsigned long flags; 916 unsigned long hint = hint_lookup[(int)direction]; 917 unsigned long prev_len = 0, current_len = 0; 918 int i; 919 920 BUG_ON(!dev); 921 ioc = GET_IOC(dev); 922 if (!ioc) 923 return 0; 924 925 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 926 927 /* Fast path single entry scatterlists. */ 928 if (nents == 1) { 929 sg_dma_address(sglist) = ccio_map_single(dev, 930 sg_virt(sglist), sglist->length, 931 direction); 932 sg_dma_len(sglist) = sglist->length; 933 return 1; 934 } 935 936 for(i = 0; i < nents; i++) 937 prev_len += sglist[i].length; 938 939 spin_lock_irqsave(&ioc->res_lock, flags); 940 941 #ifdef CCIO_COLLECT_STATS 942 ioc->msg_calls++; 943 #endif 944 945 /* 946 ** First coalesce the chunks and allocate I/O pdir space 947 ** 948 ** If this is one DMA stream, we can properly map using the 949 ** correct virtual address associated with each DMA page. 950 ** w/o this association, we wouldn't have coherent DMA! 951 ** Access to the virtual address is what forces a two pass algorithm. 952 */ 953 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range); 954 955 /* 956 ** Program the I/O Pdir 957 ** 958 ** map the virtual addresses to the I/O Pdir 959 ** o dma_address will contain the pdir index 960 ** o dma_len will contain the number of bytes to map 961 ** o page/offset contain the virtual address. 962 */ 963 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry); 964 965 spin_unlock_irqrestore(&ioc->res_lock, flags); 966 967 BUG_ON(coalesced != filled); 968 969 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 970 971 for (i = 0; i < filled; i++) 972 current_len += sg_dma_len(sglist + i); 973 974 BUG_ON(current_len != prev_len); 975 976 return filled; 977 } 978 979 /** 980 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU. 981 * @dev: The PCI device. 982 * @sglist: The scatter/gather list to be unmapped from the IOMMU. 983 * @nents: The number of entries in the scatter/gather list. 984 * @direction: The direction of the DMA transaction (to/from device). 985 * 986 * This function implements the pci_unmap_sg function. 987 */ 988 static void 989 ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 990 enum dma_data_direction direction, unsigned long attrs) 991 { 992 struct ioc *ioc; 993 994 BUG_ON(!dev); 995 ioc = GET_IOC(dev); 996 if (!ioc) { 997 WARN_ON(!ioc); 998 return; 999 } 1000 1001 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1002 __func__, nents, sg_virt(sglist), sglist->length); 1003 1004 #ifdef CCIO_COLLECT_STATS 1005 ioc->usg_calls++; 1006 #endif 1007 1008 while(sg_dma_len(sglist) && nents--) { 1009 1010 #ifdef CCIO_COLLECT_STATS 1011 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; 1012 #endif 1013 ccio_unmap_page(dev, sg_dma_address(sglist), 1014 sg_dma_len(sglist), direction, 0); 1015 ++sglist; 1016 } 1017 1018 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1019 } 1020 1021 static const struct dma_map_ops ccio_ops = { 1022 .dma_supported = ccio_dma_supported, 1023 .alloc = ccio_alloc, 1024 .free = ccio_free, 1025 .map_page = ccio_map_page, 1026 .unmap_page = ccio_unmap_page, 1027 .map_sg = ccio_map_sg, 1028 .unmap_sg = ccio_unmap_sg, 1029 }; 1030 1031 #ifdef CONFIG_PROC_FS 1032 static int ccio_proc_info(struct seq_file *m, void *p) 1033 { 1034 struct ioc *ioc = ioc_list; 1035 1036 while (ioc != NULL) { 1037 unsigned int total_pages = ioc->res_size << 3; 1038 #ifdef CCIO_COLLECT_STATS 1039 unsigned long avg = 0, min, max; 1040 int j; 1041 #endif 1042 1043 seq_printf(m, "%s\n", ioc->name); 1044 1045 seq_printf(m, "Cujo 2.0 bug : %s\n", 1046 (ioc->cujo20_bug ? "yes" : "no")); 1047 1048 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1049 total_pages * 8, total_pages); 1050 1051 #ifdef CCIO_COLLECT_STATS 1052 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1053 total_pages - ioc->used_pages, ioc->used_pages, 1054 (int)(ioc->used_pages * 100 / total_pages)); 1055 #endif 1056 1057 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1058 ioc->res_size, total_pages); 1059 1060 #ifdef CCIO_COLLECT_STATS 1061 min = max = ioc->avg_search[0]; 1062 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) { 1063 avg += ioc->avg_search[j]; 1064 if(ioc->avg_search[j] > max) 1065 max = ioc->avg_search[j]; 1066 if(ioc->avg_search[j] < min) 1067 min = ioc->avg_search[j]; 1068 } 1069 avg /= CCIO_SEARCH_SAMPLE; 1070 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1071 min, avg, max); 1072 1073 seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", 1074 ioc->msingle_calls, ioc->msingle_pages, 1075 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1076 1077 /* KLUGE - unmap_sg calls unmap_page for each mapped page */ 1078 min = ioc->usingle_calls - ioc->usg_calls; 1079 max = ioc->usingle_pages - ioc->usg_pages; 1080 seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", 1081 min, max, (int)((max * 1000)/min)); 1082 1083 seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", 1084 ioc->msg_calls, ioc->msg_pages, 1085 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1086 1087 seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", 1088 ioc->usg_calls, ioc->usg_pages, 1089 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1090 #endif /* CCIO_COLLECT_STATS */ 1091 1092 ioc = ioc->next; 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int ccio_proc_bitmap_info(struct seq_file *m, void *p) 1099 { 1100 struct ioc *ioc = ioc_list; 1101 1102 while (ioc != NULL) { 1103 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, 1104 ioc->res_size, false); 1105 seq_putc(m, '\n'); 1106 ioc = ioc->next; 1107 break; /* XXX - remove me */ 1108 } 1109 1110 return 0; 1111 } 1112 #endif /* CONFIG_PROC_FS */ 1113 1114 /** 1115 * ccio_find_ioc - Find the ioc in the ioc_list 1116 * @hw_path: The hardware path of the ioc. 1117 * 1118 * This function searches the ioc_list for an ioc that matches 1119 * the provide hardware path. 1120 */ 1121 static struct ioc * ccio_find_ioc(int hw_path) 1122 { 1123 int i; 1124 struct ioc *ioc; 1125 1126 ioc = ioc_list; 1127 for (i = 0; i < ioc_count; i++) { 1128 if (ioc->hw_path == hw_path) 1129 return ioc; 1130 1131 ioc = ioc->next; 1132 } 1133 1134 return NULL; 1135 } 1136 1137 /** 1138 * ccio_get_iommu - Find the iommu which controls this device 1139 * @dev: The parisc device. 1140 * 1141 * This function searches through the registered IOMMU's and returns 1142 * the appropriate IOMMU for the device based on its hardware path. 1143 */ 1144 void * ccio_get_iommu(const struct parisc_device *dev) 1145 { 1146 dev = find_pa_parent_type(dev, HPHW_IOA); 1147 if (!dev) 1148 return NULL; 1149 1150 return ccio_find_ioc(dev->hw_path); 1151 } 1152 1153 #define CUJO_20_STEP 0x10000000 /* inc upper nibble */ 1154 1155 /* Cujo 2.0 has a bug which will silently corrupt data being transferred 1156 * to/from certain pages. To avoid this happening, we mark these pages 1157 * as `used', and ensure that nothing will try to allocate from them. 1158 */ 1159 void __init ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp) 1160 { 1161 unsigned int idx; 1162 struct parisc_device *dev = parisc_parent(cujo); 1163 struct ioc *ioc = ccio_get_iommu(dev); 1164 u8 *res_ptr; 1165 1166 ioc->cujo20_bug = 1; 1167 res_ptr = ioc->res_map; 1168 idx = PDIR_INDEX(iovp) >> 3; 1169 1170 while (idx < ioc->res_size) { 1171 res_ptr[idx] |= 0xff; 1172 idx += PDIR_INDEX(CUJO_20_STEP) >> 3; 1173 } 1174 } 1175 1176 #if 0 1177 /* GRANT - is this needed for U2 or not? */ 1178 1179 /* 1180 ** Get the size of the I/O TLB for this I/O MMU. 1181 ** 1182 ** If spa_shift is non-zero (ie probably U2), 1183 ** then calculate the I/O TLB size using spa_shift. 1184 ** 1185 ** Otherwise we are supposed to get the IODC entry point ENTRY TLB 1186 ** and execute it. However, both U2 and Uturn firmware supplies spa_shift. 1187 ** I think only Java (K/D/R-class too?) systems don't do this. 1188 */ 1189 static int 1190 ccio_get_iotlb_size(struct parisc_device *dev) 1191 { 1192 if (dev->spa_shift == 0) { 1193 panic("%s() : Can't determine I/O TLB size.\n", __func__); 1194 } 1195 return (1 << dev->spa_shift); 1196 } 1197 #else 1198 1199 /* Uturn supports 256 TLB entries */ 1200 #define CCIO_CHAINID_SHIFT 8 1201 #define CCIO_CHAINID_MASK 0xff 1202 #endif /* 0 */ 1203 1204 /* We *can't* support JAVA (T600). Venture there at your own risk. */ 1205 static const struct parisc_device_id ccio_tbl[] __initconst = { 1206 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */ 1207 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */ 1208 { 0, } 1209 }; 1210 1211 static int ccio_probe(struct parisc_device *dev); 1212 1213 static struct parisc_driver ccio_driver __refdata = { 1214 .name = "ccio", 1215 .id_table = ccio_tbl, 1216 .probe = ccio_probe, 1217 }; 1218 1219 /** 1220 * ccio_ioc_init - Initialize the I/O Controller 1221 * @ioc: The I/O Controller. 1222 * 1223 * Initialize the I/O Controller which includes setting up the 1224 * I/O Page Directory, the resource map, and initalizing the 1225 * U2/Uturn chip into virtual mode. 1226 */ 1227 static void __init 1228 ccio_ioc_init(struct ioc *ioc) 1229 { 1230 int i; 1231 unsigned int iov_order; 1232 u32 iova_space_size; 1233 1234 /* 1235 ** Determine IOVA Space size from memory size. 1236 ** 1237 ** Ideally, PCI drivers would register the maximum number 1238 ** of DMA they can have outstanding for each device they 1239 ** own. Next best thing would be to guess how much DMA 1240 ** can be outstanding based on PCI Class/sub-class. Both 1241 ** methods still require some "extra" to support PCI 1242 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1243 */ 1244 1245 iova_space_size = (u32) (totalram_pages() / count_parisc_driver(&ccio_driver)); 1246 1247 /* limit IOVA space size to 1MB-1GB */ 1248 1249 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1250 iova_space_size = 1 << (20 - PAGE_SHIFT); 1251 #ifdef __LP64__ 1252 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1253 iova_space_size = 1 << (30 - PAGE_SHIFT); 1254 #endif 1255 } 1256 1257 /* 1258 ** iova space must be log2() in size. 1259 ** thus, pdir/res_map will also be log2(). 1260 */ 1261 1262 /* We could use larger page sizes in order to *decrease* the number 1263 ** of mappings needed. (ie 8k pages means 1/2 the mappings). 1264 ** 1265 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either 1266 ** since the pages must also be physically contiguous - typically 1267 ** this is the case under linux." 1268 */ 1269 1270 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1271 1272 /* iova_space_size is now bytes, not pages */ 1273 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1274 1275 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1276 1277 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ 1278 1279 /* Verify it's a power of two */ 1280 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); 1281 1282 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", 1283 __func__, ioc->ioc_regs, 1284 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), 1285 iova_space_size>>20, 1286 iov_order + PAGE_SHIFT); 1287 1288 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, 1289 get_order(ioc->pdir_size)); 1290 if(NULL == ioc->pdir_base) { 1291 panic("%s() could not allocate I/O Page Table\n", __func__); 1292 } 1293 memset(ioc->pdir_base, 0, ioc->pdir_size); 1294 1295 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); 1296 DBG_INIT(" base %p\n", ioc->pdir_base); 1297 1298 /* resource map size dictated by pdir_size */ 1299 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; 1300 DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); 1301 1302 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, 1303 get_order(ioc->res_size)); 1304 if(NULL == ioc->res_map) { 1305 panic("%s() could not allocate resource map\n", __func__); 1306 } 1307 memset(ioc->res_map, 0, ioc->res_size); 1308 1309 /* Initialize the res_hint to 16 */ 1310 ioc->res_hint = 16; 1311 1312 /* Initialize the spinlock */ 1313 spin_lock_init(&ioc->res_lock); 1314 1315 /* 1316 ** Chainid is the upper most bits of an IOVP used to determine 1317 ** which TLB entry an IOVP will use. 1318 */ 1319 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; 1320 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); 1321 1322 /* 1323 ** Initialize IOA hardware 1324 */ 1325 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, 1326 &ioc->ioc_regs->io_chain_id_mask); 1327 1328 WRITE_U32(virt_to_phys(ioc->pdir_base), 1329 &ioc->ioc_regs->io_pdir_base); 1330 1331 /* 1332 ** Go to "Virtual Mode" 1333 */ 1334 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); 1335 1336 /* 1337 ** Initialize all I/O TLB entries to 0 (Valid bit off). 1338 */ 1339 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); 1340 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); 1341 1342 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { 1343 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), 1344 &ioc->ioc_regs->io_command); 1345 } 1346 } 1347 1348 static void __init 1349 ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) 1350 { 1351 int result; 1352 1353 res->parent = NULL; 1354 res->flags = IORESOURCE_MEM; 1355 /* 1356 * bracing ((signed) ...) are required for 64bit kernel because 1357 * we only want to sign extend the lower 16 bits of the register. 1358 * The upper 16-bits of range registers are hardcoded to 0xffff. 1359 */ 1360 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); 1361 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); 1362 res->name = name; 1363 /* 1364 * Check if this MMIO range is disable 1365 */ 1366 if (res->end + 1 == res->start) 1367 return; 1368 1369 /* On some platforms (e.g. K-Class), we have already registered 1370 * resources for devices reported by firmware. Some are children 1371 * of ccio. 1372 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem). 1373 */ 1374 result = insert_resource(&iomem_resource, res); 1375 if (result < 0) { 1376 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n", 1377 __func__, (unsigned long)res->start, (unsigned long)res->end); 1378 } 1379 } 1380 1381 static void __init ccio_init_resources(struct ioc *ioc) 1382 { 1383 struct resource *res = ioc->mmio_region; 1384 char *name = kmalloc(14, GFP_KERNEL); 1385 1386 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); 1387 1388 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); 1389 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); 1390 } 1391 1392 static int new_ioc_area(struct resource *res, unsigned long size, 1393 unsigned long min, unsigned long max, unsigned long align) 1394 { 1395 if (max <= min) 1396 return -EBUSY; 1397 1398 res->start = (max - size + 1) &~ (align - 1); 1399 res->end = res->start + size; 1400 1401 /* We might be trying to expand the MMIO range to include 1402 * a child device that has already registered it's MMIO space. 1403 * Use "insert" instead of request_resource(). 1404 */ 1405 if (!insert_resource(&iomem_resource, res)) 1406 return 0; 1407 1408 return new_ioc_area(res, size, min, max - size, align); 1409 } 1410 1411 static int expand_ioc_area(struct resource *res, unsigned long size, 1412 unsigned long min, unsigned long max, unsigned long align) 1413 { 1414 unsigned long start, len; 1415 1416 if (!res->parent) 1417 return new_ioc_area(res, size, min, max, align); 1418 1419 start = (res->start - size) &~ (align - 1); 1420 len = res->end - start + 1; 1421 if (start >= min) { 1422 if (!adjust_resource(res, start, len)) 1423 return 0; 1424 } 1425 1426 start = res->start; 1427 len = ((size + res->end + align) &~ (align - 1)) - start; 1428 if (start + len <= max) { 1429 if (!adjust_resource(res, start, len)) 1430 return 0; 1431 } 1432 1433 return -EBUSY; 1434 } 1435 1436 /* 1437 * Dino calls this function. Beware that we may get called on systems 1438 * which have no IOC (725, B180, C160L, etc) but do have a Dino. 1439 * So it's legal to find no parent IOC. 1440 * 1441 * Some other issues: one of the resources in the ioc may be unassigned. 1442 */ 1443 int ccio_allocate_resource(const struct parisc_device *dev, 1444 struct resource *res, unsigned long size, 1445 unsigned long min, unsigned long max, unsigned long align) 1446 { 1447 struct resource *parent = &iomem_resource; 1448 struct ioc *ioc = ccio_get_iommu(dev); 1449 if (!ioc) 1450 goto out; 1451 1452 parent = ioc->mmio_region; 1453 if (parent->parent && 1454 !allocate_resource(parent, res, size, min, max, align, NULL, NULL)) 1455 return 0; 1456 1457 if ((parent + 1)->parent && 1458 !allocate_resource(parent + 1, res, size, min, max, align, 1459 NULL, NULL)) 1460 return 0; 1461 1462 if (!expand_ioc_area(parent, size, min, max, align)) { 1463 __raw_writel(((parent->start)>>16) | 0xffff0000, 1464 &ioc->ioc_regs->io_io_low); 1465 __raw_writel(((parent->end)>>16) | 0xffff0000, 1466 &ioc->ioc_regs->io_io_high); 1467 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) { 1468 parent++; 1469 __raw_writel(((parent->start)>>16) | 0xffff0000, 1470 &ioc->ioc_regs->io_io_low_hv); 1471 __raw_writel(((parent->end)>>16) | 0xffff0000, 1472 &ioc->ioc_regs->io_io_high_hv); 1473 } else { 1474 return -EBUSY; 1475 } 1476 1477 out: 1478 return allocate_resource(parent, res, size, min, max, align, NULL,NULL); 1479 } 1480 1481 int ccio_request_resource(const struct parisc_device *dev, 1482 struct resource *res) 1483 { 1484 struct resource *parent; 1485 struct ioc *ioc = ccio_get_iommu(dev); 1486 1487 if (!ioc) { 1488 parent = &iomem_resource; 1489 } else if ((ioc->mmio_region->start <= res->start) && 1490 (res->end <= ioc->mmio_region->end)) { 1491 parent = ioc->mmio_region; 1492 } else if (((ioc->mmio_region + 1)->start <= res->start) && 1493 (res->end <= (ioc->mmio_region + 1)->end)) { 1494 parent = ioc->mmio_region + 1; 1495 } else { 1496 return -EBUSY; 1497 } 1498 1499 /* "transparent" bus bridges need to register MMIO resources 1500 * firmware assigned them. e.g. children of hppb.c (e.g. K-class) 1501 * registered their resources in the PDC "bus walk" (See 1502 * arch/parisc/kernel/inventory.c). 1503 */ 1504 return insert_resource(parent, res); 1505 } 1506 1507 /** 1508 * ccio_probe - Determine if ccio should claim this device. 1509 * @dev: The device which has been found 1510 * 1511 * Determine if ccio should claim this chip (return 0) or not (return 1). 1512 * If so, initialize the chip and tell other partners in crime they 1513 * have work to do. 1514 */ 1515 static int __init ccio_probe(struct parisc_device *dev) 1516 { 1517 int i; 1518 struct ioc *ioc, **ioc_p = &ioc_list; 1519 struct pci_hba_data *hba; 1520 1521 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); 1522 if (ioc == NULL) { 1523 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); 1524 return -ENOMEM; 1525 } 1526 1527 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; 1528 1529 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, 1530 (unsigned long)dev->hpa.start); 1531 1532 for (i = 0; i < ioc_count; i++) { 1533 ioc_p = &(*ioc_p)->next; 1534 } 1535 *ioc_p = ioc; 1536 1537 ioc->hw_path = dev->hw_path; 1538 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); 1539 if (!ioc->ioc_regs) { 1540 kfree(ioc); 1541 return -ENOMEM; 1542 } 1543 ccio_ioc_init(ioc); 1544 ccio_init_resources(ioc); 1545 hppa_dma_ops = &ccio_ops; 1546 1547 hba = kzalloc(sizeof(*hba), GFP_KERNEL); 1548 /* if this fails, no I/O cards will work, so may as well bug */ 1549 BUG_ON(hba == NULL); 1550 1551 hba->iommu = ioc; 1552 dev->dev.platform_data = hba; 1553 1554 #ifdef CONFIG_PROC_FS 1555 if (ioc_count == 0) { 1556 proc_create_single(MODULE_NAME, 0, proc_runway_root, 1557 ccio_proc_info); 1558 proc_create_single(MODULE_NAME"-bitmap", 0, proc_runway_root, 1559 ccio_proc_bitmap_info); 1560 } 1561 #endif 1562 ioc_count++; 1563 return 0; 1564 } 1565 1566 /** 1567 * ccio_init - ccio initialization procedure. 1568 * 1569 * Register this driver. 1570 */ 1571 void __init ccio_init(void) 1572 { 1573 register_parisc_driver(&ccio_driver); 1574 } 1575 1576