1 /* 2 ** ccio-dma.c: 3 ** DMA management routines for first generation cache-coherent machines. 4 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. 5 ** 6 ** (c) Copyright 2000 Grant Grundler 7 ** (c) Copyright 2000 Ryan Bradetich 8 ** (c) Copyright 2000 Hewlett-Packard Company 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** "Real Mode" operation refers to U2/Uturn chip operation. 17 ** U2/Uturn were designed to perform coherency checks w/o using 18 ** the I/O MMU - basically what x86 does. 19 ** 20 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: 21 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc 22 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c 23 ** 24 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. 25 ** 26 ** Drawbacks of using Real Mode are: 27 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal). 28 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute. 29 ** o Ability to do scatter/gather in HW is lost. 30 ** o Doesn't work under PCX-U/U+ machines since they didn't follow 31 ** the coherency design originally worked out. Only PCX-W does. 32 */ 33 34 #include <linux/types.h> 35 #include <linux/kernel.h> 36 #include <linux/init.h> 37 #include <linux/mm.h> 38 #include <linux/spinlock.h> 39 #include <linux/slab.h> 40 #include <linux/string.h> 41 #include <linux/pci.h> 42 #include <linux/reboot.h> 43 #include <linux/proc_fs.h> 44 #include <linux/seq_file.h> 45 #include <linux/scatterlist.h> 46 #include <linux/iommu-helper.h> 47 48 #include <asm/byteorder.h> 49 #include <asm/cache.h> /* for L1_CACHE_BYTES */ 50 #include <asm/uaccess.h> 51 #include <asm/page.h> 52 #include <asm/dma.h> 53 #include <asm/io.h> 54 #include <asm/hardware.h> /* for register_module() */ 55 #include <asm/parisc-device.h> 56 57 /* 58 ** Choose "ccio" since that's what HP-UX calls it. 59 ** Make it easier for folks to migrate from one to the other :^) 60 */ 61 #define MODULE_NAME "ccio" 62 63 #undef DEBUG_CCIO_RES 64 #undef DEBUG_CCIO_RUN 65 #undef DEBUG_CCIO_INIT 66 #undef DEBUG_CCIO_RUN_SG 67 68 #ifdef CONFIG_PROC_FS 69 /* depends on proc fs support. But costs CPU performance. */ 70 #undef CCIO_COLLECT_STATS 71 #endif 72 73 #include <asm/runway.h> /* for proc_runway_root */ 74 75 #ifdef DEBUG_CCIO_INIT 76 #define DBG_INIT(x...) printk(x) 77 #else 78 #define DBG_INIT(x...) 79 #endif 80 81 #ifdef DEBUG_CCIO_RUN 82 #define DBG_RUN(x...) printk(x) 83 #else 84 #define DBG_RUN(x...) 85 #endif 86 87 #ifdef DEBUG_CCIO_RES 88 #define DBG_RES(x...) printk(x) 89 #else 90 #define DBG_RES(x...) 91 #endif 92 93 #ifdef DEBUG_CCIO_RUN_SG 94 #define DBG_RUN_SG(x...) printk(x) 95 #else 96 #define DBG_RUN_SG(x...) 97 #endif 98 99 #define CCIO_INLINE inline 100 #define WRITE_U32(value, addr) __raw_writel(value, addr) 101 #define READ_U32(addr) __raw_readl(addr) 102 103 #define U2_IOA_RUNWAY 0x580 104 #define U2_BC_GSC 0x501 105 #define UTURN_IOA_RUNWAY 0x581 106 #define UTURN_BC_GSC 0x502 107 108 #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */ 109 #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */ 110 #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */ 111 112 struct ioa_registers { 113 /* Runway Supervisory Set */ 114 int32_t unused1[12]; 115 uint32_t io_command; /* Offset 12 */ 116 uint32_t io_status; /* Offset 13 */ 117 uint32_t io_control; /* Offset 14 */ 118 int32_t unused2[1]; 119 120 /* Runway Auxiliary Register Set */ 121 uint32_t io_err_resp; /* Offset 0 */ 122 uint32_t io_err_info; /* Offset 1 */ 123 uint32_t io_err_req; /* Offset 2 */ 124 uint32_t io_err_resp_hi; /* Offset 3 */ 125 uint32_t io_tlb_entry_m; /* Offset 4 */ 126 uint32_t io_tlb_entry_l; /* Offset 5 */ 127 uint32_t unused3[1]; 128 uint32_t io_pdir_base; /* Offset 7 */ 129 uint32_t io_io_low_hv; /* Offset 8 */ 130 uint32_t io_io_high_hv; /* Offset 9 */ 131 uint32_t unused4[1]; 132 uint32_t io_chain_id_mask; /* Offset 11 */ 133 uint32_t unused5[2]; 134 uint32_t io_io_low; /* Offset 14 */ 135 uint32_t io_io_high; /* Offset 15 */ 136 }; 137 138 /* 139 ** IOA Registers 140 ** ------------- 141 ** 142 ** Runway IO_CONTROL Register (+0x38) 143 ** 144 ** The Runway IO_CONTROL register controls the forwarding of transactions. 145 ** 146 ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 | 147 ** | HV | TLB | reserved | HV | mode | reserved | 148 ** 149 ** o mode field indicates the address translation of transactions 150 ** forwarded from Runway to GSC+: 151 ** Mode Name Value Definition 152 ** Off (default) 0 Opaque to matching addresses. 153 ** Include 1 Transparent for matching addresses. 154 ** Peek 3 Map matching addresses. 155 ** 156 ** + "Off" mode: Runway transactions which match the I/O range 157 ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored. 158 ** + "Include" mode: all addresses within the I/O range specified 159 ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently 160 ** forwarded. This is the I/O Adapter's normal operating mode. 161 ** + "Peek" mode: used during system configuration to initialize the 162 ** GSC+ bus. Runway Write_Shorts in the address range specified by 163 ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter 164 ** *AND* the GSC+ address is remapped to the Broadcast Physical 165 ** Address space by setting the 14 high order address bits of the 166 ** 32 bit GSC+ address to ones. 167 ** 168 ** o TLB field affects transactions which are forwarded from GSC+ to Runway. 169 ** "Real" mode is the poweron default. 170 ** 171 ** TLB Mode Value Description 172 ** Real 0 No TLB translation. Address is directly mapped and the 173 ** virtual address is composed of selected physical bits. 174 ** Error 1 Software fills the TLB manually. 175 ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory). 176 ** 177 ** 178 ** IO_IO_LOW_HV +0x60 (HV dependent) 179 ** IO_IO_HIGH_HV +0x64 (HV dependent) 180 ** IO_IO_LOW +0x78 (Architected register) 181 ** IO_IO_HIGH +0x7c (Architected register) 182 ** 183 ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the 184 ** I/O Adapter address space, respectively. 185 ** 186 ** 0 ... 7 | 8 ... 15 | 16 ... 31 | 187 ** 11111111 | 11111111 | address | 188 ** 189 ** Each LOW/HIGH pair describes a disjoint address space region. 190 ** (2 per GSC+ port). Each incoming Runway transaction address is compared 191 ** with both sets of LOW/HIGH registers. If the address is in the range 192 ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction 193 ** for forwarded to the respective GSC+ bus. 194 ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying 195 ** an address space region. 196 ** 197 ** In order for a Runway address to reside within GSC+ extended address space: 198 ** Runway Address [0:7] must identically compare to 8'b11111111 199 ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19] 200 ** Runway Address [12:23] must be greater than or equal to 201 ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31]. 202 ** Runway Address [24:39] is not used in the comparison. 203 ** 204 ** When the Runway transaction is forwarded to GSC+, the GSC+ address is 205 ** as follows: 206 ** GSC+ Address[0:3] 4'b1111 207 ** GSC+ Address[4:29] Runway Address[12:37] 208 ** GSC+ Address[30:31] 2'b00 209 ** 210 ** All 4 Low/High registers must be initialized (by PDC) once the lower bus 211 ** is interrogated and address space is defined. The operating system will 212 ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following 213 ** the PDC initialization. However, the hardware version dependent IO_IO_LOW 214 ** and IO_IO_HIGH registers should not be subsequently altered by the OS. 215 ** 216 ** Writes to both sets of registers will take effect immediately, bypassing 217 ** the queues, which ensures that subsequent Runway transactions are checked 218 ** against the updated bounds values. However reads are queued, introducing 219 ** the possibility of a read being bypassed by a subsequent write to the same 220 ** register. This sequence can be avoided by having software wait for read 221 ** returns before issuing subsequent writes. 222 */ 223 224 struct ioc { 225 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */ 226 u8 *res_map; /* resource map, bit == pdir entry */ 227 u64 *pdir_base; /* physical base address */ 228 u32 pdir_size; /* bytes, function of IOV Space size */ 229 u32 res_hint; /* next available IOVP - 230 circular search */ 231 u32 res_size; /* size of resource map in bytes */ 232 spinlock_t res_lock; 233 234 #ifdef CCIO_COLLECT_STATS 235 #define CCIO_SEARCH_SAMPLE 0x100 236 unsigned long avg_search[CCIO_SEARCH_SAMPLE]; 237 unsigned long avg_idx; /* current index into avg_search */ 238 unsigned long used_pages; 239 unsigned long msingle_calls; 240 unsigned long msingle_pages; 241 unsigned long msg_calls; 242 unsigned long msg_pages; 243 unsigned long usingle_calls; 244 unsigned long usingle_pages; 245 unsigned long usg_calls; 246 unsigned long usg_pages; 247 #endif 248 unsigned short cujo20_bug; 249 250 /* STUFF We don't need in performance path */ 251 u32 chainid_shift; /* specify bit location of chain_id */ 252 struct ioc *next; /* Linked list of discovered iocs */ 253 const char *name; /* device name from firmware */ 254 unsigned int hw_path; /* the hardware path this ioc is associatd with */ 255 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */ 256 struct resource mmio_region[2]; /* The "routed" MMIO regions */ 257 }; 258 259 static struct ioc *ioc_list; 260 static int ioc_count; 261 262 /************************************************************** 263 * 264 * I/O Pdir Resource Management 265 * 266 * Bits set in the resource map are in use. 267 * Each bit can represent a number of pages. 268 * LSbs represent lower addresses (IOVA's). 269 * 270 * This was was copied from sba_iommu.c. Don't try to unify 271 * the two resource managers unless a way to have different 272 * allocation policies is also adjusted. We'd like to avoid 273 * I/O TLB thrashing by having resource allocation policy 274 * match the I/O TLB replacement policy. 275 * 276 ***************************************************************/ 277 #define IOVP_SIZE PAGE_SIZE 278 #define IOVP_SHIFT PAGE_SHIFT 279 #define IOVP_MASK PAGE_MASK 280 281 /* Convert from IOVP to IOVA and vice versa. */ 282 #define CCIO_IOVA(iovp,offset) ((iovp) | (offset)) 283 #define CCIO_IOVP(iova) ((iova) & IOVP_MASK) 284 285 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 286 #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT) 287 #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset) 288 289 /* 290 ** Don't worry about the 150% average search length on a miss. 291 ** If the search wraps around, and passes the res_hint, it will 292 ** cause the kernel to panic anyhow. 293 */ 294 #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ 295 for(; res_ptr < res_end; ++res_ptr) { \ 296 int ret;\ 297 unsigned int idx;\ 298 idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \ 299 ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\ 300 if ((0 == (*res_ptr & mask)) && !ret) { \ 301 *res_ptr |= mask; \ 302 res_idx = idx;\ 303 ioc->res_hint = res_idx + (size >> 3); \ 304 goto resource_found; \ 305 } \ 306 } 307 308 #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ 309 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \ 310 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \ 311 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ 312 res_ptr = (u##size *)&(ioc)->res_map[0]; \ 313 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); 314 315 /* 316 ** Find available bit in this ioa's resource map. 317 ** Use a "circular" search: 318 ** o Most IOVA's are "temporary" - avg search time should be small. 319 ** o keep a history of what happened for debugging 320 ** o KISS. 321 ** 322 ** Perf optimizations: 323 ** o search for log2(size) bits at a time. 324 ** o search for available resource bits using byte/word/whatever. 325 ** o use different search for "large" (eg > 4 pages) or "very large" 326 ** (eg > 16 pages) mappings. 327 */ 328 329 /** 330 * ccio_alloc_range - Allocate pages in the ioc's resource map. 331 * @ioc: The I/O Controller. 332 * @pages_needed: The requested number of pages to be mapped into the 333 * I/O Pdir... 334 * 335 * This function searches the resource map of the ioc to locate a range 336 * of available pages for the requested size. 337 */ 338 static int 339 ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 340 { 341 unsigned int pages_needed = size >> IOVP_SHIFT; 342 unsigned int res_idx; 343 unsigned long boundary_size; 344 #ifdef CCIO_COLLECT_STATS 345 unsigned long cr_start = mfctl(16); 346 #endif 347 348 BUG_ON(pages_needed == 0); 349 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE); 350 351 DBG_RES("%s() size: %d pages_needed %d\n", 352 __func__, size, pages_needed); 353 354 /* 355 ** "seek and ye shall find"...praying never hurts either... 356 ** ggg sacrifices another 710 to the computer gods. 357 */ 358 359 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, 360 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; 361 362 if (pages_needed <= 8) { 363 /* 364 * LAN traffic will not thrash the TLB IFF the same NIC 365 * uses 8 adjacent pages to map separate payload data. 366 * ie the same byte in the resource bit map. 367 */ 368 #if 0 369 /* FIXME: bit search should shift it's way through 370 * an unsigned long - not byte at a time. As it is now, 371 * we effectively allocate this byte to this mapping. 372 */ 373 unsigned long mask = ~(~0UL >> pages_needed); 374 CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8); 375 #else 376 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8); 377 #endif 378 } else if (pages_needed <= 16) { 379 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16); 380 } else if (pages_needed <= 32) { 381 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32); 382 #ifdef __LP64__ 383 } else if (pages_needed <= 64) { 384 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64); 385 #endif 386 } else { 387 panic("%s: %s() Too many pages to map. pages_needed: %u\n", 388 __FILE__, __func__, pages_needed); 389 } 390 391 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__, 392 __func__); 393 394 resource_found: 395 396 DBG_RES("%s() res_idx %d res_hint: %d\n", 397 __func__, res_idx, ioc->res_hint); 398 399 #ifdef CCIO_COLLECT_STATS 400 { 401 unsigned long cr_end = mfctl(16); 402 unsigned long tmp = cr_end - cr_start; 403 /* check for roll over */ 404 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 405 } 406 ioc->avg_search[ioc->avg_idx++] = cr_start; 407 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; 408 ioc->used_pages += pages_needed; 409 #endif 410 /* 411 ** return the bit address. 412 */ 413 return res_idx << 3; 414 } 415 416 #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ 417 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \ 418 BUG_ON((*res_ptr & mask) != mask); \ 419 *res_ptr &= ~(mask); 420 421 /** 422 * ccio_free_range - Free pages from the ioc's resource map. 423 * @ioc: The I/O Controller. 424 * @iova: The I/O Virtual Address. 425 * @pages_mapped: The requested number of pages to be freed from the 426 * I/O Pdir. 427 * 428 * This function frees the resouces allocated for the iova. 429 */ 430 static void 431 ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped) 432 { 433 unsigned long iovp = CCIO_IOVP(iova); 434 unsigned int res_idx = PDIR_INDEX(iovp) >> 3; 435 436 BUG_ON(pages_mapped == 0); 437 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE); 438 BUG_ON(pages_mapped > BITS_PER_LONG); 439 440 DBG_RES("%s(): res_idx: %d pages_mapped %d\n", 441 __func__, res_idx, pages_mapped); 442 443 #ifdef CCIO_COLLECT_STATS 444 ioc->used_pages -= pages_mapped; 445 #endif 446 447 if(pages_mapped <= 8) { 448 #if 0 449 /* see matching comments in alloc_range */ 450 unsigned long mask = ~(~0UL >> pages_mapped); 451 CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8); 452 #else 453 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8); 454 #endif 455 } else if(pages_mapped <= 16) { 456 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16); 457 } else if(pages_mapped <= 32) { 458 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32); 459 #ifdef __LP64__ 460 } else if(pages_mapped <= 64) { 461 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64); 462 #endif 463 } else { 464 panic("%s:%s() Too many pages to unmap.\n", __FILE__, 465 __func__); 466 } 467 } 468 469 /**************************************************************** 470 ** 471 ** CCIO dma_ops support routines 472 ** 473 *****************************************************************/ 474 475 typedef unsigned long space_t; 476 #define KERNEL_SPACE 0 477 478 /* 479 ** DMA "Page Type" and Hints 480 ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be 481 ** set for subcacheline DMA transfers since we don't want to damage the 482 ** other part of a cacheline. 483 ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent(). 484 ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming" 485 ** data can avoid this if the mapping covers full cache lines. 486 ** o STOP_MOST is needed for atomicity across cachelines. 487 ** Apparently only "some EISA devices" need this. 488 ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs 489 ** to use this hint iff the EISA devices needs this feature. 490 ** According to the U2 ERS, STOP_MOST enabled pages hurt performance. 491 ** o PREFETCH should *not* be set for cases like Multiple PCI devices 492 ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC 493 ** device can be fetched and multiply DMA streams will thrash the 494 ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules 495 ** and Invalidation of Prefetch Entries". 496 ** 497 ** FIXME: the default hints need to be per GSC device - not global. 498 ** 499 ** HP-UX dorks: linux device driver programming model is totally different 500 ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers 501 ** do special things to work on non-coherent platforms...linux has to 502 ** be much more careful with this. 503 */ 504 #define IOPDIR_VALID 0x01UL 505 #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */ 506 #ifdef CONFIG_EISA 507 #define HINT_STOP_MOST 0x04UL /* LSL support */ 508 #else 509 #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */ 510 #endif 511 #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */ 512 #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */ 513 514 515 /* 516 ** Use direction (ie PCI_DMA_TODEVICE) to pick hint. 517 ** ccio_alloc_consistent() depends on this to get SAFE_DMA 518 ** when it passes in BIDIRECTIONAL flag. 519 */ 520 static u32 hint_lookup[] = { 521 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID, 522 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID, 523 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID, 524 }; 525 526 /** 527 * ccio_io_pdir_entry - Initialize an I/O Pdir. 528 * @pdir_ptr: A pointer into I/O Pdir. 529 * @sid: The Space Identifier. 530 * @vba: The virtual address. 531 * @hints: The DMA Hint. 532 * 533 * Given a virtual address (vba, arg2) and space id, (sid, arg1), 534 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir 535 * entry consists of 8 bytes as shown below (MSB == bit 0): 536 * 537 * 538 * WORD 0: 539 * +------+----------------+-----------------------------------------------+ 540 * | Phys | Virtual Index | Phys | 541 * | 0:3 | 0:11 | 4:19 | 542 * |4 bits| 12 bits | 16 bits | 543 * +------+----------------+-----------------------------------------------+ 544 * WORD 1: 545 * +-----------------------+-----------------------------------------------+ 546 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid | 547 * | 20:39 | | Enable |Enable | |Enable|DMA | | 548 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit | 549 * +-----------------------+-----------------------------------------------+ 550 * 551 * The virtual index field is filled with the results of the LCI 552 * (Load Coherence Index) instruction. The 8 bits used for the virtual 553 * index are bits 12:19 of the value returned by LCI. 554 */ 555 static void CCIO_INLINE 556 ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 557 unsigned long hints) 558 { 559 register unsigned long pa; 560 register unsigned long ci; /* coherent index */ 561 562 /* We currently only support kernel addresses */ 563 BUG_ON(sid != KERNEL_SPACE); 564 565 mtsp(sid,1); 566 567 /* 568 ** WORD 1 - low order word 569 ** "hints" parm includes the VALID bit! 570 ** "dep" clobbers the physical address offset bits as well. 571 */ 572 pa = virt_to_phys(vba); 573 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints)); 574 ((u32 *)pdir_ptr)[1] = (u32) pa; 575 576 /* 577 ** WORD 0 - high order word 578 */ 579 580 #ifdef __LP64__ 581 /* 582 ** get bits 12:15 of physical address 583 ** shift bits 16:31 of physical address 584 ** and deposit them 585 */ 586 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa)); 587 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa)); 588 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci)); 589 #else 590 pa = 0; 591 #endif 592 /* 593 ** get CPU coherency index bits 594 ** Grab virtual index [0:11] 595 ** Deposit virt_idx bits into I/O PDIR word 596 */ 597 asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 598 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci)); 599 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci)); 600 601 ((u32 *)pdir_ptr)[0] = (u32) pa; 602 603 604 /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) 605 ** PCX-U/U+ do. (eg C200/C240) 606 ** PCX-T'? Don't know. (eg C110 or similar K-class) 607 ** 608 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit". 609 ** Hopefully we can patch (NOP) these out at boot time somehow. 610 ** 611 ** "Since PCX-U employs an offset hash that is incompatible with 612 ** the real mode coherence index generation of U2, the PDIR entry 613 ** must be flushed to memory to retain coherence." 614 */ 615 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 616 asm volatile("sync"); 617 } 618 619 /** 620 * ccio_clear_io_tlb - Remove stale entries from the I/O TLB. 621 * @ioc: The I/O Controller. 622 * @iovp: The I/O Virtual Page. 623 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. 624 * 625 * Purge invalid I/O PDIR entries from the I/O TLB. 626 * 627 * FIXME: Can we change the byte_cnt to pages_mapped? 628 */ 629 static CCIO_INLINE void 630 ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt) 631 { 632 u32 chain_size = 1 << ioc->chainid_shift; 633 634 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */ 635 byte_cnt += chain_size; 636 637 while(byte_cnt > chain_size) { 638 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); 639 iovp += chain_size; 640 byte_cnt -= chain_size; 641 } 642 } 643 644 /** 645 * ccio_mark_invalid - Mark the I/O Pdir entries invalid. 646 * @ioc: The I/O Controller. 647 * @iova: The I/O Virtual Address. 648 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. 649 * 650 * Mark the I/O Pdir entries invalid and blow away the corresponding I/O 651 * TLB entries. 652 * 653 * FIXME: at some threshold it might be "cheaper" to just blow 654 * away the entire I/O TLB instead of individual entries. 655 * 656 * FIXME: Uturn has 256 TLB entries. We don't need to purge every 657 * PDIR entry - just once for each possible TLB entry. 658 * (We do need to maker I/O PDIR entries invalid regardless). 659 * 660 * FIXME: Can we change byte_cnt to pages_mapped? 661 */ 662 static CCIO_INLINE void 663 ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 664 { 665 u32 iovp = (u32)CCIO_IOVP(iova); 666 size_t saved_byte_cnt; 667 668 /* round up to nearest page size */ 669 saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE); 670 671 while(byte_cnt > 0) { 672 /* invalidate one page at a time */ 673 unsigned int idx = PDIR_INDEX(iovp); 674 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); 675 676 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); 677 pdir_ptr[7] = 0; /* clear only VALID bit */ 678 /* 679 ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) 680 ** PCX-U/U+ do. (eg C200/C240) 681 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit". 682 ** 683 ** Hopefully someone figures out how to patch (NOP) the 684 ** FDC/SYNC out at boot time. 685 */ 686 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7])); 687 688 iovp += IOVP_SIZE; 689 byte_cnt -= IOVP_SIZE; 690 } 691 692 asm volatile("sync"); 693 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt); 694 } 695 696 /**************************************************************** 697 ** 698 ** CCIO dma_ops 699 ** 700 *****************************************************************/ 701 702 /** 703 * ccio_dma_supported - Verify the IOMMU supports the DMA address range. 704 * @dev: The PCI device. 705 * @mask: A bit mask describing the DMA address range of the device. 706 * 707 * This function implements the pci_dma_supported function. 708 */ 709 static int 710 ccio_dma_supported(struct device *dev, u64 mask) 711 { 712 if(dev == NULL) { 713 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 714 BUG(); 715 return 0; 716 } 717 718 /* only support 32-bit devices (ie PCI/GSC) */ 719 return (int)(mask == 0xffffffffUL); 720 } 721 722 /** 723 * ccio_map_single - Map an address range into the IOMMU. 724 * @dev: The PCI device. 725 * @addr: The start address of the DMA region. 726 * @size: The length of the DMA region. 727 * @direction: The direction of the DMA transaction (to/from device). 728 * 729 * This function implements the pci_map_single function. 730 */ 731 static dma_addr_t 732 ccio_map_single(struct device *dev, void *addr, size_t size, 733 enum dma_data_direction direction) 734 { 735 int idx; 736 struct ioc *ioc; 737 unsigned long flags; 738 dma_addr_t iovp; 739 dma_addr_t offset; 740 u64 *pdir_start; 741 unsigned long hint = hint_lookup[(int)direction]; 742 743 BUG_ON(!dev); 744 ioc = GET_IOC(dev); 745 746 BUG_ON(size <= 0); 747 748 /* save offset bits */ 749 offset = ((unsigned long) addr) & ~IOVP_MASK; 750 751 /* round up to nearest IOVP_SIZE */ 752 size = ALIGN(size + offset, IOVP_SIZE); 753 spin_lock_irqsave(&ioc->res_lock, flags); 754 755 #ifdef CCIO_COLLECT_STATS 756 ioc->msingle_calls++; 757 ioc->msingle_pages += size >> IOVP_SHIFT; 758 #endif 759 760 idx = ccio_alloc_range(ioc, dev, size); 761 iovp = (dma_addr_t)MKIOVP(idx); 762 763 pdir_start = &(ioc->pdir_base[idx]); 764 765 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", 766 __func__, addr, (long)iovp | offset, size); 767 768 /* If not cacheline aligned, force SAFE_DMA on the whole mess */ 769 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES)) 770 hint |= HINT_SAFE_DMA; 771 772 while(size > 0) { 773 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint); 774 775 DBG_RUN(" pdir %p %08x%08x\n", 776 pdir_start, 777 (u32) (((u32 *) pdir_start)[0]), 778 (u32) (((u32 *) pdir_start)[1])); 779 ++pdir_start; 780 addr += IOVP_SIZE; 781 size -= IOVP_SIZE; 782 } 783 784 spin_unlock_irqrestore(&ioc->res_lock, flags); 785 786 /* form complete address */ 787 return CCIO_IOVA(iovp, offset); 788 } 789 790 /** 791 * ccio_unmap_single - Unmap an address range from the IOMMU. 792 * @dev: The PCI device. 793 * @addr: The start address of the DMA region. 794 * @size: The length of the DMA region. 795 * @direction: The direction of the DMA transaction (to/from device). 796 * 797 * This function implements the pci_unmap_single function. 798 */ 799 static void 800 ccio_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 801 enum dma_data_direction direction) 802 { 803 struct ioc *ioc; 804 unsigned long flags; 805 dma_addr_t offset = iova & ~IOVP_MASK; 806 807 BUG_ON(!dev); 808 ioc = GET_IOC(dev); 809 810 DBG_RUN("%s() iovp 0x%lx/%x\n", 811 __func__, (long)iova, size); 812 813 iova ^= offset; /* clear offset bits */ 814 size += offset; 815 size = ALIGN(size, IOVP_SIZE); 816 817 spin_lock_irqsave(&ioc->res_lock, flags); 818 819 #ifdef CCIO_COLLECT_STATS 820 ioc->usingle_calls++; 821 ioc->usingle_pages += size >> IOVP_SHIFT; 822 #endif 823 824 ccio_mark_invalid(ioc, iova, size); 825 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT)); 826 spin_unlock_irqrestore(&ioc->res_lock, flags); 827 } 828 829 /** 830 * ccio_alloc_consistent - Allocate a consistent DMA mapping. 831 * @dev: The PCI device. 832 * @size: The length of the DMA region. 833 * @dma_handle: The DMA address handed back to the device (not the cpu). 834 * 835 * This function implements the pci_alloc_consistent function. 836 */ 837 static void * 838 ccio_alloc_consistent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) 839 { 840 void *ret; 841 #if 0 842 /* GRANT Need to establish hierarchy for non-PCI devs as well 843 ** and then provide matching gsc_map_xxx() functions for them as well. 844 */ 845 if(!hwdev) { 846 /* only support PCI */ 847 *dma_handle = 0; 848 return 0; 849 } 850 #endif 851 ret = (void *) __get_free_pages(flag, get_order(size)); 852 853 if (ret) { 854 memset(ret, 0, size); 855 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL); 856 } 857 858 return ret; 859 } 860 861 /** 862 * ccio_free_consistent - Free a consistent DMA mapping. 863 * @dev: The PCI device. 864 * @size: The length of the DMA region. 865 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent. 866 * @dma_handle: The device address returned from the ccio_alloc_consistent. 867 * 868 * This function implements the pci_free_consistent function. 869 */ 870 static void 871 ccio_free_consistent(struct device *dev, size_t size, void *cpu_addr, 872 dma_addr_t dma_handle) 873 { 874 ccio_unmap_single(dev, dma_handle, size, 0); 875 free_pages((unsigned long)cpu_addr, get_order(size)); 876 } 877 878 /* 879 ** Since 0 is a valid pdir_base index value, can't use that 880 ** to determine if a value is valid or not. Use a flag to indicate 881 ** the SG list entry contains a valid pdir index. 882 */ 883 #define PIDE_FLAG 0x80000000UL 884 885 #ifdef CCIO_COLLECT_STATS 886 #define IOMMU_MAP_STATS 887 #endif 888 #include "iommu-helpers.h" 889 890 /** 891 * ccio_map_sg - Map the scatter/gather list into the IOMMU. 892 * @dev: The PCI device. 893 * @sglist: The scatter/gather list to be mapped in the IOMMU. 894 * @nents: The number of entries in the scatter/gather list. 895 * @direction: The direction of the DMA transaction (to/from device). 896 * 897 * This function implements the pci_map_sg function. 898 */ 899 static int 900 ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 901 enum dma_data_direction direction) 902 { 903 struct ioc *ioc; 904 int coalesced, filled = 0; 905 unsigned long flags; 906 unsigned long hint = hint_lookup[(int)direction]; 907 unsigned long prev_len = 0, current_len = 0; 908 int i; 909 910 BUG_ON(!dev); 911 ioc = GET_IOC(dev); 912 913 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 914 915 /* Fast path single entry scatterlists. */ 916 if (nents == 1) { 917 sg_dma_address(sglist) = ccio_map_single(dev, 918 (void *)sg_virt_addr(sglist), sglist->length, 919 direction); 920 sg_dma_len(sglist) = sglist->length; 921 return 1; 922 } 923 924 for(i = 0; i < nents; i++) 925 prev_len += sglist[i].length; 926 927 spin_lock_irqsave(&ioc->res_lock, flags); 928 929 #ifdef CCIO_COLLECT_STATS 930 ioc->msg_calls++; 931 #endif 932 933 /* 934 ** First coalesce the chunks and allocate I/O pdir space 935 ** 936 ** If this is one DMA stream, we can properly map using the 937 ** correct virtual address associated with each DMA page. 938 ** w/o this association, we wouldn't have coherent DMA! 939 ** Access to the virtual address is what forces a two pass algorithm. 940 */ 941 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range); 942 943 /* 944 ** Program the I/O Pdir 945 ** 946 ** map the virtual addresses to the I/O Pdir 947 ** o dma_address will contain the pdir index 948 ** o dma_len will contain the number of bytes to map 949 ** o page/offset contain the virtual address. 950 */ 951 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry); 952 953 spin_unlock_irqrestore(&ioc->res_lock, flags); 954 955 BUG_ON(coalesced != filled); 956 957 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 958 959 for (i = 0; i < filled; i++) 960 current_len += sg_dma_len(sglist + i); 961 962 BUG_ON(current_len != prev_len); 963 964 return filled; 965 } 966 967 /** 968 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU. 969 * @dev: The PCI device. 970 * @sglist: The scatter/gather list to be unmapped from the IOMMU. 971 * @nents: The number of entries in the scatter/gather list. 972 * @direction: The direction of the DMA transaction (to/from device). 973 * 974 * This function implements the pci_unmap_sg function. 975 */ 976 static void 977 ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 978 enum dma_data_direction direction) 979 { 980 struct ioc *ioc; 981 982 BUG_ON(!dev); 983 ioc = GET_IOC(dev); 984 985 DBG_RUN_SG("%s() START %d entries, %08lx,%x\n", 986 __func__, nents, sg_virt_addr(sglist), sglist->length); 987 988 #ifdef CCIO_COLLECT_STATS 989 ioc->usg_calls++; 990 #endif 991 992 while(sg_dma_len(sglist) && nents--) { 993 994 #ifdef CCIO_COLLECT_STATS 995 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; 996 #endif 997 ccio_unmap_single(dev, sg_dma_address(sglist), 998 sg_dma_len(sglist), direction); 999 ++sglist; 1000 } 1001 1002 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1003 } 1004 1005 static struct hppa_dma_ops ccio_ops = { 1006 .dma_supported = ccio_dma_supported, 1007 .alloc_consistent = ccio_alloc_consistent, 1008 .alloc_noncoherent = ccio_alloc_consistent, 1009 .free_consistent = ccio_free_consistent, 1010 .map_single = ccio_map_single, 1011 .unmap_single = ccio_unmap_single, 1012 .map_sg = ccio_map_sg, 1013 .unmap_sg = ccio_unmap_sg, 1014 .dma_sync_single_for_cpu = NULL, /* NOP for U2/Uturn */ 1015 .dma_sync_single_for_device = NULL, /* NOP for U2/Uturn */ 1016 .dma_sync_sg_for_cpu = NULL, /* ditto */ 1017 .dma_sync_sg_for_device = NULL, /* ditto */ 1018 }; 1019 1020 #ifdef CONFIG_PROC_FS 1021 static int ccio_proc_info(struct seq_file *m, void *p) 1022 { 1023 int len = 0; 1024 struct ioc *ioc = ioc_list; 1025 1026 while (ioc != NULL) { 1027 unsigned int total_pages = ioc->res_size << 3; 1028 #ifdef CCIO_COLLECT_STATS 1029 unsigned long avg = 0, min, max; 1030 int j; 1031 #endif 1032 1033 len += seq_printf(m, "%s\n", ioc->name); 1034 1035 len += seq_printf(m, "Cujo 2.0 bug : %s\n", 1036 (ioc->cujo20_bug ? "yes" : "no")); 1037 1038 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1039 total_pages * 8, total_pages); 1040 1041 #ifdef CCIO_COLLECT_STATS 1042 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1043 total_pages - ioc->used_pages, ioc->used_pages, 1044 (int)(ioc->used_pages * 100 / total_pages)); 1045 #endif 1046 1047 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1048 ioc->res_size, total_pages); 1049 1050 #ifdef CCIO_COLLECT_STATS 1051 min = max = ioc->avg_search[0]; 1052 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) { 1053 avg += ioc->avg_search[j]; 1054 if(ioc->avg_search[j] > max) 1055 max = ioc->avg_search[j]; 1056 if(ioc->avg_search[j] < min) 1057 min = ioc->avg_search[j]; 1058 } 1059 avg /= CCIO_SEARCH_SAMPLE; 1060 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1061 min, avg, max); 1062 1063 len += seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", 1064 ioc->msingle_calls, ioc->msingle_pages, 1065 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1066 1067 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1068 min = ioc->usingle_calls - ioc->usg_calls; 1069 max = ioc->usingle_pages - ioc->usg_pages; 1070 len += seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", 1071 min, max, (int)((max * 1000)/min)); 1072 1073 len += seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", 1074 ioc->msg_calls, ioc->msg_pages, 1075 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1076 1077 len += seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", 1078 ioc->usg_calls, ioc->usg_pages, 1079 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1080 #endif /* CCIO_COLLECT_STATS */ 1081 1082 ioc = ioc->next; 1083 } 1084 1085 return 0; 1086 } 1087 1088 static int ccio_proc_info_open(struct inode *inode, struct file *file) 1089 { 1090 return single_open(file, &ccio_proc_info, NULL); 1091 } 1092 1093 static const struct file_operations ccio_proc_info_fops = { 1094 .owner = THIS_MODULE, 1095 .open = ccio_proc_info_open, 1096 .read = seq_read, 1097 .llseek = seq_lseek, 1098 .release = single_release, 1099 }; 1100 1101 static int ccio_proc_bitmap_info(struct seq_file *m, void *p) 1102 { 1103 int len = 0; 1104 struct ioc *ioc = ioc_list; 1105 1106 while (ioc != NULL) { 1107 u32 *res_ptr = (u32 *)ioc->res_map; 1108 int j; 1109 1110 for (j = 0; j < (ioc->res_size / sizeof(u32)); j++) { 1111 if ((j & 7) == 0) 1112 len += seq_puts(m, "\n "); 1113 len += seq_printf(m, "%08x", *res_ptr); 1114 res_ptr++; 1115 } 1116 len += seq_puts(m, "\n\n"); 1117 ioc = ioc->next; 1118 break; /* XXX - remove me */ 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int ccio_proc_bitmap_open(struct inode *inode, struct file *file) 1125 { 1126 return single_open(file, &ccio_proc_bitmap_info, NULL); 1127 } 1128 1129 static const struct file_operations ccio_proc_bitmap_fops = { 1130 .owner = THIS_MODULE, 1131 .open = ccio_proc_bitmap_open, 1132 .read = seq_read, 1133 .llseek = seq_lseek, 1134 .release = single_release, 1135 }; 1136 #endif /* CONFIG_PROC_FS */ 1137 1138 /** 1139 * ccio_find_ioc - Find the ioc in the ioc_list 1140 * @hw_path: The hardware path of the ioc. 1141 * 1142 * This function searches the ioc_list for an ioc that matches 1143 * the provide hardware path. 1144 */ 1145 static struct ioc * ccio_find_ioc(int hw_path) 1146 { 1147 int i; 1148 struct ioc *ioc; 1149 1150 ioc = ioc_list; 1151 for (i = 0; i < ioc_count; i++) { 1152 if (ioc->hw_path == hw_path) 1153 return ioc; 1154 1155 ioc = ioc->next; 1156 } 1157 1158 return NULL; 1159 } 1160 1161 /** 1162 * ccio_get_iommu - Find the iommu which controls this device 1163 * @dev: The parisc device. 1164 * 1165 * This function searches through the registered IOMMU's and returns 1166 * the appropriate IOMMU for the device based on its hardware path. 1167 */ 1168 void * ccio_get_iommu(const struct parisc_device *dev) 1169 { 1170 dev = find_pa_parent_type(dev, HPHW_IOA); 1171 if (!dev) 1172 return NULL; 1173 1174 return ccio_find_ioc(dev->hw_path); 1175 } 1176 1177 #define CUJO_20_STEP 0x10000000 /* inc upper nibble */ 1178 1179 /* Cujo 2.0 has a bug which will silently corrupt data being transferred 1180 * to/from certain pages. To avoid this happening, we mark these pages 1181 * as `used', and ensure that nothing will try to allocate from them. 1182 */ 1183 void ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp) 1184 { 1185 unsigned int idx; 1186 struct parisc_device *dev = parisc_parent(cujo); 1187 struct ioc *ioc = ccio_get_iommu(dev); 1188 u8 *res_ptr; 1189 1190 ioc->cujo20_bug = 1; 1191 res_ptr = ioc->res_map; 1192 idx = PDIR_INDEX(iovp) >> 3; 1193 1194 while (idx < ioc->res_size) { 1195 res_ptr[idx] |= 0xff; 1196 idx += PDIR_INDEX(CUJO_20_STEP) >> 3; 1197 } 1198 } 1199 1200 #if 0 1201 /* GRANT - is this needed for U2 or not? */ 1202 1203 /* 1204 ** Get the size of the I/O TLB for this I/O MMU. 1205 ** 1206 ** If spa_shift is non-zero (ie probably U2), 1207 ** then calculate the I/O TLB size using spa_shift. 1208 ** 1209 ** Otherwise we are supposed to get the IODC entry point ENTRY TLB 1210 ** and execute it. However, both U2 and Uturn firmware supplies spa_shift. 1211 ** I think only Java (K/D/R-class too?) systems don't do this. 1212 */ 1213 static int 1214 ccio_get_iotlb_size(struct parisc_device *dev) 1215 { 1216 if (dev->spa_shift == 0) { 1217 panic("%s() : Can't determine I/O TLB size.\n", __func__); 1218 } 1219 return (1 << dev->spa_shift); 1220 } 1221 #else 1222 1223 /* Uturn supports 256 TLB entries */ 1224 #define CCIO_CHAINID_SHIFT 8 1225 #define CCIO_CHAINID_MASK 0xff 1226 #endif /* 0 */ 1227 1228 /* We *can't* support JAVA (T600). Venture there at your own risk. */ 1229 static const struct parisc_device_id ccio_tbl[] = { 1230 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */ 1231 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */ 1232 { 0, } 1233 }; 1234 1235 static int ccio_probe(struct parisc_device *dev); 1236 1237 static struct parisc_driver ccio_driver = { 1238 .name = "ccio", 1239 .id_table = ccio_tbl, 1240 .probe = ccio_probe, 1241 }; 1242 1243 /** 1244 * ccio_ioc_init - Initalize the I/O Controller 1245 * @ioc: The I/O Controller. 1246 * 1247 * Initalize the I/O Controller which includes setting up the 1248 * I/O Page Directory, the resource map, and initalizing the 1249 * U2/Uturn chip into virtual mode. 1250 */ 1251 static void 1252 ccio_ioc_init(struct ioc *ioc) 1253 { 1254 int i; 1255 unsigned int iov_order; 1256 u32 iova_space_size; 1257 1258 /* 1259 ** Determine IOVA Space size from memory size. 1260 ** 1261 ** Ideally, PCI drivers would register the maximum number 1262 ** of DMA they can have outstanding for each device they 1263 ** own. Next best thing would be to guess how much DMA 1264 ** can be outstanding based on PCI Class/sub-class. Both 1265 ** methods still require some "extra" to support PCI 1266 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1267 */ 1268 1269 iova_space_size = (u32) (totalram_pages / count_parisc_driver(&ccio_driver)); 1270 1271 /* limit IOVA space size to 1MB-1GB */ 1272 1273 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1274 iova_space_size = 1 << (20 - PAGE_SHIFT); 1275 #ifdef __LP64__ 1276 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1277 iova_space_size = 1 << (30 - PAGE_SHIFT); 1278 #endif 1279 } 1280 1281 /* 1282 ** iova space must be log2() in size. 1283 ** thus, pdir/res_map will also be log2(). 1284 */ 1285 1286 /* We could use larger page sizes in order to *decrease* the number 1287 ** of mappings needed. (ie 8k pages means 1/2 the mappings). 1288 ** 1289 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either 1290 ** since the pages must also be physically contiguous - typically 1291 ** this is the case under linux." 1292 */ 1293 1294 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1295 1296 /* iova_space_size is now bytes, not pages */ 1297 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1298 1299 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1300 1301 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ 1302 1303 /* Verify it's a power of two */ 1304 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); 1305 1306 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", 1307 __func__, ioc->ioc_regs, 1308 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT), 1309 iova_space_size>>20, 1310 iov_order + PAGE_SHIFT); 1311 1312 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, 1313 get_order(ioc->pdir_size)); 1314 if(NULL == ioc->pdir_base) { 1315 panic("%s() could not allocate I/O Page Table\n", __func__); 1316 } 1317 memset(ioc->pdir_base, 0, ioc->pdir_size); 1318 1319 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); 1320 DBG_INIT(" base %p\n", ioc->pdir_base); 1321 1322 /* resource map size dictated by pdir_size */ 1323 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; 1324 DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); 1325 1326 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, 1327 get_order(ioc->res_size)); 1328 if(NULL == ioc->res_map) { 1329 panic("%s() could not allocate resource map\n", __func__); 1330 } 1331 memset(ioc->res_map, 0, ioc->res_size); 1332 1333 /* Initialize the res_hint to 16 */ 1334 ioc->res_hint = 16; 1335 1336 /* Initialize the spinlock */ 1337 spin_lock_init(&ioc->res_lock); 1338 1339 /* 1340 ** Chainid is the upper most bits of an IOVP used to determine 1341 ** which TLB entry an IOVP will use. 1342 */ 1343 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; 1344 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); 1345 1346 /* 1347 ** Initialize IOA hardware 1348 */ 1349 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, 1350 &ioc->ioc_regs->io_chain_id_mask); 1351 1352 WRITE_U32(virt_to_phys(ioc->pdir_base), 1353 &ioc->ioc_regs->io_pdir_base); 1354 1355 /* 1356 ** Go to "Virtual Mode" 1357 */ 1358 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); 1359 1360 /* 1361 ** Initialize all I/O TLB entries to 0 (Valid bit off). 1362 */ 1363 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); 1364 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); 1365 1366 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { 1367 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), 1368 &ioc->ioc_regs->io_command); 1369 } 1370 } 1371 1372 static void __init 1373 ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) 1374 { 1375 int result; 1376 1377 res->parent = NULL; 1378 res->flags = IORESOURCE_MEM; 1379 /* 1380 * bracing ((signed) ...) are required for 64bit kernel because 1381 * we only want to sign extend the lower 16 bits of the register. 1382 * The upper 16-bits of range registers are hardcoded to 0xffff. 1383 */ 1384 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); 1385 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); 1386 res->name = name; 1387 /* 1388 * Check if this MMIO range is disable 1389 */ 1390 if (res->end + 1 == res->start) 1391 return; 1392 1393 /* On some platforms (e.g. K-Class), we have already registered 1394 * resources for devices reported by firmware. Some are children 1395 * of ccio. 1396 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem). 1397 */ 1398 result = insert_resource(&iomem_resource, res); 1399 if (result < 0) { 1400 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n", 1401 __func__, (unsigned long)res->start, (unsigned long)res->end); 1402 } 1403 } 1404 1405 static void __init ccio_init_resources(struct ioc *ioc) 1406 { 1407 struct resource *res = ioc->mmio_region; 1408 char *name = kmalloc(14, GFP_KERNEL); 1409 1410 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); 1411 1412 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); 1413 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); 1414 } 1415 1416 static int new_ioc_area(struct resource *res, unsigned long size, 1417 unsigned long min, unsigned long max, unsigned long align) 1418 { 1419 if (max <= min) 1420 return -EBUSY; 1421 1422 res->start = (max - size + 1) &~ (align - 1); 1423 res->end = res->start + size; 1424 1425 /* We might be trying to expand the MMIO range to include 1426 * a child device that has already registered it's MMIO space. 1427 * Use "insert" instead of request_resource(). 1428 */ 1429 if (!insert_resource(&iomem_resource, res)) 1430 return 0; 1431 1432 return new_ioc_area(res, size, min, max - size, align); 1433 } 1434 1435 static int expand_ioc_area(struct resource *res, unsigned long size, 1436 unsigned long min, unsigned long max, unsigned long align) 1437 { 1438 unsigned long start, len; 1439 1440 if (!res->parent) 1441 return new_ioc_area(res, size, min, max, align); 1442 1443 start = (res->start - size) &~ (align - 1); 1444 len = res->end - start + 1; 1445 if (start >= min) { 1446 if (!adjust_resource(res, start, len)) 1447 return 0; 1448 } 1449 1450 start = res->start; 1451 len = ((size + res->end + align) &~ (align - 1)) - start; 1452 if (start + len <= max) { 1453 if (!adjust_resource(res, start, len)) 1454 return 0; 1455 } 1456 1457 return -EBUSY; 1458 } 1459 1460 /* 1461 * Dino calls this function. Beware that we may get called on systems 1462 * which have no IOC (725, B180, C160L, etc) but do have a Dino. 1463 * So it's legal to find no parent IOC. 1464 * 1465 * Some other issues: one of the resources in the ioc may be unassigned. 1466 */ 1467 int ccio_allocate_resource(const struct parisc_device *dev, 1468 struct resource *res, unsigned long size, 1469 unsigned long min, unsigned long max, unsigned long align) 1470 { 1471 struct resource *parent = &iomem_resource; 1472 struct ioc *ioc = ccio_get_iommu(dev); 1473 if (!ioc) 1474 goto out; 1475 1476 parent = ioc->mmio_region; 1477 if (parent->parent && 1478 !allocate_resource(parent, res, size, min, max, align, NULL, NULL)) 1479 return 0; 1480 1481 if ((parent + 1)->parent && 1482 !allocate_resource(parent + 1, res, size, min, max, align, 1483 NULL, NULL)) 1484 return 0; 1485 1486 if (!expand_ioc_area(parent, size, min, max, align)) { 1487 __raw_writel(((parent->start)>>16) | 0xffff0000, 1488 &ioc->ioc_regs->io_io_low); 1489 __raw_writel(((parent->end)>>16) | 0xffff0000, 1490 &ioc->ioc_regs->io_io_high); 1491 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) { 1492 parent++; 1493 __raw_writel(((parent->start)>>16) | 0xffff0000, 1494 &ioc->ioc_regs->io_io_low_hv); 1495 __raw_writel(((parent->end)>>16) | 0xffff0000, 1496 &ioc->ioc_regs->io_io_high_hv); 1497 } else { 1498 return -EBUSY; 1499 } 1500 1501 out: 1502 return allocate_resource(parent, res, size, min, max, align, NULL,NULL); 1503 } 1504 1505 int ccio_request_resource(const struct parisc_device *dev, 1506 struct resource *res) 1507 { 1508 struct resource *parent; 1509 struct ioc *ioc = ccio_get_iommu(dev); 1510 1511 if (!ioc) { 1512 parent = &iomem_resource; 1513 } else if ((ioc->mmio_region->start <= res->start) && 1514 (res->end <= ioc->mmio_region->end)) { 1515 parent = ioc->mmio_region; 1516 } else if (((ioc->mmio_region + 1)->start <= res->start) && 1517 (res->end <= (ioc->mmio_region + 1)->end)) { 1518 parent = ioc->mmio_region + 1; 1519 } else { 1520 return -EBUSY; 1521 } 1522 1523 /* "transparent" bus bridges need to register MMIO resources 1524 * firmware assigned them. e.g. children of hppb.c (e.g. K-class) 1525 * registered their resources in the PDC "bus walk" (See 1526 * arch/parisc/kernel/inventory.c). 1527 */ 1528 return insert_resource(parent, res); 1529 } 1530 1531 /** 1532 * ccio_probe - Determine if ccio should claim this device. 1533 * @dev: The device which has been found 1534 * 1535 * Determine if ccio should claim this chip (return 0) or not (return 1). 1536 * If so, initialize the chip and tell other partners in crime they 1537 * have work to do. 1538 */ 1539 static int __init ccio_probe(struct parisc_device *dev) 1540 { 1541 int i; 1542 struct ioc *ioc, **ioc_p = &ioc_list; 1543 1544 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); 1545 if (ioc == NULL) { 1546 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); 1547 return 1; 1548 } 1549 1550 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; 1551 1552 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, 1553 (unsigned long)dev->hpa.start); 1554 1555 for (i = 0; i < ioc_count; i++) { 1556 ioc_p = &(*ioc_p)->next; 1557 } 1558 *ioc_p = ioc; 1559 1560 ioc->hw_path = dev->hw_path; 1561 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); 1562 ccio_ioc_init(ioc); 1563 ccio_init_resources(ioc); 1564 hppa_dma_ops = &ccio_ops; 1565 dev->dev.platform_data = kzalloc(sizeof(struct pci_hba_data), GFP_KERNEL); 1566 1567 /* if this fails, no I/O cards will work, so may as well bug */ 1568 BUG_ON(dev->dev.platform_data == NULL); 1569 HBA_DATA(dev->dev.platform_data)->iommu = ioc; 1570 1571 #ifdef CONFIG_PROC_FS 1572 if (ioc_count == 0) { 1573 proc_create(MODULE_NAME, 0, proc_runway_root, 1574 &ccio_proc_info_fops); 1575 proc_create(MODULE_NAME"-bitmap", 0, proc_runway_root, 1576 &ccio_proc_bitmap_fops); 1577 } 1578 #endif 1579 ioc_count++; 1580 1581 parisc_has_iommu(); 1582 return 0; 1583 } 1584 1585 /** 1586 * ccio_init - ccio initialization procedure. 1587 * 1588 * Register this driver. 1589 */ 1590 void __init ccio_init(void) 1591 { 1592 register_parisc_driver(&ccio_driver); 1593 } 1594 1595