1 /* 2 ** ccio-dma.c: 3 ** DMA management routines for first generation cache-coherent machines. 4 ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU. 5 ** 6 ** (c) Copyright 2000 Grant Grundler 7 ** (c) Copyright 2000 Ryan Bradetich 8 ** (c) Copyright 2000 Hewlett-Packard Company 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** "Real Mode" operation refers to U2/Uturn chip operation. 17 ** U2/Uturn were designed to perform coherency checks w/o using 18 ** the I/O MMU - basically what x86 does. 19 ** 20 ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at: 21 ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc 22 ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c 23 ** 24 ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c. 25 ** 26 ** Drawbacks of using Real Mode are: 27 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal). 28 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute. 29 ** o Ability to do scatter/gather in HW is lost. 30 ** o Doesn't work under PCX-U/U+ machines since they didn't follow 31 ** the coherency design originally worked out. Only PCX-W does. 32 */ 33 34 #include <linux/types.h> 35 #include <linux/kernel.h> 36 #include <linux/init.h> 37 #include <linux/mm.h> 38 #include <linux/spinlock.h> 39 #include <linux/slab.h> 40 #include <linux/string.h> 41 #include <linux/pci.h> 42 #include <linux/reboot.h> 43 #include <linux/proc_fs.h> 44 #include <linux/seq_file.h> 45 #include <linux/scatterlist.h> 46 #include <linux/iommu-helper.h> 47 #include <linux/export.h> 48 49 #include <asm/byteorder.h> 50 #include <asm/cache.h> /* for L1_CACHE_BYTES */ 51 #include <linux/uaccess.h> 52 #include <asm/page.h> 53 #include <asm/dma.h> 54 #include <asm/io.h> 55 #include <asm/hardware.h> /* for register_module() */ 56 #include <asm/parisc-device.h> 57 58 #include "iommu.h" 59 60 /* 61 ** Choose "ccio" since that's what HP-UX calls it. 62 ** Make it easier for folks to migrate from one to the other :^) 63 */ 64 #define MODULE_NAME "ccio" 65 66 #undef DEBUG_CCIO_RES 67 #undef DEBUG_CCIO_RUN 68 #undef DEBUG_CCIO_INIT 69 #undef DEBUG_CCIO_RUN_SG 70 71 #ifdef CONFIG_PROC_FS 72 /* depends on proc fs support. But costs CPU performance. */ 73 #undef CCIO_COLLECT_STATS 74 #endif 75 76 #include <asm/runway.h> /* for proc_runway_root */ 77 78 #ifdef DEBUG_CCIO_INIT 79 #define DBG_INIT(x...) printk(x) 80 #else 81 #define DBG_INIT(x...) 82 #endif 83 84 #ifdef DEBUG_CCIO_RUN 85 #define DBG_RUN(x...) printk(x) 86 #else 87 #define DBG_RUN(x...) 88 #endif 89 90 #ifdef DEBUG_CCIO_RES 91 #define DBG_RES(x...) printk(x) 92 #else 93 #define DBG_RES(x...) 94 #endif 95 96 #ifdef DEBUG_CCIO_RUN_SG 97 #define DBG_RUN_SG(x...) printk(x) 98 #else 99 #define DBG_RUN_SG(x...) 100 #endif 101 102 #define CCIO_INLINE inline 103 #define WRITE_U32(value, addr) __raw_writel(value, addr) 104 #define READ_U32(addr) __raw_readl(addr) 105 106 #define U2_IOA_RUNWAY 0x580 107 #define U2_BC_GSC 0x501 108 #define UTURN_IOA_RUNWAY 0x581 109 #define UTURN_BC_GSC 0x502 110 111 #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */ 112 #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */ 113 #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */ 114 115 struct ioa_registers { 116 /* Runway Supervisory Set */ 117 int32_t unused1[12]; 118 uint32_t io_command; /* Offset 12 */ 119 uint32_t io_status; /* Offset 13 */ 120 uint32_t io_control; /* Offset 14 */ 121 int32_t unused2[1]; 122 123 /* Runway Auxiliary Register Set */ 124 uint32_t io_err_resp; /* Offset 0 */ 125 uint32_t io_err_info; /* Offset 1 */ 126 uint32_t io_err_req; /* Offset 2 */ 127 uint32_t io_err_resp_hi; /* Offset 3 */ 128 uint32_t io_tlb_entry_m; /* Offset 4 */ 129 uint32_t io_tlb_entry_l; /* Offset 5 */ 130 uint32_t unused3[1]; 131 uint32_t io_pdir_base; /* Offset 7 */ 132 uint32_t io_io_low_hv; /* Offset 8 */ 133 uint32_t io_io_high_hv; /* Offset 9 */ 134 uint32_t unused4[1]; 135 uint32_t io_chain_id_mask; /* Offset 11 */ 136 uint32_t unused5[2]; 137 uint32_t io_io_low; /* Offset 14 */ 138 uint32_t io_io_high; /* Offset 15 */ 139 }; 140 141 /* 142 ** IOA Registers 143 ** ------------- 144 ** 145 ** Runway IO_CONTROL Register (+0x38) 146 ** 147 ** The Runway IO_CONTROL register controls the forwarding of transactions. 148 ** 149 ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 | 150 ** | HV | TLB | reserved | HV | mode | reserved | 151 ** 152 ** o mode field indicates the address translation of transactions 153 ** forwarded from Runway to GSC+: 154 ** Mode Name Value Definition 155 ** Off (default) 0 Opaque to matching addresses. 156 ** Include 1 Transparent for matching addresses. 157 ** Peek 3 Map matching addresses. 158 ** 159 ** + "Off" mode: Runway transactions which match the I/O range 160 ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored. 161 ** + "Include" mode: all addresses within the I/O range specified 162 ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently 163 ** forwarded. This is the I/O Adapter's normal operating mode. 164 ** + "Peek" mode: used during system configuration to initialize the 165 ** GSC+ bus. Runway Write_Shorts in the address range specified by 166 ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter 167 ** *AND* the GSC+ address is remapped to the Broadcast Physical 168 ** Address space by setting the 14 high order address bits of the 169 ** 32 bit GSC+ address to ones. 170 ** 171 ** o TLB field affects transactions which are forwarded from GSC+ to Runway. 172 ** "Real" mode is the poweron default. 173 ** 174 ** TLB Mode Value Description 175 ** Real 0 No TLB translation. Address is directly mapped and the 176 ** virtual address is composed of selected physical bits. 177 ** Error 1 Software fills the TLB manually. 178 ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory). 179 ** 180 ** 181 ** IO_IO_LOW_HV +0x60 (HV dependent) 182 ** IO_IO_HIGH_HV +0x64 (HV dependent) 183 ** IO_IO_LOW +0x78 (Architected register) 184 ** IO_IO_HIGH +0x7c (Architected register) 185 ** 186 ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the 187 ** I/O Adapter address space, respectively. 188 ** 189 ** 0 ... 7 | 8 ... 15 | 16 ... 31 | 190 ** 11111111 | 11111111 | address | 191 ** 192 ** Each LOW/HIGH pair describes a disjoint address space region. 193 ** (2 per GSC+ port). Each incoming Runway transaction address is compared 194 ** with both sets of LOW/HIGH registers. If the address is in the range 195 ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction 196 ** for forwarded to the respective GSC+ bus. 197 ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying 198 ** an address space region. 199 ** 200 ** In order for a Runway address to reside within GSC+ extended address space: 201 ** Runway Address [0:7] must identically compare to 8'b11111111 202 ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19] 203 ** Runway Address [12:23] must be greater than or equal to 204 ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31]. 205 ** Runway Address [24:39] is not used in the comparison. 206 ** 207 ** When the Runway transaction is forwarded to GSC+, the GSC+ address is 208 ** as follows: 209 ** GSC+ Address[0:3] 4'b1111 210 ** GSC+ Address[4:29] Runway Address[12:37] 211 ** GSC+ Address[30:31] 2'b00 212 ** 213 ** All 4 Low/High registers must be initialized (by PDC) once the lower bus 214 ** is interrogated and address space is defined. The operating system will 215 ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following 216 ** the PDC initialization. However, the hardware version dependent IO_IO_LOW 217 ** and IO_IO_HIGH registers should not be subsequently altered by the OS. 218 ** 219 ** Writes to both sets of registers will take effect immediately, bypassing 220 ** the queues, which ensures that subsequent Runway transactions are checked 221 ** against the updated bounds values. However reads are queued, introducing 222 ** the possibility of a read being bypassed by a subsequent write to the same 223 ** register. This sequence can be avoided by having software wait for read 224 ** returns before issuing subsequent writes. 225 */ 226 227 struct ioc { 228 struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */ 229 u8 *res_map; /* resource map, bit == pdir entry */ 230 u64 *pdir_base; /* physical base address */ 231 u32 pdir_size; /* bytes, function of IOV Space size */ 232 u32 res_hint; /* next available IOVP - 233 circular search */ 234 u32 res_size; /* size of resource map in bytes */ 235 spinlock_t res_lock; 236 237 #ifdef CCIO_COLLECT_STATS 238 #define CCIO_SEARCH_SAMPLE 0x100 239 unsigned long avg_search[CCIO_SEARCH_SAMPLE]; 240 unsigned long avg_idx; /* current index into avg_search */ 241 unsigned long used_pages; 242 unsigned long msingle_calls; 243 unsigned long msingle_pages; 244 unsigned long msg_calls; 245 unsigned long msg_pages; 246 unsigned long usingle_calls; 247 unsigned long usingle_pages; 248 unsigned long usg_calls; 249 unsigned long usg_pages; 250 #endif 251 unsigned short cujo20_bug; 252 253 /* STUFF We don't need in performance path */ 254 u32 chainid_shift; /* specify bit location of chain_id */ 255 struct ioc *next; /* Linked list of discovered iocs */ 256 const char *name; /* device name from firmware */ 257 unsigned int hw_path; /* the hardware path this ioc is associatd with */ 258 struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */ 259 struct resource mmio_region[2]; /* The "routed" MMIO regions */ 260 }; 261 262 static struct ioc *ioc_list; 263 static int ioc_count; 264 265 /************************************************************** 266 * 267 * I/O Pdir Resource Management 268 * 269 * Bits set in the resource map are in use. 270 * Each bit can represent a number of pages. 271 * LSbs represent lower addresses (IOVA's). 272 * 273 * This was was copied from sba_iommu.c. Don't try to unify 274 * the two resource managers unless a way to have different 275 * allocation policies is also adjusted. We'd like to avoid 276 * I/O TLB thrashing by having resource allocation policy 277 * match the I/O TLB replacement policy. 278 * 279 ***************************************************************/ 280 #define IOVP_SIZE PAGE_SIZE 281 #define IOVP_SHIFT PAGE_SHIFT 282 #define IOVP_MASK PAGE_MASK 283 284 /* Convert from IOVP to IOVA and vice versa. */ 285 #define CCIO_IOVA(iovp,offset) ((iovp) | (offset)) 286 #define CCIO_IOVP(iova) ((iova) & IOVP_MASK) 287 288 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 289 #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT) 290 #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset) 291 292 /* 293 ** Don't worry about the 150% average search length on a miss. 294 ** If the search wraps around, and passes the res_hint, it will 295 ** cause the kernel to panic anyhow. 296 */ 297 #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ 298 for(; res_ptr < res_end; ++res_ptr) { \ 299 int ret;\ 300 unsigned int idx;\ 301 idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \ 302 ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\ 303 if ((0 == (*res_ptr & mask)) && !ret) { \ 304 *res_ptr |= mask; \ 305 res_idx = idx;\ 306 ioc->res_hint = res_idx + (size >> 3); \ 307 goto resource_found; \ 308 } \ 309 } 310 311 #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ 312 u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \ 313 u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \ 314 CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ 315 res_ptr = (u##size *)&(ioc)->res_map[0]; \ 316 CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); 317 318 /* 319 ** Find available bit in this ioa's resource map. 320 ** Use a "circular" search: 321 ** o Most IOVA's are "temporary" - avg search time should be small. 322 ** o keep a history of what happened for debugging 323 ** o KISS. 324 ** 325 ** Perf optimizations: 326 ** o search for log2(size) bits at a time. 327 ** o search for available resource bits using byte/word/whatever. 328 ** o use different search for "large" (eg > 4 pages) or "very large" 329 ** (eg > 16 pages) mappings. 330 */ 331 332 /** 333 * ccio_alloc_range - Allocate pages in the ioc's resource map. 334 * @ioc: The I/O Controller. 335 * @pages_needed: The requested number of pages to be mapped into the 336 * I/O Pdir... 337 * 338 * This function searches the resource map of the ioc to locate a range 339 * of available pages for the requested size. 340 */ 341 static int 342 ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size) 343 { 344 unsigned int pages_needed = size >> IOVP_SHIFT; 345 unsigned int res_idx; 346 unsigned long boundary_size; 347 #ifdef CCIO_COLLECT_STATS 348 unsigned long cr_start = mfctl(16); 349 #endif 350 351 BUG_ON(pages_needed == 0); 352 BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE); 353 354 DBG_RES("%s() size: %d pages_needed %d\n", 355 __func__, size, pages_needed); 356 357 /* 358 ** "seek and ye shall find"...praying never hurts either... 359 ** ggg sacrifices another 710 to the computer gods. 360 */ 361 362 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, 363 1ULL << IOVP_SHIFT) >> IOVP_SHIFT; 364 365 if (pages_needed <= 8) { 366 /* 367 * LAN traffic will not thrash the TLB IFF the same NIC 368 * uses 8 adjacent pages to map separate payload data. 369 * ie the same byte in the resource bit map. 370 */ 371 #if 0 372 /* FIXME: bit search should shift it's way through 373 * an unsigned long - not byte at a time. As it is now, 374 * we effectively allocate this byte to this mapping. 375 */ 376 unsigned long mask = ~(~0UL >> pages_needed); 377 CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8); 378 #else 379 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8); 380 #endif 381 } else if (pages_needed <= 16) { 382 CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16); 383 } else if (pages_needed <= 32) { 384 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32); 385 #ifdef __LP64__ 386 } else if (pages_needed <= 64) { 387 CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64); 388 #endif 389 } else { 390 panic("%s: %s() Too many pages to map. pages_needed: %u\n", 391 __FILE__, __func__, pages_needed); 392 } 393 394 panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__, 395 __func__); 396 397 resource_found: 398 399 DBG_RES("%s() res_idx %d res_hint: %d\n", 400 __func__, res_idx, ioc->res_hint); 401 402 #ifdef CCIO_COLLECT_STATS 403 { 404 unsigned long cr_end = mfctl(16); 405 unsigned long tmp = cr_end - cr_start; 406 /* check for roll over */ 407 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 408 } 409 ioc->avg_search[ioc->avg_idx++] = cr_start; 410 ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1; 411 ioc->used_pages += pages_needed; 412 #endif 413 /* 414 ** return the bit address. 415 */ 416 return res_idx << 3; 417 } 418 419 #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ 420 u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \ 421 BUG_ON((*res_ptr & mask) != mask); \ 422 *res_ptr &= ~(mask); 423 424 /** 425 * ccio_free_range - Free pages from the ioc's resource map. 426 * @ioc: The I/O Controller. 427 * @iova: The I/O Virtual Address. 428 * @pages_mapped: The requested number of pages to be freed from the 429 * I/O Pdir. 430 * 431 * This function frees the resouces allocated for the iova. 432 */ 433 static void 434 ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped) 435 { 436 unsigned long iovp = CCIO_IOVP(iova); 437 unsigned int res_idx = PDIR_INDEX(iovp) >> 3; 438 439 BUG_ON(pages_mapped == 0); 440 BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE); 441 BUG_ON(pages_mapped > BITS_PER_LONG); 442 443 DBG_RES("%s(): res_idx: %d pages_mapped %d\n", 444 __func__, res_idx, pages_mapped); 445 446 #ifdef CCIO_COLLECT_STATS 447 ioc->used_pages -= pages_mapped; 448 #endif 449 450 if(pages_mapped <= 8) { 451 #if 0 452 /* see matching comments in alloc_range */ 453 unsigned long mask = ~(~0UL >> pages_mapped); 454 CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8); 455 #else 456 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8); 457 #endif 458 } else if(pages_mapped <= 16) { 459 CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16); 460 } else if(pages_mapped <= 32) { 461 CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32); 462 #ifdef __LP64__ 463 } else if(pages_mapped <= 64) { 464 CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64); 465 #endif 466 } else { 467 panic("%s:%s() Too many pages to unmap.\n", __FILE__, 468 __func__); 469 } 470 } 471 472 /**************************************************************** 473 ** 474 ** CCIO dma_ops support routines 475 ** 476 *****************************************************************/ 477 478 typedef unsigned long space_t; 479 #define KERNEL_SPACE 0 480 481 /* 482 ** DMA "Page Type" and Hints 483 ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be 484 ** set for subcacheline DMA transfers since we don't want to damage the 485 ** other part of a cacheline. 486 ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent(). 487 ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming" 488 ** data can avoid this if the mapping covers full cache lines. 489 ** o STOP_MOST is needed for atomicity across cachelines. 490 ** Apparently only "some EISA devices" need this. 491 ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs 492 ** to use this hint iff the EISA devices needs this feature. 493 ** According to the U2 ERS, STOP_MOST enabled pages hurt performance. 494 ** o PREFETCH should *not* be set for cases like Multiple PCI devices 495 ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC 496 ** device can be fetched and multiply DMA streams will thrash the 497 ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules 498 ** and Invalidation of Prefetch Entries". 499 ** 500 ** FIXME: the default hints need to be per GSC device - not global. 501 ** 502 ** HP-UX dorks: linux device driver programming model is totally different 503 ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers 504 ** do special things to work on non-coherent platforms...linux has to 505 ** be much more careful with this. 506 */ 507 #define IOPDIR_VALID 0x01UL 508 #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */ 509 #ifdef CONFIG_EISA 510 #define HINT_STOP_MOST 0x04UL /* LSL support */ 511 #else 512 #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */ 513 #endif 514 #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */ 515 #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */ 516 517 518 /* 519 ** Use direction (ie PCI_DMA_TODEVICE) to pick hint. 520 ** ccio_alloc_consistent() depends on this to get SAFE_DMA 521 ** when it passes in BIDIRECTIONAL flag. 522 */ 523 static u32 hint_lookup[] = { 524 [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID, 525 [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID, 526 [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID, 527 }; 528 529 /** 530 * ccio_io_pdir_entry - Initialize an I/O Pdir. 531 * @pdir_ptr: A pointer into I/O Pdir. 532 * @sid: The Space Identifier. 533 * @vba: The virtual address. 534 * @hints: The DMA Hint. 535 * 536 * Given a virtual address (vba, arg2) and space id, (sid, arg1), 537 * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir 538 * entry consists of 8 bytes as shown below (MSB == bit 0): 539 * 540 * 541 * WORD 0: 542 * +------+----------------+-----------------------------------------------+ 543 * | Phys | Virtual Index | Phys | 544 * | 0:3 | 0:11 | 4:19 | 545 * |4 bits| 12 bits | 16 bits | 546 * +------+----------------+-----------------------------------------------+ 547 * WORD 1: 548 * +-----------------------+-----------------------------------------------+ 549 * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid | 550 * | 20:39 | | Enable |Enable | |Enable|DMA | | 551 * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit | 552 * +-----------------------+-----------------------------------------------+ 553 * 554 * The virtual index field is filled with the results of the LCI 555 * (Load Coherence Index) instruction. The 8 bits used for the virtual 556 * index are bits 12:19 of the value returned by LCI. 557 */ 558 static void CCIO_INLINE 559 ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 560 unsigned long hints) 561 { 562 register unsigned long pa; 563 register unsigned long ci; /* coherent index */ 564 565 /* We currently only support kernel addresses */ 566 BUG_ON(sid != KERNEL_SPACE); 567 568 mtsp(sid,1); 569 570 /* 571 ** WORD 1 - low order word 572 ** "hints" parm includes the VALID bit! 573 ** "dep" clobbers the physical address offset bits as well. 574 */ 575 pa = virt_to_phys(vba); 576 asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints)); 577 ((u32 *)pdir_ptr)[1] = (u32) pa; 578 579 /* 580 ** WORD 0 - high order word 581 */ 582 583 #ifdef __LP64__ 584 /* 585 ** get bits 12:15 of physical address 586 ** shift bits 16:31 of physical address 587 ** and deposit them 588 */ 589 asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa)); 590 asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa)); 591 asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci)); 592 #else 593 pa = 0; 594 #endif 595 /* 596 ** get CPU coherency index bits 597 ** Grab virtual index [0:11] 598 ** Deposit virt_idx bits into I/O PDIR word 599 */ 600 asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 601 asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci)); 602 asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci)); 603 604 ((u32 *)pdir_ptr)[0] = (u32) pa; 605 606 607 /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) 608 ** PCX-U/U+ do. (eg C200/C240) 609 ** PCX-T'? Don't know. (eg C110 or similar K-class) 610 ** 611 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit". 612 ** 613 ** "Since PCX-U employs an offset hash that is incompatible with 614 ** the real mode coherence index generation of U2, the PDIR entry 615 ** must be flushed to memory to retain coherence." 616 */ 617 asm_io_fdc(pdir_ptr); 618 asm_io_sync(); 619 } 620 621 /** 622 * ccio_clear_io_tlb - Remove stale entries from the I/O TLB. 623 * @ioc: The I/O Controller. 624 * @iovp: The I/O Virtual Page. 625 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. 626 * 627 * Purge invalid I/O PDIR entries from the I/O TLB. 628 * 629 * FIXME: Can we change the byte_cnt to pages_mapped? 630 */ 631 static CCIO_INLINE void 632 ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt) 633 { 634 u32 chain_size = 1 << ioc->chainid_shift; 635 636 iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */ 637 byte_cnt += chain_size; 638 639 while(byte_cnt > chain_size) { 640 WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command); 641 iovp += chain_size; 642 byte_cnt -= chain_size; 643 } 644 } 645 646 /** 647 * ccio_mark_invalid - Mark the I/O Pdir entries invalid. 648 * @ioc: The I/O Controller. 649 * @iova: The I/O Virtual Address. 650 * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir. 651 * 652 * Mark the I/O Pdir entries invalid and blow away the corresponding I/O 653 * TLB entries. 654 * 655 * FIXME: at some threshold it might be "cheaper" to just blow 656 * away the entire I/O TLB instead of individual entries. 657 * 658 * FIXME: Uturn has 256 TLB entries. We don't need to purge every 659 * PDIR entry - just once for each possible TLB entry. 660 * (We do need to maker I/O PDIR entries invalid regardless). 661 * 662 * FIXME: Can we change byte_cnt to pages_mapped? 663 */ 664 static CCIO_INLINE void 665 ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 666 { 667 u32 iovp = (u32)CCIO_IOVP(iova); 668 size_t saved_byte_cnt; 669 670 /* round up to nearest page size */ 671 saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE); 672 673 while(byte_cnt > 0) { 674 /* invalidate one page at a time */ 675 unsigned int idx = PDIR_INDEX(iovp); 676 char *pdir_ptr = (char *) &(ioc->pdir_base[idx]); 677 678 BUG_ON(idx >= (ioc->pdir_size / sizeof(u64))); 679 pdir_ptr[7] = 0; /* clear only VALID bit */ 680 /* 681 ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360) 682 ** PCX-U/U+ do. (eg C200/C240) 683 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit". 684 */ 685 asm_io_fdc(pdir_ptr); 686 687 iovp += IOVP_SIZE; 688 byte_cnt -= IOVP_SIZE; 689 } 690 691 asm_io_sync(); 692 ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt); 693 } 694 695 /**************************************************************** 696 ** 697 ** CCIO dma_ops 698 ** 699 *****************************************************************/ 700 701 /** 702 * ccio_dma_supported - Verify the IOMMU supports the DMA address range. 703 * @dev: The PCI device. 704 * @mask: A bit mask describing the DMA address range of the device. 705 */ 706 static int 707 ccio_dma_supported(struct device *dev, u64 mask) 708 { 709 if(dev == NULL) { 710 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 711 BUG(); 712 return 0; 713 } 714 715 /* only support 32-bit or better devices (ie PCI/GSC) */ 716 return (int)(mask >= 0xffffffffUL); 717 } 718 719 /** 720 * ccio_map_single - Map an address range into the IOMMU. 721 * @dev: The PCI device. 722 * @addr: The start address of the DMA region. 723 * @size: The length of the DMA region. 724 * @direction: The direction of the DMA transaction (to/from device). 725 * 726 * This function implements the pci_map_single function. 727 */ 728 static dma_addr_t 729 ccio_map_single(struct device *dev, void *addr, size_t size, 730 enum dma_data_direction direction) 731 { 732 int idx; 733 struct ioc *ioc; 734 unsigned long flags; 735 dma_addr_t iovp; 736 dma_addr_t offset; 737 u64 *pdir_start; 738 unsigned long hint = hint_lookup[(int)direction]; 739 740 BUG_ON(!dev); 741 ioc = GET_IOC(dev); 742 if (!ioc) 743 return DMA_MAPPING_ERROR; 744 745 BUG_ON(size <= 0); 746 747 /* save offset bits */ 748 offset = ((unsigned long) addr) & ~IOVP_MASK; 749 750 /* round up to nearest IOVP_SIZE */ 751 size = ALIGN(size + offset, IOVP_SIZE); 752 spin_lock_irqsave(&ioc->res_lock, flags); 753 754 #ifdef CCIO_COLLECT_STATS 755 ioc->msingle_calls++; 756 ioc->msingle_pages += size >> IOVP_SHIFT; 757 #endif 758 759 idx = ccio_alloc_range(ioc, dev, size); 760 iovp = (dma_addr_t)MKIOVP(idx); 761 762 pdir_start = &(ioc->pdir_base[idx]); 763 764 DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n", 765 __func__, addr, (long)iovp | offset, size); 766 767 /* If not cacheline aligned, force SAFE_DMA on the whole mess */ 768 if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES)) 769 hint |= HINT_SAFE_DMA; 770 771 while(size > 0) { 772 ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint); 773 774 DBG_RUN(" pdir %p %08x%08x\n", 775 pdir_start, 776 (u32) (((u32 *) pdir_start)[0]), 777 (u32) (((u32 *) pdir_start)[1])); 778 ++pdir_start; 779 addr += IOVP_SIZE; 780 size -= IOVP_SIZE; 781 } 782 783 spin_unlock_irqrestore(&ioc->res_lock, flags); 784 785 /* form complete address */ 786 return CCIO_IOVA(iovp, offset); 787 } 788 789 790 static dma_addr_t 791 ccio_map_page(struct device *dev, struct page *page, unsigned long offset, 792 size_t size, enum dma_data_direction direction, 793 unsigned long attrs) 794 { 795 return ccio_map_single(dev, page_address(page) + offset, size, 796 direction); 797 } 798 799 800 /** 801 * ccio_unmap_page - Unmap an address range from the IOMMU. 802 * @dev: The PCI device. 803 * @addr: The start address of the DMA region. 804 * @size: The length of the DMA region. 805 * @direction: The direction of the DMA transaction (to/from device). 806 */ 807 static void 808 ccio_unmap_page(struct device *dev, dma_addr_t iova, size_t size, 809 enum dma_data_direction direction, unsigned long attrs) 810 { 811 struct ioc *ioc; 812 unsigned long flags; 813 dma_addr_t offset = iova & ~IOVP_MASK; 814 815 BUG_ON(!dev); 816 ioc = GET_IOC(dev); 817 if (!ioc) { 818 WARN_ON(!ioc); 819 return; 820 } 821 822 DBG_RUN("%s() iovp 0x%lx/%x\n", 823 __func__, (long)iova, size); 824 825 iova ^= offset; /* clear offset bits */ 826 size += offset; 827 size = ALIGN(size, IOVP_SIZE); 828 829 spin_lock_irqsave(&ioc->res_lock, flags); 830 831 #ifdef CCIO_COLLECT_STATS 832 ioc->usingle_calls++; 833 ioc->usingle_pages += size >> IOVP_SHIFT; 834 #endif 835 836 ccio_mark_invalid(ioc, iova, size); 837 ccio_free_range(ioc, iova, (size >> IOVP_SHIFT)); 838 spin_unlock_irqrestore(&ioc->res_lock, flags); 839 } 840 841 /** 842 * ccio_alloc - Allocate a consistent DMA mapping. 843 * @dev: The PCI device. 844 * @size: The length of the DMA region. 845 * @dma_handle: The DMA address handed back to the device (not the cpu). 846 * 847 * This function implements the pci_alloc_consistent function. 848 */ 849 static void * 850 ccio_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag, 851 unsigned long attrs) 852 { 853 void *ret; 854 #if 0 855 /* GRANT Need to establish hierarchy for non-PCI devs as well 856 ** and then provide matching gsc_map_xxx() functions for them as well. 857 */ 858 if(!hwdev) { 859 /* only support PCI */ 860 *dma_handle = 0; 861 return 0; 862 } 863 #endif 864 ret = (void *) __get_free_pages(flag, get_order(size)); 865 866 if (ret) { 867 memset(ret, 0, size); 868 *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL); 869 } 870 871 return ret; 872 } 873 874 /** 875 * ccio_free - Free a consistent DMA mapping. 876 * @dev: The PCI device. 877 * @size: The length of the DMA region. 878 * @cpu_addr: The cpu address returned from the ccio_alloc_consistent. 879 * @dma_handle: The device address returned from the ccio_alloc_consistent. 880 * 881 * This function implements the pci_free_consistent function. 882 */ 883 static void 884 ccio_free(struct device *dev, size_t size, void *cpu_addr, 885 dma_addr_t dma_handle, unsigned long attrs) 886 { 887 ccio_unmap_page(dev, dma_handle, size, 0, 0); 888 free_pages((unsigned long)cpu_addr, get_order(size)); 889 } 890 891 /* 892 ** Since 0 is a valid pdir_base index value, can't use that 893 ** to determine if a value is valid or not. Use a flag to indicate 894 ** the SG list entry contains a valid pdir index. 895 */ 896 #define PIDE_FLAG 0x80000000UL 897 898 #ifdef CCIO_COLLECT_STATS 899 #define IOMMU_MAP_STATS 900 #endif 901 #include "iommu-helpers.h" 902 903 /** 904 * ccio_map_sg - Map the scatter/gather list into the IOMMU. 905 * @dev: The PCI device. 906 * @sglist: The scatter/gather list to be mapped in the IOMMU. 907 * @nents: The number of entries in the scatter/gather list. 908 * @direction: The direction of the DMA transaction (to/from device). 909 * 910 * This function implements the pci_map_sg function. 911 */ 912 static int 913 ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 914 enum dma_data_direction direction, unsigned long attrs) 915 { 916 struct ioc *ioc; 917 int coalesced, filled = 0; 918 unsigned long flags; 919 unsigned long hint = hint_lookup[(int)direction]; 920 unsigned long prev_len = 0, current_len = 0; 921 int i; 922 923 BUG_ON(!dev); 924 ioc = GET_IOC(dev); 925 if (!ioc) 926 return 0; 927 928 DBG_RUN_SG("%s() START %d entries\n", __func__, nents); 929 930 /* Fast path single entry scatterlists. */ 931 if (nents == 1) { 932 sg_dma_address(sglist) = ccio_map_single(dev, 933 sg_virt(sglist), sglist->length, 934 direction); 935 sg_dma_len(sglist) = sglist->length; 936 return 1; 937 } 938 939 for(i = 0; i < nents; i++) 940 prev_len += sglist[i].length; 941 942 spin_lock_irqsave(&ioc->res_lock, flags); 943 944 #ifdef CCIO_COLLECT_STATS 945 ioc->msg_calls++; 946 #endif 947 948 /* 949 ** First coalesce the chunks and allocate I/O pdir space 950 ** 951 ** If this is one DMA stream, we can properly map using the 952 ** correct virtual address associated with each DMA page. 953 ** w/o this association, we wouldn't have coherent DMA! 954 ** Access to the virtual address is what forces a two pass algorithm. 955 */ 956 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range); 957 958 /* 959 ** Program the I/O Pdir 960 ** 961 ** map the virtual addresses to the I/O Pdir 962 ** o dma_address will contain the pdir index 963 ** o dma_len will contain the number of bytes to map 964 ** o page/offset contain the virtual address. 965 */ 966 filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry); 967 968 spin_unlock_irqrestore(&ioc->res_lock, flags); 969 970 BUG_ON(coalesced != filled); 971 972 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); 973 974 for (i = 0; i < filled; i++) 975 current_len += sg_dma_len(sglist + i); 976 977 BUG_ON(current_len != prev_len); 978 979 return filled; 980 } 981 982 /** 983 * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU. 984 * @dev: The PCI device. 985 * @sglist: The scatter/gather list to be unmapped from the IOMMU. 986 * @nents: The number of entries in the scatter/gather list. 987 * @direction: The direction of the DMA transaction (to/from device). 988 * 989 * This function implements the pci_unmap_sg function. 990 */ 991 static void 992 ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 993 enum dma_data_direction direction, unsigned long attrs) 994 { 995 struct ioc *ioc; 996 997 BUG_ON(!dev); 998 ioc = GET_IOC(dev); 999 if (!ioc) { 1000 WARN_ON(!ioc); 1001 return; 1002 } 1003 1004 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 1005 __func__, nents, sg_virt(sglist), sglist->length); 1006 1007 #ifdef CCIO_COLLECT_STATS 1008 ioc->usg_calls++; 1009 #endif 1010 1011 while(sg_dma_len(sglist) && nents--) { 1012 1013 #ifdef CCIO_COLLECT_STATS 1014 ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT; 1015 #endif 1016 ccio_unmap_page(dev, sg_dma_address(sglist), 1017 sg_dma_len(sglist), direction, 0); 1018 ++sglist; 1019 } 1020 1021 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); 1022 } 1023 1024 static const struct dma_map_ops ccio_ops = { 1025 .dma_supported = ccio_dma_supported, 1026 .alloc = ccio_alloc, 1027 .free = ccio_free, 1028 .map_page = ccio_map_page, 1029 .unmap_page = ccio_unmap_page, 1030 .map_sg = ccio_map_sg, 1031 .unmap_sg = ccio_unmap_sg, 1032 }; 1033 1034 #ifdef CONFIG_PROC_FS 1035 static int ccio_proc_info(struct seq_file *m, void *p) 1036 { 1037 struct ioc *ioc = ioc_list; 1038 1039 while (ioc != NULL) { 1040 unsigned int total_pages = ioc->res_size << 3; 1041 #ifdef CCIO_COLLECT_STATS 1042 unsigned long avg = 0, min, max; 1043 int j; 1044 #endif 1045 1046 seq_printf(m, "%s\n", ioc->name); 1047 1048 seq_printf(m, "Cujo 2.0 bug : %s\n", 1049 (ioc->cujo20_bug ? "yes" : "no")); 1050 1051 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1052 total_pages * 8, total_pages); 1053 1054 #ifdef CCIO_COLLECT_STATS 1055 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1056 total_pages - ioc->used_pages, ioc->used_pages, 1057 (int)(ioc->used_pages * 100 / total_pages)); 1058 #endif 1059 1060 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1061 ioc->res_size, total_pages); 1062 1063 #ifdef CCIO_COLLECT_STATS 1064 min = max = ioc->avg_search[0]; 1065 for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) { 1066 avg += ioc->avg_search[j]; 1067 if(ioc->avg_search[j] > max) 1068 max = ioc->avg_search[j]; 1069 if(ioc->avg_search[j] < min) 1070 min = ioc->avg_search[j]; 1071 } 1072 avg /= CCIO_SEARCH_SAMPLE; 1073 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1074 min, avg, max); 1075 1076 seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n", 1077 ioc->msingle_calls, ioc->msingle_pages, 1078 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1079 1080 /* KLUGE - unmap_sg calls unmap_page for each mapped page */ 1081 min = ioc->usingle_calls - ioc->usg_calls; 1082 max = ioc->usingle_pages - ioc->usg_pages; 1083 seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n", 1084 min, max, (int)((max * 1000)/min)); 1085 1086 seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n", 1087 ioc->msg_calls, ioc->msg_pages, 1088 (int)((ioc->msg_pages * 1000)/ioc->msg_calls)); 1089 1090 seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n", 1091 ioc->usg_calls, ioc->usg_pages, 1092 (int)((ioc->usg_pages * 1000)/ioc->usg_calls)); 1093 #endif /* CCIO_COLLECT_STATS */ 1094 1095 ioc = ioc->next; 1096 } 1097 1098 return 0; 1099 } 1100 1101 static int ccio_proc_bitmap_info(struct seq_file *m, void *p) 1102 { 1103 struct ioc *ioc = ioc_list; 1104 1105 while (ioc != NULL) { 1106 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map, 1107 ioc->res_size, false); 1108 seq_putc(m, '\n'); 1109 ioc = ioc->next; 1110 break; /* XXX - remove me */ 1111 } 1112 1113 return 0; 1114 } 1115 #endif /* CONFIG_PROC_FS */ 1116 1117 /** 1118 * ccio_find_ioc - Find the ioc in the ioc_list 1119 * @hw_path: The hardware path of the ioc. 1120 * 1121 * This function searches the ioc_list for an ioc that matches 1122 * the provide hardware path. 1123 */ 1124 static struct ioc * ccio_find_ioc(int hw_path) 1125 { 1126 int i; 1127 struct ioc *ioc; 1128 1129 ioc = ioc_list; 1130 for (i = 0; i < ioc_count; i++) { 1131 if (ioc->hw_path == hw_path) 1132 return ioc; 1133 1134 ioc = ioc->next; 1135 } 1136 1137 return NULL; 1138 } 1139 1140 /** 1141 * ccio_get_iommu - Find the iommu which controls this device 1142 * @dev: The parisc device. 1143 * 1144 * This function searches through the registered IOMMU's and returns 1145 * the appropriate IOMMU for the device based on its hardware path. 1146 */ 1147 void * ccio_get_iommu(const struct parisc_device *dev) 1148 { 1149 dev = find_pa_parent_type(dev, HPHW_IOA); 1150 if (!dev) 1151 return NULL; 1152 1153 return ccio_find_ioc(dev->hw_path); 1154 } 1155 1156 #define CUJO_20_STEP 0x10000000 /* inc upper nibble */ 1157 1158 /* Cujo 2.0 has a bug which will silently corrupt data being transferred 1159 * to/from certain pages. To avoid this happening, we mark these pages 1160 * as `used', and ensure that nothing will try to allocate from them. 1161 */ 1162 void __init ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp) 1163 { 1164 unsigned int idx; 1165 struct parisc_device *dev = parisc_parent(cujo); 1166 struct ioc *ioc = ccio_get_iommu(dev); 1167 u8 *res_ptr; 1168 1169 ioc->cujo20_bug = 1; 1170 res_ptr = ioc->res_map; 1171 idx = PDIR_INDEX(iovp) >> 3; 1172 1173 while (idx < ioc->res_size) { 1174 res_ptr[idx] |= 0xff; 1175 idx += PDIR_INDEX(CUJO_20_STEP) >> 3; 1176 } 1177 } 1178 1179 #if 0 1180 /* GRANT - is this needed for U2 or not? */ 1181 1182 /* 1183 ** Get the size of the I/O TLB for this I/O MMU. 1184 ** 1185 ** If spa_shift is non-zero (ie probably U2), 1186 ** then calculate the I/O TLB size using spa_shift. 1187 ** 1188 ** Otherwise we are supposed to get the IODC entry point ENTRY TLB 1189 ** and execute it. However, both U2 and Uturn firmware supplies spa_shift. 1190 ** I think only Java (K/D/R-class too?) systems don't do this. 1191 */ 1192 static int 1193 ccio_get_iotlb_size(struct parisc_device *dev) 1194 { 1195 if (dev->spa_shift == 0) { 1196 panic("%s() : Can't determine I/O TLB size.\n", __func__); 1197 } 1198 return (1 << dev->spa_shift); 1199 } 1200 #else 1201 1202 /* Uturn supports 256 TLB entries */ 1203 #define CCIO_CHAINID_SHIFT 8 1204 #define CCIO_CHAINID_MASK 0xff 1205 #endif /* 0 */ 1206 1207 /* We *can't* support JAVA (T600). Venture there at your own risk. */ 1208 static const struct parisc_device_id ccio_tbl[] __initconst = { 1209 { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */ 1210 { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */ 1211 { 0, } 1212 }; 1213 1214 static int ccio_probe(struct parisc_device *dev); 1215 1216 static struct parisc_driver ccio_driver __refdata = { 1217 .name = "ccio", 1218 .id_table = ccio_tbl, 1219 .probe = ccio_probe, 1220 }; 1221 1222 /** 1223 * ccio_ioc_init - Initialize the I/O Controller 1224 * @ioc: The I/O Controller. 1225 * 1226 * Initialize the I/O Controller which includes setting up the 1227 * I/O Page Directory, the resource map, and initalizing the 1228 * U2/Uturn chip into virtual mode. 1229 */ 1230 static void __init 1231 ccio_ioc_init(struct ioc *ioc) 1232 { 1233 int i; 1234 unsigned int iov_order; 1235 u32 iova_space_size; 1236 1237 /* 1238 ** Determine IOVA Space size from memory size. 1239 ** 1240 ** Ideally, PCI drivers would register the maximum number 1241 ** of DMA they can have outstanding for each device they 1242 ** own. Next best thing would be to guess how much DMA 1243 ** can be outstanding based on PCI Class/sub-class. Both 1244 ** methods still require some "extra" to support PCI 1245 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1246 */ 1247 1248 iova_space_size = (u32) (totalram_pages() / count_parisc_driver(&ccio_driver)); 1249 1250 /* limit IOVA space size to 1MB-1GB */ 1251 1252 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1253 iova_space_size = 1 << (20 - PAGE_SHIFT); 1254 #ifdef __LP64__ 1255 } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1256 iova_space_size = 1 << (30 - PAGE_SHIFT); 1257 #endif 1258 } 1259 1260 /* 1261 ** iova space must be log2() in size. 1262 ** thus, pdir/res_map will also be log2(). 1263 */ 1264 1265 /* We could use larger page sizes in order to *decrease* the number 1266 ** of mappings needed. (ie 8k pages means 1/2 the mappings). 1267 ** 1268 ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either 1269 ** since the pages must also be physically contiguous - typically 1270 ** this is the case under linux." 1271 */ 1272 1273 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1274 1275 /* iova_space_size is now bytes, not pages */ 1276 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1277 1278 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1279 1280 BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */ 1281 1282 /* Verify it's a power of two */ 1283 BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT)); 1284 1285 DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n", 1286 __func__, ioc->ioc_regs, 1287 (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT), 1288 iova_space_size>>20, 1289 iov_order + PAGE_SHIFT); 1290 1291 ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL, 1292 get_order(ioc->pdir_size)); 1293 if(NULL == ioc->pdir_base) { 1294 panic("%s() could not allocate I/O Page Table\n", __func__); 1295 } 1296 memset(ioc->pdir_base, 0, ioc->pdir_size); 1297 1298 BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base); 1299 DBG_INIT(" base %p\n", ioc->pdir_base); 1300 1301 /* resource map size dictated by pdir_size */ 1302 ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3; 1303 DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); 1304 1305 ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL, 1306 get_order(ioc->res_size)); 1307 if(NULL == ioc->res_map) { 1308 panic("%s() could not allocate resource map\n", __func__); 1309 } 1310 memset(ioc->res_map, 0, ioc->res_size); 1311 1312 /* Initialize the res_hint to 16 */ 1313 ioc->res_hint = 16; 1314 1315 /* Initialize the spinlock */ 1316 spin_lock_init(&ioc->res_lock); 1317 1318 /* 1319 ** Chainid is the upper most bits of an IOVP used to determine 1320 ** which TLB entry an IOVP will use. 1321 */ 1322 ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT; 1323 DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift); 1324 1325 /* 1326 ** Initialize IOA hardware 1327 */ 1328 WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift, 1329 &ioc->ioc_regs->io_chain_id_mask); 1330 1331 WRITE_U32(virt_to_phys(ioc->pdir_base), 1332 &ioc->ioc_regs->io_pdir_base); 1333 1334 /* 1335 ** Go to "Virtual Mode" 1336 */ 1337 WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control); 1338 1339 /* 1340 ** Initialize all I/O TLB entries to 0 (Valid bit off). 1341 */ 1342 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m); 1343 WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l); 1344 1345 for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) { 1346 WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)), 1347 &ioc->ioc_regs->io_command); 1348 } 1349 } 1350 1351 static void __init 1352 ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr) 1353 { 1354 int result; 1355 1356 res->parent = NULL; 1357 res->flags = IORESOURCE_MEM; 1358 /* 1359 * bracing ((signed) ...) are required for 64bit kernel because 1360 * we only want to sign extend the lower 16 bits of the register. 1361 * The upper 16-bits of range registers are hardcoded to 0xffff. 1362 */ 1363 res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16); 1364 res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1); 1365 res->name = name; 1366 /* 1367 * Check if this MMIO range is disable 1368 */ 1369 if (res->end + 1 == res->start) 1370 return; 1371 1372 /* On some platforms (e.g. K-Class), we have already registered 1373 * resources for devices reported by firmware. Some are children 1374 * of ccio. 1375 * "insert" ccio ranges in the mmio hierarchy (/proc/iomem). 1376 */ 1377 result = insert_resource(&iomem_resource, res); 1378 if (result < 0) { 1379 printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n", 1380 __func__, (unsigned long)res->start, (unsigned long)res->end); 1381 } 1382 } 1383 1384 static void __init ccio_init_resources(struct ioc *ioc) 1385 { 1386 struct resource *res = ioc->mmio_region; 1387 char *name = kmalloc(14, GFP_KERNEL); 1388 1389 snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path); 1390 1391 ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low); 1392 ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv); 1393 } 1394 1395 static int new_ioc_area(struct resource *res, unsigned long size, 1396 unsigned long min, unsigned long max, unsigned long align) 1397 { 1398 if (max <= min) 1399 return -EBUSY; 1400 1401 res->start = (max - size + 1) &~ (align - 1); 1402 res->end = res->start + size; 1403 1404 /* We might be trying to expand the MMIO range to include 1405 * a child device that has already registered it's MMIO space. 1406 * Use "insert" instead of request_resource(). 1407 */ 1408 if (!insert_resource(&iomem_resource, res)) 1409 return 0; 1410 1411 return new_ioc_area(res, size, min, max - size, align); 1412 } 1413 1414 static int expand_ioc_area(struct resource *res, unsigned long size, 1415 unsigned long min, unsigned long max, unsigned long align) 1416 { 1417 unsigned long start, len; 1418 1419 if (!res->parent) 1420 return new_ioc_area(res, size, min, max, align); 1421 1422 start = (res->start - size) &~ (align - 1); 1423 len = res->end - start + 1; 1424 if (start >= min) { 1425 if (!adjust_resource(res, start, len)) 1426 return 0; 1427 } 1428 1429 start = res->start; 1430 len = ((size + res->end + align) &~ (align - 1)) - start; 1431 if (start + len <= max) { 1432 if (!adjust_resource(res, start, len)) 1433 return 0; 1434 } 1435 1436 return -EBUSY; 1437 } 1438 1439 /* 1440 * Dino calls this function. Beware that we may get called on systems 1441 * which have no IOC (725, B180, C160L, etc) but do have a Dino. 1442 * So it's legal to find no parent IOC. 1443 * 1444 * Some other issues: one of the resources in the ioc may be unassigned. 1445 */ 1446 int ccio_allocate_resource(const struct parisc_device *dev, 1447 struct resource *res, unsigned long size, 1448 unsigned long min, unsigned long max, unsigned long align) 1449 { 1450 struct resource *parent = &iomem_resource; 1451 struct ioc *ioc = ccio_get_iommu(dev); 1452 if (!ioc) 1453 goto out; 1454 1455 parent = ioc->mmio_region; 1456 if (parent->parent && 1457 !allocate_resource(parent, res, size, min, max, align, NULL, NULL)) 1458 return 0; 1459 1460 if ((parent + 1)->parent && 1461 !allocate_resource(parent + 1, res, size, min, max, align, 1462 NULL, NULL)) 1463 return 0; 1464 1465 if (!expand_ioc_area(parent, size, min, max, align)) { 1466 __raw_writel(((parent->start)>>16) | 0xffff0000, 1467 &ioc->ioc_regs->io_io_low); 1468 __raw_writel(((parent->end)>>16) | 0xffff0000, 1469 &ioc->ioc_regs->io_io_high); 1470 } else if (!expand_ioc_area(parent + 1, size, min, max, align)) { 1471 parent++; 1472 __raw_writel(((parent->start)>>16) | 0xffff0000, 1473 &ioc->ioc_regs->io_io_low_hv); 1474 __raw_writel(((parent->end)>>16) | 0xffff0000, 1475 &ioc->ioc_regs->io_io_high_hv); 1476 } else { 1477 return -EBUSY; 1478 } 1479 1480 out: 1481 return allocate_resource(parent, res, size, min, max, align, NULL,NULL); 1482 } 1483 1484 int ccio_request_resource(const struct parisc_device *dev, 1485 struct resource *res) 1486 { 1487 struct resource *parent; 1488 struct ioc *ioc = ccio_get_iommu(dev); 1489 1490 if (!ioc) { 1491 parent = &iomem_resource; 1492 } else if ((ioc->mmio_region->start <= res->start) && 1493 (res->end <= ioc->mmio_region->end)) { 1494 parent = ioc->mmio_region; 1495 } else if (((ioc->mmio_region + 1)->start <= res->start) && 1496 (res->end <= (ioc->mmio_region + 1)->end)) { 1497 parent = ioc->mmio_region + 1; 1498 } else { 1499 return -EBUSY; 1500 } 1501 1502 /* "transparent" bus bridges need to register MMIO resources 1503 * firmware assigned them. e.g. children of hppb.c (e.g. K-class) 1504 * registered their resources in the PDC "bus walk" (See 1505 * arch/parisc/kernel/inventory.c). 1506 */ 1507 return insert_resource(parent, res); 1508 } 1509 1510 /** 1511 * ccio_probe - Determine if ccio should claim this device. 1512 * @dev: The device which has been found 1513 * 1514 * Determine if ccio should claim this chip (return 0) or not (return 1). 1515 * If so, initialize the chip and tell other partners in crime they 1516 * have work to do. 1517 */ 1518 static int __init ccio_probe(struct parisc_device *dev) 1519 { 1520 int i; 1521 struct ioc *ioc, **ioc_p = &ioc_list; 1522 struct pci_hba_data *hba; 1523 1524 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); 1525 if (ioc == NULL) { 1526 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); 1527 return -ENOMEM; 1528 } 1529 1530 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; 1531 1532 printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name, 1533 (unsigned long)dev->hpa.start); 1534 1535 for (i = 0; i < ioc_count; i++) { 1536 ioc_p = &(*ioc_p)->next; 1537 } 1538 *ioc_p = ioc; 1539 1540 ioc->hw_path = dev->hw_path; 1541 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); 1542 if (!ioc->ioc_regs) { 1543 kfree(ioc); 1544 return -ENOMEM; 1545 } 1546 ccio_ioc_init(ioc); 1547 ccio_init_resources(ioc); 1548 hppa_dma_ops = &ccio_ops; 1549 1550 hba = kzalloc(sizeof(*hba), GFP_KERNEL); 1551 /* if this fails, no I/O cards will work, so may as well bug */ 1552 BUG_ON(hba == NULL); 1553 1554 hba->iommu = ioc; 1555 dev->dev.platform_data = hba; 1556 1557 #ifdef CONFIG_PROC_FS 1558 if (ioc_count == 0) { 1559 proc_create_single(MODULE_NAME, 0, proc_runway_root, 1560 ccio_proc_info); 1561 proc_create_single(MODULE_NAME"-bitmap", 0, proc_runway_root, 1562 ccio_proc_bitmap_info); 1563 } 1564 #endif 1565 ioc_count++; 1566 return 0; 1567 } 1568 1569 /** 1570 * ccio_init - ccio initialization procedure. 1571 * 1572 * Register this driver. 1573 */ 1574 void __init ccio_init(void) 1575 { 1576 register_parisc_driver(&ccio_driver); 1577 } 1578 1579