1 /* 2 * Rockchip eFuse Driver 3 * 4 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 5 * Author: Caesar Wang <wxt@rock-chips.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/io.h> 21 #include <linux/module.h> 22 #include <linux/nvmem-provider.h> 23 #include <linux/slab.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 28 #define RK3288_A_SHIFT 6 29 #define RK3288_A_MASK 0x3ff 30 #define RK3288_PGENB BIT(3) 31 #define RK3288_LOAD BIT(2) 32 #define RK3288_STROBE BIT(1) 33 #define RK3288_CSB BIT(0) 34 35 #define RK3399_A_SHIFT 16 36 #define RK3399_A_MASK 0x3ff 37 #define RK3399_NBYTES 4 38 #define RK3399_STROBSFTSEL BIT(9) 39 #define RK3399_RSB BIT(7) 40 #define RK3399_PD BIT(5) 41 #define RK3399_PGENB BIT(3) 42 #define RK3399_LOAD BIT(2) 43 #define RK3399_STROBE BIT(1) 44 #define RK3399_CSB BIT(0) 45 46 #define REG_EFUSE_CTRL 0x0000 47 #define REG_EFUSE_DOUT 0x0004 48 49 struct rockchip_efuse_chip { 50 struct device *dev; 51 void __iomem *base; 52 struct clk *clk; 53 }; 54 55 static int rockchip_rk3288_efuse_read(void *context, unsigned int offset, 56 void *val, size_t bytes) 57 { 58 struct rockchip_efuse_chip *efuse = context; 59 u8 *buf = val; 60 int ret; 61 62 ret = clk_prepare_enable(efuse->clk); 63 if (ret < 0) { 64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 65 return ret; 66 } 67 68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); 69 udelay(1); 70 while (bytes--) { 71 writel(readl(efuse->base + REG_EFUSE_CTRL) & 72 (~(RK3288_A_MASK << RK3288_A_SHIFT)), 73 efuse->base + REG_EFUSE_CTRL); 74 writel(readl(efuse->base + REG_EFUSE_CTRL) | 75 ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), 76 efuse->base + REG_EFUSE_CTRL); 77 udelay(1); 78 writel(readl(efuse->base + REG_EFUSE_CTRL) | 79 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); 80 udelay(1); 81 *buf++ = readb(efuse->base + REG_EFUSE_DOUT); 82 writel(readl(efuse->base + REG_EFUSE_CTRL) & 83 (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); 84 udelay(1); 85 } 86 87 /* Switch to standby mode */ 88 writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); 89 90 clk_disable_unprepare(efuse->clk); 91 92 return 0; 93 } 94 95 static int rockchip_rk3399_efuse_read(void *context, unsigned int offset, 96 void *val, size_t bytes) 97 { 98 struct rockchip_efuse_chip *efuse = context; 99 unsigned int addr_start, addr_end, addr_offset, addr_len; 100 u32 out_value; 101 u8 *buf; 102 int ret, i = 0; 103 104 ret = clk_prepare_enable(efuse->clk); 105 if (ret < 0) { 106 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 107 return ret; 108 } 109 110 addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES; 111 addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES; 112 addr_offset = offset % RK3399_NBYTES; 113 addr_len = addr_end - addr_start; 114 115 buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL); 116 if (!buf) { 117 clk_disable_unprepare(efuse->clk); 118 return -ENOMEM; 119 } 120 121 writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, 122 efuse->base + REG_EFUSE_CTRL); 123 udelay(1); 124 while (addr_len--) { 125 writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | 126 ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), 127 efuse->base + REG_EFUSE_CTRL); 128 udelay(1); 129 out_value = readl(efuse->base + REG_EFUSE_DOUT); 130 writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), 131 efuse->base + REG_EFUSE_CTRL); 132 udelay(1); 133 134 memcpy(&buf[i], &out_value, RK3399_NBYTES); 135 i += RK3399_NBYTES; 136 } 137 138 /* Switch to standby mode */ 139 writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL); 140 141 memcpy(val, buf + addr_offset, bytes); 142 143 kfree(buf); 144 145 clk_disable_unprepare(efuse->clk); 146 147 return 0; 148 } 149 150 static struct nvmem_config econfig = { 151 .name = "rockchip-efuse", 152 .owner = THIS_MODULE, 153 .stride = 1, 154 .word_size = 1, 155 .read_only = true, 156 }; 157 158 static const struct of_device_id rockchip_efuse_match[] = { 159 /* deprecated but kept around for dts binding compatibility */ 160 { 161 .compatible = "rockchip,rockchip-efuse", 162 .data = (void *)&rockchip_rk3288_efuse_read, 163 }, 164 { 165 .compatible = "rockchip,rk3066a-efuse", 166 .data = (void *)&rockchip_rk3288_efuse_read, 167 }, 168 { 169 .compatible = "rockchip,rk3188-efuse", 170 .data = (void *)&rockchip_rk3288_efuse_read, 171 }, 172 { 173 .compatible = "rockchip,rk322x-efuse", 174 .data = (void *)&rockchip_rk3288_efuse_read, 175 }, 176 { 177 .compatible = "rockchip,rk3288-efuse", 178 .data = (void *)&rockchip_rk3288_efuse_read, 179 }, 180 { 181 .compatible = "rockchip,rk3399-efuse", 182 .data = (void *)&rockchip_rk3399_efuse_read, 183 }, 184 { /* sentinel */}, 185 }; 186 MODULE_DEVICE_TABLE(of, rockchip_efuse_match); 187 188 static int rockchip_efuse_probe(struct platform_device *pdev) 189 { 190 struct resource *res; 191 struct nvmem_device *nvmem; 192 struct rockchip_efuse_chip *efuse; 193 const struct of_device_id *match; 194 struct device *dev = &pdev->dev; 195 196 match = of_match_device(dev->driver->of_match_table, dev); 197 if (!match || !match->data) { 198 dev_err(dev, "failed to get match data\n"); 199 return -EINVAL; 200 } 201 202 efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip), 203 GFP_KERNEL); 204 if (!efuse) 205 return -ENOMEM; 206 207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 208 efuse->base = devm_ioremap_resource(&pdev->dev, res); 209 if (IS_ERR(efuse->base)) 210 return PTR_ERR(efuse->base); 211 212 efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse"); 213 if (IS_ERR(efuse->clk)) 214 return PTR_ERR(efuse->clk); 215 216 efuse->dev = &pdev->dev; 217 econfig.size = resource_size(res); 218 econfig.reg_read = match->data; 219 econfig.priv = efuse; 220 econfig.dev = efuse->dev; 221 nvmem = nvmem_register(&econfig); 222 if (IS_ERR(nvmem)) 223 return PTR_ERR(nvmem); 224 225 platform_set_drvdata(pdev, nvmem); 226 227 return 0; 228 } 229 230 static int rockchip_efuse_remove(struct platform_device *pdev) 231 { 232 struct nvmem_device *nvmem = platform_get_drvdata(pdev); 233 234 return nvmem_unregister(nvmem); 235 } 236 237 static struct platform_driver rockchip_efuse_driver = { 238 .probe = rockchip_efuse_probe, 239 .remove = rockchip_efuse_remove, 240 .driver = { 241 .name = "rockchip-efuse", 242 .of_match_table = rockchip_efuse_match, 243 }, 244 }; 245 246 module_platform_driver(rockchip_efuse_driver); 247 MODULE_DESCRIPTION("rockchip_efuse driver"); 248 MODULE_LICENSE("GPL v2"); 249