15b497af4SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 203a69568SZhengShunQian /* 303a69568SZhengShunQian * Rockchip eFuse Driver 403a69568SZhengShunQian * 503a69568SZhengShunQian * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 603a69568SZhengShunQian * Author: Caesar Wang <wxt@rock-chips.com> 703a69568SZhengShunQian */ 803a69568SZhengShunQian 9c37ff3fbSCaesar Wang #include <linux/clk.h> 10c37ff3fbSCaesar Wang #include <linux/delay.h> 1103a69568SZhengShunQian #include <linux/device.h> 1203a69568SZhengShunQian #include <linux/io.h> 1303a69568SZhengShunQian #include <linux/module.h> 14c37ff3fbSCaesar Wang #include <linux/nvmem-provider.h> 15c37ff3fbSCaesar Wang #include <linux/slab.h> 1603a69568SZhengShunQian #include <linux/of.h> 1702baff32SFinley Xiao #include <linux/of_platform.h> 18c37ff3fbSCaesar Wang #include <linux/platform_device.h> 1903a69568SZhengShunQian 2002baff32SFinley Xiao #define RK3288_A_SHIFT 6 2102baff32SFinley Xiao #define RK3288_A_MASK 0x3ff 2202baff32SFinley Xiao #define RK3288_PGENB BIT(3) 2302baff32SFinley Xiao #define RK3288_LOAD BIT(2) 2402baff32SFinley Xiao #define RK3288_STROBE BIT(1) 2502baff32SFinley Xiao #define RK3288_CSB BIT(0) 2602baff32SFinley Xiao 279a479b08SFinley Xiao #define RK3328_SECURE_SIZES 96 289a479b08SFinley Xiao #define RK3328_INT_STATUS 0x0018 299a479b08SFinley Xiao #define RK3328_DOUT 0x0020 309a479b08SFinley Xiao #define RK3328_AUTO_CTRL 0x0024 319a479b08SFinley Xiao #define RK3328_INT_FINISH BIT(0) 329a479b08SFinley Xiao #define RK3328_AUTO_ENB BIT(0) 339a479b08SFinley Xiao #define RK3328_AUTO_RD BIT(1) 349a479b08SFinley Xiao 3502baff32SFinley Xiao #define RK3399_A_SHIFT 16 3602baff32SFinley Xiao #define RK3399_A_MASK 0x3ff 3702baff32SFinley Xiao #define RK3399_NBYTES 4 3802baff32SFinley Xiao #define RK3399_STROBSFTSEL BIT(9) 3902baff32SFinley Xiao #define RK3399_RSB BIT(7) 4002baff32SFinley Xiao #define RK3399_PD BIT(5) 4102baff32SFinley Xiao #define RK3399_PGENB BIT(3) 4202baff32SFinley Xiao #define RK3399_LOAD BIT(2) 4302baff32SFinley Xiao #define RK3399_STROBE BIT(1) 4402baff32SFinley Xiao #define RK3399_CSB BIT(0) 4503a69568SZhengShunQian 4603a69568SZhengShunQian #define REG_EFUSE_CTRL 0x0000 4703a69568SZhengShunQian #define REG_EFUSE_DOUT 0x0004 4803a69568SZhengShunQian 49c37ff3fbSCaesar Wang struct rockchip_efuse_chip { 5003a69568SZhengShunQian struct device *dev; 5103a69568SZhengShunQian void __iomem *base; 52c37ff3fbSCaesar Wang struct clk *clk; 5303a69568SZhengShunQian }; 5403a69568SZhengShunQian 5502baff32SFinley Xiao static int rockchip_rk3288_efuse_read(void *context, unsigned int offset, 56cc907553SSrinivas Kandagatla void *val, size_t bytes) 5703a69568SZhengShunQian { 58c37ff3fbSCaesar Wang struct rockchip_efuse_chip *efuse = context; 5903a69568SZhengShunQian u8 *buf = val; 6003a69568SZhengShunQian int ret; 6103a69568SZhengShunQian 62c37ff3fbSCaesar Wang ret = clk_prepare_enable(efuse->clk); 6303a69568SZhengShunQian if (ret < 0) { 64c37ff3fbSCaesar Wang dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 6503a69568SZhengShunQian return ret; 6603a69568SZhengShunQian } 6703a69568SZhengShunQian 6802baff32SFinley Xiao writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); 6903a69568SZhengShunQian udelay(1); 70cc907553SSrinivas Kandagatla while (bytes--) { 71c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) & 7202baff32SFinley Xiao (~(RK3288_A_MASK << RK3288_A_SHIFT)), 73c37ff3fbSCaesar Wang efuse->base + REG_EFUSE_CTRL); 74c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) | 7502baff32SFinley Xiao ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), 76c37ff3fbSCaesar Wang efuse->base + REG_EFUSE_CTRL); 7703a69568SZhengShunQian udelay(1); 78c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) | 7902baff32SFinley Xiao RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); 8003a69568SZhengShunQian udelay(1); 81c37ff3fbSCaesar Wang *buf++ = readb(efuse->base + REG_EFUSE_DOUT); 82c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) & 8302baff32SFinley Xiao (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); 8403a69568SZhengShunQian udelay(1); 8503a69568SZhengShunQian } 8603a69568SZhengShunQian 8703a69568SZhengShunQian /* Switch to standby mode */ 8802baff32SFinley Xiao writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); 8902baff32SFinley Xiao 9002baff32SFinley Xiao clk_disable_unprepare(efuse->clk); 9102baff32SFinley Xiao 9202baff32SFinley Xiao return 0; 9302baff32SFinley Xiao } 9402baff32SFinley Xiao 959a479b08SFinley Xiao static int rockchip_rk3328_efuse_read(void *context, unsigned int offset, 969a479b08SFinley Xiao void *val, size_t bytes) 979a479b08SFinley Xiao { 989a479b08SFinley Xiao struct rockchip_efuse_chip *efuse = context; 999a479b08SFinley Xiao unsigned int addr_start, addr_end, addr_offset, addr_len; 1009a479b08SFinley Xiao u32 out_value, status; 1019a479b08SFinley Xiao u8 *buf; 1029a479b08SFinley Xiao int ret, i = 0; 1039a479b08SFinley Xiao 1049a479b08SFinley Xiao ret = clk_prepare_enable(efuse->clk); 1059a479b08SFinley Xiao if (ret < 0) { 1069a479b08SFinley Xiao dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 1079a479b08SFinley Xiao return ret; 1089a479b08SFinley Xiao } 1099a479b08SFinley Xiao 1109a479b08SFinley Xiao /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */ 1119a479b08SFinley Xiao offset += RK3328_SECURE_SIZES; 1129a479b08SFinley Xiao addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES; 1139a479b08SFinley Xiao addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES; 1149a479b08SFinley Xiao addr_offset = offset % RK3399_NBYTES; 1159a479b08SFinley Xiao addr_len = addr_end - addr_start; 1169a479b08SFinley Xiao 1176396bb22SKees Cook buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)), 1186396bb22SKees Cook GFP_KERNEL); 1199a479b08SFinley Xiao if (!buf) { 1209a479b08SFinley Xiao ret = -ENOMEM; 1219a479b08SFinley Xiao goto nomem; 1229a479b08SFinley Xiao } 1239a479b08SFinley Xiao 1249a479b08SFinley Xiao while (addr_len--) { 1259a479b08SFinley Xiao writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | 1269a479b08SFinley Xiao ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), 1279a479b08SFinley Xiao efuse->base + RK3328_AUTO_CTRL); 1289a479b08SFinley Xiao udelay(4); 1299a479b08SFinley Xiao status = readl(efuse->base + RK3328_INT_STATUS); 1309a479b08SFinley Xiao if (!(status & RK3328_INT_FINISH)) { 1319a479b08SFinley Xiao ret = -EIO; 1329a479b08SFinley Xiao goto err; 1339a479b08SFinley Xiao } 1349a479b08SFinley Xiao out_value = readl(efuse->base + RK3328_DOUT); 1359a479b08SFinley Xiao writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS); 1369a479b08SFinley Xiao 1379a479b08SFinley Xiao memcpy(&buf[i], &out_value, RK3399_NBYTES); 1389a479b08SFinley Xiao i += RK3399_NBYTES; 1399a479b08SFinley Xiao } 1409a479b08SFinley Xiao 1419a479b08SFinley Xiao memcpy(val, buf + addr_offset, bytes); 1429a479b08SFinley Xiao err: 1439a479b08SFinley Xiao kfree(buf); 1449a479b08SFinley Xiao nomem: 1459a479b08SFinley Xiao clk_disable_unprepare(efuse->clk); 1469a479b08SFinley Xiao 1479a479b08SFinley Xiao return ret; 1489a479b08SFinley Xiao } 1499a479b08SFinley Xiao 15002baff32SFinley Xiao static int rockchip_rk3399_efuse_read(void *context, unsigned int offset, 15102baff32SFinley Xiao void *val, size_t bytes) 15202baff32SFinley Xiao { 15302baff32SFinley Xiao struct rockchip_efuse_chip *efuse = context; 15402baff32SFinley Xiao unsigned int addr_start, addr_end, addr_offset, addr_len; 15502baff32SFinley Xiao u32 out_value; 15602baff32SFinley Xiao u8 *buf; 15702baff32SFinley Xiao int ret, i = 0; 15802baff32SFinley Xiao 15902baff32SFinley Xiao ret = clk_prepare_enable(efuse->clk); 16002baff32SFinley Xiao if (ret < 0) { 16102baff32SFinley Xiao dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 16202baff32SFinley Xiao return ret; 16302baff32SFinley Xiao } 16402baff32SFinley Xiao 16502baff32SFinley Xiao addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES; 16602baff32SFinley Xiao addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES; 16702baff32SFinley Xiao addr_offset = offset % RK3399_NBYTES; 16802baff32SFinley Xiao addr_len = addr_end - addr_start; 16902baff32SFinley Xiao 1706396bb22SKees Cook buf = kzalloc(array3_size(addr_len, RK3399_NBYTES, sizeof(*buf)), 1716396bb22SKees Cook GFP_KERNEL); 17202baff32SFinley Xiao if (!buf) { 17302baff32SFinley Xiao clk_disable_unprepare(efuse->clk); 17402baff32SFinley Xiao return -ENOMEM; 17502baff32SFinley Xiao } 17602baff32SFinley Xiao 17702baff32SFinley Xiao writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, 17802baff32SFinley Xiao efuse->base + REG_EFUSE_CTRL); 17902baff32SFinley Xiao udelay(1); 18002baff32SFinley Xiao while (addr_len--) { 18102baff32SFinley Xiao writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | 18202baff32SFinley Xiao ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), 18302baff32SFinley Xiao efuse->base + REG_EFUSE_CTRL); 18402baff32SFinley Xiao udelay(1); 18502baff32SFinley Xiao out_value = readl(efuse->base + REG_EFUSE_DOUT); 18602baff32SFinley Xiao writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), 18702baff32SFinley Xiao efuse->base + REG_EFUSE_CTRL); 18802baff32SFinley Xiao udelay(1); 18902baff32SFinley Xiao 19002baff32SFinley Xiao memcpy(&buf[i], &out_value, RK3399_NBYTES); 19102baff32SFinley Xiao i += RK3399_NBYTES; 19202baff32SFinley Xiao } 19302baff32SFinley Xiao 19402baff32SFinley Xiao /* Switch to standby mode */ 19502baff32SFinley Xiao writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL); 19602baff32SFinley Xiao 19702baff32SFinley Xiao memcpy(val, buf + addr_offset, bytes); 19802baff32SFinley Xiao 19902baff32SFinley Xiao kfree(buf); 20003a69568SZhengShunQian 201c37ff3fbSCaesar Wang clk_disable_unprepare(efuse->clk); 20203a69568SZhengShunQian 20303a69568SZhengShunQian return 0; 20403a69568SZhengShunQian } 20503a69568SZhengShunQian 20603a69568SZhengShunQian static struct nvmem_config econfig = { 20703a69568SZhengShunQian .name = "rockchip-efuse", 208cc907553SSrinivas Kandagatla .stride = 1, 209cc907553SSrinivas Kandagatla .word_size = 1, 21003a69568SZhengShunQian .read_only = true, 21103a69568SZhengShunQian }; 21203a69568SZhengShunQian 21303a69568SZhengShunQian static const struct of_device_id rockchip_efuse_match[] = { 21402baff32SFinley Xiao /* deprecated but kept around for dts binding compatibility */ 21502baff32SFinley Xiao { 21602baff32SFinley Xiao .compatible = "rockchip,rockchip-efuse", 21702baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 21802baff32SFinley Xiao }, 21902baff32SFinley Xiao { 22002baff32SFinley Xiao .compatible = "rockchip,rk3066a-efuse", 22102baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 22202baff32SFinley Xiao }, 22302baff32SFinley Xiao { 22402baff32SFinley Xiao .compatible = "rockchip,rk3188-efuse", 22502baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 22602baff32SFinley Xiao }, 22702baff32SFinley Xiao { 228d6e4bd1bSFrank Wang .compatible = "rockchip,rk3228-efuse", 229820de1fbSFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 230820de1fbSFinley Xiao }, 231820de1fbSFinley Xiao { 23202baff32SFinley Xiao .compatible = "rockchip,rk3288-efuse", 23302baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 23402baff32SFinley Xiao }, 23502baff32SFinley Xiao { 2367a15cf2aSRomain Perier .compatible = "rockchip,rk3368-efuse", 2377a15cf2aSRomain Perier .data = (void *)&rockchip_rk3288_efuse_read, 2387a15cf2aSRomain Perier }, 2397a15cf2aSRomain Perier { 2409a479b08SFinley Xiao .compatible = "rockchip,rk3328-efuse", 2419a479b08SFinley Xiao .data = (void *)&rockchip_rk3328_efuse_read, 2429a479b08SFinley Xiao }, 2439a479b08SFinley Xiao { 24402baff32SFinley Xiao .compatible = "rockchip,rk3399-efuse", 24502baff32SFinley Xiao .data = (void *)&rockchip_rk3399_efuse_read, 24602baff32SFinley Xiao }, 24703a69568SZhengShunQian { /* sentinel */}, 24803a69568SZhengShunQian }; 24903a69568SZhengShunQian MODULE_DEVICE_TABLE(of, rockchip_efuse_match); 25003a69568SZhengShunQian 2517e532f79Skbuild test robot static int rockchip_efuse_probe(struct platform_device *pdev) 25203a69568SZhengShunQian { 25303a69568SZhengShunQian struct resource *res; 25403a69568SZhengShunQian struct nvmem_device *nvmem; 255c37ff3fbSCaesar Wang struct rockchip_efuse_chip *efuse; 2567b4e76cbSAndrey Smirnov const void *data; 25702baff32SFinley Xiao struct device *dev = &pdev->dev; 25802baff32SFinley Xiao 2597b4e76cbSAndrey Smirnov data = of_device_get_match_data(dev); 2607b4e76cbSAndrey Smirnov if (!data) { 26102baff32SFinley Xiao dev_err(dev, "failed to get match data\n"); 26202baff32SFinley Xiao return -EINVAL; 26302baff32SFinley Xiao } 264c37ff3fbSCaesar Wang 265e84d1f96SAndrey Smirnov efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip), 266c37ff3fbSCaesar Wang GFP_KERNEL); 267c37ff3fbSCaesar Wang if (!efuse) 268c37ff3fbSCaesar Wang return -ENOMEM; 26903a69568SZhengShunQian 270*94904db2SYangtao Li efuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 271c37ff3fbSCaesar Wang if (IS_ERR(efuse->base)) 272c37ff3fbSCaesar Wang return PTR_ERR(efuse->base); 27303a69568SZhengShunQian 274e84d1f96SAndrey Smirnov efuse->clk = devm_clk_get(dev, "pclk_efuse"); 275c37ff3fbSCaesar Wang if (IS_ERR(efuse->clk)) 276c37ff3fbSCaesar Wang return PTR_ERR(efuse->clk); 27703a69568SZhengShunQian 278e84d1f96SAndrey Smirnov efuse->dev = dev; 27932277723SFinley Xiao if (of_property_read_u32(dev->of_node, "rockchip,efuse-size", 28032277723SFinley Xiao &econfig.size)) 281cc907553SSrinivas Kandagatla econfig.size = resource_size(res); 2827b4e76cbSAndrey Smirnov econfig.reg_read = data; 283cc907553SSrinivas Kandagatla econfig.priv = efuse; 284c37ff3fbSCaesar Wang econfig.dev = efuse->dev; 285f4bec713SAndrey Smirnov nvmem = devm_nvmem_register(dev, &econfig); 28603a69568SZhengShunQian 287f4bec713SAndrey Smirnov return PTR_ERR_OR_ZERO(nvmem); 28803a69568SZhengShunQian } 28903a69568SZhengShunQian 29003a69568SZhengShunQian static struct platform_driver rockchip_efuse_driver = { 29103a69568SZhengShunQian .probe = rockchip_efuse_probe, 29203a69568SZhengShunQian .driver = { 29303a69568SZhengShunQian .name = "rockchip-efuse", 29403a69568SZhengShunQian .of_match_table = rockchip_efuse_match, 29503a69568SZhengShunQian }, 29603a69568SZhengShunQian }; 29703a69568SZhengShunQian 29803a69568SZhengShunQian module_platform_driver(rockchip_efuse_driver); 29903a69568SZhengShunQian MODULE_DESCRIPTION("rockchip_efuse driver"); 30003a69568SZhengShunQian MODULE_LICENSE("GPL v2"); 301