1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i.MX6 OCOTP fusebox driver 4 * 5 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 6 * 7 * Copyright 2019 NXP 8 * 9 * Based on the barebox ocotp driver, 10 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, 11 * Orex Computed Radiography 12 * 13 * Write support based on the fsl_otp driver, 14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/device.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/nvmem-provider.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <linux/delay.h> 27 28 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the 29 * OTP Bank0 Word0 30 */ 31 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr 32 * of two consecutive OTP words. 33 */ 34 35 #define IMX_OCOTP_ADDR_CTRL 0x0000 36 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004 37 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008 38 #define IMX_OCOTP_ADDR_TIMING 0x0010 39 #define IMX_OCOTP_ADDR_DATA0 0x0020 40 #define IMX_OCOTP_ADDR_DATA1 0x0030 41 #define IMX_OCOTP_ADDR_DATA2 0x0040 42 #define IMX_OCOTP_ADDR_DATA3 0x0050 43 44 #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF 45 #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 46 #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 47 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 48 49 #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF 50 #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200 51 #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400 52 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800 53 54 #define IMX_OCOTP_BM_CTRL_DEFAULT \ 55 { \ 56 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \ 57 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \ 58 .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \ 59 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\ 60 } 61 62 #define IMX_OCOTP_BM_CTRL_8MP \ 63 { \ 64 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \ 65 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \ 66 .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \ 67 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\ 68 } 69 70 #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ 71 #define TIMING_STROBE_READ_NS 37 /* Min time before read */ 72 #define TIMING_RELAX_NS 17 73 #define DEF_FSOURCE 1001 /* > 1000 ns */ 74 #define DEF_STROBE_PROG 10000 /* IPG clocks */ 75 #define IMX_OCOTP_WR_UNLOCK 0x3E770000 76 #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA 77 78 static DEFINE_MUTEX(ocotp_mutex); 79 80 struct ocotp_priv { 81 struct device *dev; 82 struct clk *clk; 83 void __iomem *base; 84 const struct ocotp_params *params; 85 struct nvmem_config *config; 86 }; 87 88 struct ocotp_ctrl_reg { 89 u32 bm_addr; 90 u32 bm_busy; 91 u32 bm_error; 92 u32 bm_rel_shadows; 93 }; 94 95 struct ocotp_params { 96 unsigned int nregs; 97 unsigned int bank_address_words; 98 void (*set_timing)(struct ocotp_priv *priv); 99 struct ocotp_ctrl_reg ctrl; 100 }; 101 102 static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) 103 { 104 int count; 105 u32 c, mask; 106 u32 bm_ctrl_busy, bm_ctrl_error; 107 void __iomem *base = priv->base; 108 109 bm_ctrl_busy = priv->params->ctrl.bm_busy; 110 bm_ctrl_error = priv->params->ctrl.bm_error; 111 112 mask = bm_ctrl_busy | bm_ctrl_error | flags; 113 114 for (count = 10000; count >= 0; count--) { 115 c = readl(base + IMX_OCOTP_ADDR_CTRL); 116 if (!(c & mask)) 117 break; 118 cpu_relax(); 119 } 120 121 if (count < 0) { 122 /* HW_OCOTP_CTRL[ERROR] will be set under the following 123 * conditions: 124 * - A write is performed to a shadow register during a shadow 125 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is 126 * set. In addition, the contents of the shadow register shall 127 * not be updated. 128 * - A write is performed to a shadow register which has been 129 * locked. 130 * - A read is performed to from a shadow register which has 131 * been read locked. 132 * - A program is performed to a fuse word which has been locked 133 * - A read is performed to from a fuse word which has been read 134 * locked. 135 */ 136 if (c & bm_ctrl_error) 137 return -EPERM; 138 return -ETIMEDOUT; 139 } 140 141 return 0; 142 } 143 144 static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv) 145 { 146 u32 c, bm_ctrl_error; 147 void __iomem *base = priv->base; 148 149 bm_ctrl_error = priv->params->ctrl.bm_error; 150 151 c = readl(base + IMX_OCOTP_ADDR_CTRL); 152 if (!(c & bm_ctrl_error)) 153 return; 154 155 writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR); 156 } 157 158 static int imx_ocotp_read(void *context, unsigned int offset, 159 void *val, size_t bytes) 160 { 161 struct ocotp_priv *priv = context; 162 unsigned int count; 163 u8 *buf, *p; 164 int i, ret; 165 u32 index, num_bytes; 166 167 index = offset >> 2; 168 num_bytes = round_up((offset % 4) + bytes, 4); 169 count = num_bytes >> 2; 170 171 if (count > (priv->params->nregs - index)) 172 count = priv->params->nregs - index; 173 174 p = kzalloc(num_bytes, GFP_KERNEL); 175 if (!p) 176 return -ENOMEM; 177 178 mutex_lock(&ocotp_mutex); 179 180 buf = p; 181 182 ret = clk_prepare_enable(priv->clk); 183 if (ret < 0) { 184 mutex_unlock(&ocotp_mutex); 185 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); 186 kfree(p); 187 return ret; 188 } 189 190 ret = imx_ocotp_wait_for_busy(priv, 0); 191 if (ret < 0) { 192 dev_err(priv->dev, "timeout during read setup\n"); 193 goto read_end; 194 } 195 196 for (i = index; i < (index + count); i++) { 197 *(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + 198 i * IMX_OCOTP_OFFSET_PER_WORD); 199 200 /* 47.3.1.2 201 * For "read locked" registers 0xBADABADA will be returned and 202 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by 203 * software before any new write, read or reload access can be 204 * issued 205 */ 206 if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL) 207 imx_ocotp_clr_err_if_set(priv); 208 209 buf += 4; 210 } 211 212 index = offset % 4; 213 memcpy(val, &p[index], bytes); 214 215 read_end: 216 clk_disable_unprepare(priv->clk); 217 mutex_unlock(&ocotp_mutex); 218 219 kfree(p); 220 221 return ret; 222 } 223 224 static int imx_ocotp_cell_pp(void *context, const char *id, int index, 225 unsigned int offset, void *data, size_t bytes) 226 { 227 u8 *buf = data; 228 int i; 229 230 /* Deal with some post processing of nvmem cell data */ 231 if (id && !strcmp(id, "mac-address")) 232 for (i = 0; i < bytes / 2; i++) 233 swap(buf[i], buf[bytes - i - 1]); 234 235 return 0; 236 } 237 238 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) 239 { 240 unsigned long clk_rate; 241 unsigned long strobe_read, relax, strobe_prog; 242 u32 timing; 243 244 /* 47.3.1.3.1 245 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] 246 * fields with timing values to match the current frequency of the 247 * ipg_clk. OTP writes will work at maximum bus frequencies as long 248 * as the HW_OCOTP_TIMING parameters are set correctly. 249 * 250 * Note: there are minimum timings required to ensure an OTP fuse burns 251 * correctly that are independent of the ipg_clk. Those values are not 252 * formally documented anywhere however, working from the minimum 253 * timings given in u-boot we can say: 254 * 255 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 256 * microseconds feels about right as representative of a minimum time 257 * to physically burn out a fuse. 258 * 259 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before 260 * performing another read is 37 nanoseconds 261 * 262 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum 263 * timing is not entirely clear the documentation says "This 264 * count value specifies the time to add to all default timing 265 * parameters other than the Tpgm and Trd. It is given in number 266 * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG 267 * and STROBE_READ respectively. What the other timing parameters 268 * are though, is not specified. Experience shows a zero RELAX 269 * value will mess up a re-load of the shadow registers post OTP 270 * burn. 271 */ 272 clk_rate = clk_get_rate(priv->clk); 273 274 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; 275 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, 276 1000000000); 277 strobe_read += 2 * (relax + 1) - 1; 278 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, 279 1000000); 280 strobe_prog += 2 * (relax + 1) - 1; 281 282 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; 283 timing |= strobe_prog & 0x00000FFF; 284 timing |= (relax << 12) & 0x0000F000; 285 timing |= (strobe_read << 16) & 0x003F0000; 286 287 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); 288 } 289 290 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) 291 { 292 unsigned long clk_rate; 293 u64 fsource, strobe_prog; 294 u32 timing; 295 296 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 297 * 6.4.3.3 298 */ 299 clk_rate = clk_get_rate(priv->clk); 300 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, 301 NSEC_PER_SEC) + 1; 302 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, 303 NSEC_PER_SEC) + 1; 304 305 timing = strobe_prog & 0x00000FFF; 306 timing |= (fsource << 12) & 0x000FF000; 307 308 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); 309 } 310 311 static int imx_ocotp_write(void *context, unsigned int offset, void *val, 312 size_t bytes) 313 { 314 struct ocotp_priv *priv = context; 315 u32 *buf = val; 316 int ret; 317 318 u32 ctrl; 319 u8 waddr; 320 u8 word = 0; 321 322 /* allow only writing one complete OTP word at a time */ 323 if ((bytes != priv->config->word_size) || 324 (offset % priv->config->word_size)) 325 return -EINVAL; 326 327 mutex_lock(&ocotp_mutex); 328 329 ret = clk_prepare_enable(priv->clk); 330 if (ret < 0) { 331 mutex_unlock(&ocotp_mutex); 332 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); 333 return ret; 334 } 335 336 /* Setup the write timing values */ 337 priv->params->set_timing(priv); 338 339 /* 47.3.1.3.2 340 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. 341 * Overlapped accesses are not supported by the controller. Any pending 342 * write or reload must be completed before a write access can be 343 * requested. 344 */ 345 ret = imx_ocotp_wait_for_busy(priv, 0); 346 if (ret < 0) { 347 dev_err(priv->dev, "timeout during timing setup\n"); 348 goto write_end; 349 } 350 351 /* 47.3.1.3.3 352 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the 353 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed 354 * for each write access. The lock code is documented in the register 355 * description. Both the unlock code and address can be written in the 356 * same operation. 357 */ 358 if (priv->params->bank_address_words != 0) { 359 /* 360 * In banked/i.MX7 mode the OTP register bank goes into waddr 361 * see i.MX 7Solo Applications Processor Reference Manual, Rev. 362 * 0.1 section 6.4.3.1 363 */ 364 offset = offset / priv->config->word_size; 365 waddr = offset / priv->params->bank_address_words; 366 word = offset & (priv->params->bank_address_words - 1); 367 } else { 368 /* 369 * Non-banked i.MX6 mode. 370 * OTP write/read address specifies one of 128 word address 371 * locations 372 */ 373 waddr = offset / 4; 374 } 375 376 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); 377 ctrl &= ~priv->params->ctrl.bm_addr; 378 ctrl |= waddr & priv->params->ctrl.bm_addr; 379 ctrl |= IMX_OCOTP_WR_UNLOCK; 380 381 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); 382 383 /* 47.3.1.3.4 384 * Write the data to the HW_OCOTP_DATA register. This will automatically 385 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To 386 * protect programming same OTP bit twice, before program OCOTP will 387 * automatically read fuse value in OTP and use read value to mask 388 * program data. The controller will use masked program data to program 389 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit 390 * fields with 1's will result in that OTP bit being programmed. Bit 391 * fields with 0's will be ignored. At the same time that the write is 392 * accepted, the controller makes an internal copy of 393 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write 394 * sequence is initiated. This copy guarantees that erroneous writes to 395 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It 396 * should also be noted that during the programming HW_OCOTP_DATA will 397 * shift right (with zero fill). This shifting is required to program 398 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be 399 * modified. 400 * Note: on i.MX7 there are four data fields to write for banked write 401 * with the fuse blowing operation only taking place after data0 402 * has been written. This is why data0 must always be the last 403 * register written. 404 */ 405 if (priv->params->bank_address_words != 0) { 406 /* Banked/i.MX7 mode */ 407 switch (word) { 408 case 0: 409 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 410 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 411 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 412 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); 413 break; 414 case 1: 415 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); 416 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 417 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 418 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 419 break; 420 case 2: 421 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 422 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); 423 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 424 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 425 break; 426 case 3: 427 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 428 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 429 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); 430 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 431 break; 432 } 433 } else { 434 /* Non-banked i.MX6 mode */ 435 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); 436 } 437 438 /* 47.4.1.4.5 439 * Once complete, the controller will clear BUSY. A write request to a 440 * protected or locked region will result in no OTP access and no 441 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will 442 * be set. It must be cleared by software before any new write access 443 * can be issued. 444 */ 445 ret = imx_ocotp_wait_for_busy(priv, 0); 446 if (ret < 0) { 447 if (ret == -EPERM) { 448 dev_err(priv->dev, "failed write to locked region"); 449 imx_ocotp_clr_err_if_set(priv); 450 } else { 451 dev_err(priv->dev, "timeout during data write\n"); 452 } 453 goto write_end; 454 } 455 456 /* 47.3.1.4 457 * Write Postamble: Due to internal electrical characteristics of the 458 * OTP during writes, all OTP operations following a write must be 459 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following 460 * the write. 461 */ 462 udelay(2); 463 464 /* reload all shadow registers */ 465 writel(priv->params->ctrl.bm_rel_shadows, 466 priv->base + IMX_OCOTP_ADDR_CTRL_SET); 467 ret = imx_ocotp_wait_for_busy(priv, 468 priv->params->ctrl.bm_rel_shadows); 469 if (ret < 0) 470 dev_err(priv->dev, "timeout during shadow register reload\n"); 471 472 write_end: 473 clk_disable_unprepare(priv->clk); 474 mutex_unlock(&ocotp_mutex); 475 return ret < 0 ? ret : bytes; 476 } 477 478 static struct nvmem_config imx_ocotp_nvmem_config = { 479 .name = "imx-ocotp", 480 .read_only = false, 481 .word_size = 4, 482 .stride = 1, 483 .reg_read = imx_ocotp_read, 484 .reg_write = imx_ocotp_write, 485 }; 486 487 static const struct ocotp_params imx6q_params = { 488 .nregs = 128, 489 .bank_address_words = 0, 490 .set_timing = imx_ocotp_set_imx6_timing, 491 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 492 }; 493 494 static const struct ocotp_params imx6sl_params = { 495 .nregs = 64, 496 .bank_address_words = 0, 497 .set_timing = imx_ocotp_set_imx6_timing, 498 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 499 }; 500 501 static const struct ocotp_params imx6sll_params = { 502 .nregs = 128, 503 .bank_address_words = 0, 504 .set_timing = imx_ocotp_set_imx6_timing, 505 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 506 }; 507 508 static const struct ocotp_params imx6sx_params = { 509 .nregs = 128, 510 .bank_address_words = 0, 511 .set_timing = imx_ocotp_set_imx6_timing, 512 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 513 }; 514 515 static const struct ocotp_params imx6ul_params = { 516 .nregs = 128, 517 .bank_address_words = 0, 518 .set_timing = imx_ocotp_set_imx6_timing, 519 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 520 }; 521 522 static const struct ocotp_params imx6ull_params = { 523 .nregs = 64, 524 .bank_address_words = 0, 525 .set_timing = imx_ocotp_set_imx6_timing, 526 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 527 }; 528 529 static const struct ocotp_params imx7d_params = { 530 .nregs = 64, 531 .bank_address_words = 4, 532 .set_timing = imx_ocotp_set_imx7_timing, 533 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 534 }; 535 536 static const struct ocotp_params imx7ulp_params = { 537 .nregs = 256, 538 .bank_address_words = 0, 539 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 540 }; 541 542 static const struct ocotp_params imx8mq_params = { 543 .nregs = 256, 544 .bank_address_words = 0, 545 .set_timing = imx_ocotp_set_imx6_timing, 546 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 547 }; 548 549 static const struct ocotp_params imx8mm_params = { 550 .nregs = 256, 551 .bank_address_words = 0, 552 .set_timing = imx_ocotp_set_imx6_timing, 553 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 554 }; 555 556 static const struct ocotp_params imx8mn_params = { 557 .nregs = 256, 558 .bank_address_words = 0, 559 .set_timing = imx_ocotp_set_imx6_timing, 560 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 561 }; 562 563 static const struct ocotp_params imx8mp_params = { 564 .nregs = 384, 565 .bank_address_words = 0, 566 .set_timing = imx_ocotp_set_imx6_timing, 567 .ctrl = IMX_OCOTP_BM_CTRL_8MP, 568 }; 569 570 static const struct of_device_id imx_ocotp_dt_ids[] = { 571 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, 572 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, 573 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params }, 574 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params }, 575 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params }, 576 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params }, 577 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, 578 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, 579 { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params }, 580 { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params }, 581 { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params }, 582 { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params }, 583 { }, 584 }; 585 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); 586 587 static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem, 588 struct nvmem_layout *layout, 589 struct nvmem_cell_info *cell) 590 { 591 cell->read_post_process = imx_ocotp_cell_pp; 592 } 593 594 static struct nvmem_layout imx_ocotp_layout = { 595 .fixup_cell_info = imx_ocotp_fixup_cell_info, 596 }; 597 598 static int imx_ocotp_probe(struct platform_device *pdev) 599 { 600 struct device *dev = &pdev->dev; 601 struct ocotp_priv *priv; 602 struct nvmem_device *nvmem; 603 604 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 605 if (!priv) 606 return -ENOMEM; 607 608 priv->dev = dev; 609 610 priv->base = devm_platform_ioremap_resource(pdev, 0); 611 if (IS_ERR(priv->base)) 612 return PTR_ERR(priv->base); 613 614 priv->clk = devm_clk_get(dev, NULL); 615 if (IS_ERR(priv->clk)) 616 return PTR_ERR(priv->clk); 617 618 priv->params = of_device_get_match_data(&pdev->dev); 619 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; 620 imx_ocotp_nvmem_config.dev = dev; 621 imx_ocotp_nvmem_config.priv = priv; 622 imx_ocotp_nvmem_config.layout = &imx_ocotp_layout; 623 624 priv->config = &imx_ocotp_nvmem_config; 625 626 clk_prepare_enable(priv->clk); 627 imx_ocotp_clr_err_if_set(priv); 628 clk_disable_unprepare(priv->clk); 629 630 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config); 631 632 return PTR_ERR_OR_ZERO(nvmem); 633 } 634 635 static struct platform_driver imx_ocotp_driver = { 636 .probe = imx_ocotp_probe, 637 .driver = { 638 .name = "imx_ocotp", 639 .of_match_table = imx_ocotp_dt_ids, 640 }, 641 }; 642 module_platform_driver(imx_ocotp_driver); 643 644 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>"); 645 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver"); 646 MODULE_LICENSE("GPL v2"); 647