1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i.MX6 OCOTP fusebox driver 4 * 5 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 6 * 7 * Based on the barebox ocotp driver, 8 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>, 9 * Orex Computed Radiography 10 * 11 * Write support based on the fsl_otp driver, 12 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/nvmem-provider.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/delay.h> 25 26 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the 27 * OTP Bank0 Word0 28 */ 29 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr 30 * of two consecutive OTP words. 31 */ 32 33 #define IMX_OCOTP_ADDR_CTRL 0x0000 34 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004 35 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008 36 #define IMX_OCOTP_ADDR_TIMING 0x0010 37 #define IMX_OCOTP_ADDR_DATA0 0x0020 38 #define IMX_OCOTP_ADDR_DATA1 0x0030 39 #define IMX_OCOTP_ADDR_DATA2 0x0040 40 #define IMX_OCOTP_ADDR_DATA3 0x0050 41 42 #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF 43 #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 44 #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 45 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 46 47 #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF 48 #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200 49 #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400 50 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800 51 52 #define IMX_OCOTP_BM_CTRL_DEFAULT \ 53 { \ 54 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \ 55 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \ 56 .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \ 57 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\ 58 } 59 60 #define IMX_OCOTP_BM_CTRL_8MP \ 61 { \ 62 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \ 63 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \ 64 .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \ 65 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\ 66 } 67 68 #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */ 69 #define TIMING_STROBE_READ_NS 37 /* Min time before read */ 70 #define TIMING_RELAX_NS 17 71 #define DEF_FSOURCE 1001 /* > 1000 ns */ 72 #define DEF_STROBE_PROG 10000 /* IPG clocks */ 73 #define IMX_OCOTP_WR_UNLOCK 0x3E770000 74 #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA 75 76 static DEFINE_MUTEX(ocotp_mutex); 77 78 struct ocotp_priv { 79 struct device *dev; 80 struct clk *clk; 81 void __iomem *base; 82 const struct ocotp_params *params; 83 struct nvmem_config *config; 84 }; 85 86 struct ocotp_ctrl_reg { 87 u32 bm_addr; 88 u32 bm_busy; 89 u32 bm_error; 90 u32 bm_rel_shadows; 91 }; 92 93 struct ocotp_params { 94 unsigned int nregs; 95 unsigned int bank_address_words; 96 void (*set_timing)(struct ocotp_priv *priv); 97 struct ocotp_ctrl_reg ctrl; 98 }; 99 100 static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) 101 { 102 int count; 103 u32 c, mask; 104 u32 bm_ctrl_busy, bm_ctrl_error; 105 void __iomem *base = priv->base; 106 107 bm_ctrl_busy = priv->params->ctrl.bm_busy; 108 bm_ctrl_error = priv->params->ctrl.bm_error; 109 110 mask = bm_ctrl_busy | bm_ctrl_error | flags; 111 112 for (count = 10000; count >= 0; count--) { 113 c = readl(base + IMX_OCOTP_ADDR_CTRL); 114 if (!(c & mask)) 115 break; 116 cpu_relax(); 117 } 118 119 if (count < 0) { 120 /* HW_OCOTP_CTRL[ERROR] will be set under the following 121 * conditions: 122 * - A write is performed to a shadow register during a shadow 123 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is 124 * set. In addition, the contents of the shadow register shall 125 * not be updated. 126 * - A write is performed to a shadow register which has been 127 * locked. 128 * - A read is performed to from a shadow register which has 129 * been read locked. 130 * - A program is performed to a fuse word which has been locked 131 * - A read is performed to from a fuse word which has been read 132 * locked. 133 */ 134 if (c & bm_ctrl_error) 135 return -EPERM; 136 return -ETIMEDOUT; 137 } 138 139 return 0; 140 } 141 142 static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv) 143 { 144 u32 c, bm_ctrl_error; 145 void __iomem *base = priv->base; 146 147 bm_ctrl_error = priv->params->ctrl.bm_error; 148 149 c = readl(base + IMX_OCOTP_ADDR_CTRL); 150 if (!(c & bm_ctrl_error)) 151 return; 152 153 writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR); 154 } 155 156 static int imx_ocotp_read(void *context, unsigned int offset, 157 void *val, size_t bytes) 158 { 159 struct ocotp_priv *priv = context; 160 unsigned int count; 161 u32 *buf = val; 162 int i, ret; 163 u32 index; 164 165 index = offset >> 2; 166 count = bytes >> 2; 167 168 if (count > (priv->params->nregs - index)) 169 count = priv->params->nregs - index; 170 171 mutex_lock(&ocotp_mutex); 172 173 ret = clk_prepare_enable(priv->clk); 174 if (ret < 0) { 175 mutex_unlock(&ocotp_mutex); 176 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); 177 return ret; 178 } 179 180 ret = imx_ocotp_wait_for_busy(priv, 0); 181 if (ret < 0) { 182 dev_err(priv->dev, "timeout during read setup\n"); 183 goto read_end; 184 } 185 186 for (i = index; i < (index + count); i++) { 187 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + 188 i * IMX_OCOTP_OFFSET_PER_WORD); 189 190 /* 47.3.1.2 191 * For "read locked" registers 0xBADABADA will be returned and 192 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by 193 * software before any new write, read or reload access can be 194 * issued 195 */ 196 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) 197 imx_ocotp_clr_err_if_set(priv); 198 } 199 ret = 0; 200 201 read_end: 202 clk_disable_unprepare(priv->clk); 203 mutex_unlock(&ocotp_mutex); 204 return ret; 205 } 206 207 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) 208 { 209 unsigned long clk_rate; 210 unsigned long strobe_read, relax, strobe_prog; 211 u32 timing; 212 213 /* 47.3.1.3.1 214 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] 215 * fields with timing values to match the current frequency of the 216 * ipg_clk. OTP writes will work at maximum bus frequencies as long 217 * as the HW_OCOTP_TIMING parameters are set correctly. 218 * 219 * Note: there are minimum timings required to ensure an OTP fuse burns 220 * correctly that are independent of the ipg_clk. Those values are not 221 * formally documented anywhere however, working from the minimum 222 * timings given in u-boot we can say: 223 * 224 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 225 * microseconds feels about right as representative of a minimum time 226 * to physically burn out a fuse. 227 * 228 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before 229 * performing another read is 37 nanoseconds 230 * 231 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum 232 * timing is not entirely clear the documentation says "This 233 * count value specifies the time to add to all default timing 234 * parameters other than the Tpgm and Trd. It is given in number 235 * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG 236 * and STROBE_READ respectively. What the other timing parameters 237 * are though, is not specified. Experience shows a zero RELAX 238 * value will mess up a re-load of the shadow registers post OTP 239 * burn. 240 */ 241 clk_rate = clk_get_rate(priv->clk); 242 243 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; 244 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, 245 1000000000); 246 strobe_read += 2 * (relax + 1) - 1; 247 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, 248 1000000); 249 strobe_prog += 2 * (relax + 1) - 1; 250 251 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; 252 timing |= strobe_prog & 0x00000FFF; 253 timing |= (relax << 12) & 0x0000F000; 254 timing |= (strobe_read << 16) & 0x003F0000; 255 256 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); 257 } 258 259 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) 260 { 261 unsigned long clk_rate; 262 u64 fsource, strobe_prog; 263 u32 timing; 264 265 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 266 * 6.4.3.3 267 */ 268 clk_rate = clk_get_rate(priv->clk); 269 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, 270 NSEC_PER_SEC) + 1; 271 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, 272 NSEC_PER_SEC) + 1; 273 274 timing = strobe_prog & 0x00000FFF; 275 timing |= (fsource << 12) & 0x000FF000; 276 277 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); 278 } 279 280 static int imx_ocotp_write(void *context, unsigned int offset, void *val, 281 size_t bytes) 282 { 283 struct ocotp_priv *priv = context; 284 u32 *buf = val; 285 int ret; 286 287 u32 ctrl; 288 u8 waddr; 289 u8 word = 0; 290 291 /* allow only writing one complete OTP word at a time */ 292 if ((bytes != priv->config->word_size) || 293 (offset % priv->config->word_size)) 294 return -EINVAL; 295 296 mutex_lock(&ocotp_mutex); 297 298 ret = clk_prepare_enable(priv->clk); 299 if (ret < 0) { 300 mutex_unlock(&ocotp_mutex); 301 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); 302 return ret; 303 } 304 305 /* Setup the write timing values */ 306 priv->params->set_timing(priv); 307 308 /* 47.3.1.3.2 309 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. 310 * Overlapped accesses are not supported by the controller. Any pending 311 * write or reload must be completed before a write access can be 312 * requested. 313 */ 314 ret = imx_ocotp_wait_for_busy(priv, 0); 315 if (ret < 0) { 316 dev_err(priv->dev, "timeout during timing setup\n"); 317 goto write_end; 318 } 319 320 /* 47.3.1.3.3 321 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the 322 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed 323 * for each write access. The lock code is documented in the register 324 * description. Both the unlock code and address can be written in the 325 * same operation. 326 */ 327 if (priv->params->bank_address_words != 0) { 328 /* 329 * In banked/i.MX7 mode the OTP register bank goes into waddr 330 * see i.MX 7Solo Applications Processor Reference Manual, Rev. 331 * 0.1 section 6.4.3.1 332 */ 333 offset = offset / priv->config->word_size; 334 waddr = offset / priv->params->bank_address_words; 335 word = offset & (priv->params->bank_address_words - 1); 336 } else { 337 /* 338 * Non-banked i.MX6 mode. 339 * OTP write/read address specifies one of 128 word address 340 * locations 341 */ 342 waddr = offset / 4; 343 } 344 345 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); 346 ctrl &= ~priv->params->ctrl.bm_addr; 347 ctrl |= waddr & priv->params->ctrl.bm_addr; 348 ctrl |= IMX_OCOTP_WR_UNLOCK; 349 350 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); 351 352 /* 47.3.1.3.4 353 * Write the data to the HW_OCOTP_DATA register. This will automatically 354 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To 355 * protect programming same OTP bit twice, before program OCOTP will 356 * automatically read fuse value in OTP and use read value to mask 357 * program data. The controller will use masked program data to program 358 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit 359 * fields with 1's will result in that OTP bit being programmed. Bit 360 * fields with 0's will be ignored. At the same time that the write is 361 * accepted, the controller makes an internal copy of 362 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write 363 * sequence is initiated. This copy guarantees that erroneous writes to 364 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It 365 * should also be noted that during the programming HW_OCOTP_DATA will 366 * shift right (with zero fill). This shifting is required to program 367 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be 368 * modified. 369 * Note: on i.MX7 there are four data fields to write for banked write 370 * with the fuse blowing operation only taking place after data0 371 * has been written. This is why data0 must always be the last 372 * register written. 373 */ 374 if (priv->params->bank_address_words != 0) { 375 /* Banked/i.MX7 mode */ 376 switch (word) { 377 case 0: 378 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 379 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 380 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 381 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); 382 break; 383 case 1: 384 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); 385 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 386 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 387 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 388 break; 389 case 2: 390 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 391 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); 392 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); 393 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 394 break; 395 case 3: 396 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); 397 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); 398 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); 399 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); 400 break; 401 } 402 } else { 403 /* Non-banked i.MX6 mode */ 404 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); 405 } 406 407 /* 47.4.1.4.5 408 * Once complete, the controller will clear BUSY. A write request to a 409 * protected or locked region will result in no OTP access and no 410 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will 411 * be set. It must be cleared by software before any new write access 412 * can be issued. 413 */ 414 ret = imx_ocotp_wait_for_busy(priv, 0); 415 if (ret < 0) { 416 if (ret == -EPERM) { 417 dev_err(priv->dev, "failed write to locked region"); 418 imx_ocotp_clr_err_if_set(priv); 419 } else { 420 dev_err(priv->dev, "timeout during data write\n"); 421 } 422 goto write_end; 423 } 424 425 /* 47.3.1.4 426 * Write Postamble: Due to internal electrical characteristics of the 427 * OTP during writes, all OTP operations following a write must be 428 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following 429 * the write. 430 */ 431 udelay(2); 432 433 /* reload all shadow registers */ 434 writel(priv->params->ctrl.bm_rel_shadows, 435 priv->base + IMX_OCOTP_ADDR_CTRL_SET); 436 ret = imx_ocotp_wait_for_busy(priv, 437 priv->params->ctrl.bm_rel_shadows); 438 if (ret < 0) { 439 dev_err(priv->dev, "timeout during shadow register reload\n"); 440 goto write_end; 441 } 442 443 write_end: 444 clk_disable_unprepare(priv->clk); 445 mutex_unlock(&ocotp_mutex); 446 if (ret < 0) 447 return ret; 448 return bytes; 449 } 450 451 static struct nvmem_config imx_ocotp_nvmem_config = { 452 .name = "imx-ocotp", 453 .read_only = false, 454 .word_size = 4, 455 .stride = 4, 456 .reg_read = imx_ocotp_read, 457 .reg_write = imx_ocotp_write, 458 }; 459 460 static const struct ocotp_params imx6q_params = { 461 .nregs = 128, 462 .bank_address_words = 0, 463 .set_timing = imx_ocotp_set_imx6_timing, 464 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 465 }; 466 467 static const struct ocotp_params imx6sl_params = { 468 .nregs = 64, 469 .bank_address_words = 0, 470 .set_timing = imx_ocotp_set_imx6_timing, 471 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 472 }; 473 474 static const struct ocotp_params imx6sll_params = { 475 .nregs = 128, 476 .bank_address_words = 0, 477 .set_timing = imx_ocotp_set_imx6_timing, 478 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 479 }; 480 481 static const struct ocotp_params imx6sx_params = { 482 .nregs = 128, 483 .bank_address_words = 0, 484 .set_timing = imx_ocotp_set_imx6_timing, 485 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 486 }; 487 488 static const struct ocotp_params imx6ul_params = { 489 .nregs = 128, 490 .bank_address_words = 0, 491 .set_timing = imx_ocotp_set_imx6_timing, 492 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 493 }; 494 495 static const struct ocotp_params imx6ull_params = { 496 .nregs = 64, 497 .bank_address_words = 0, 498 .set_timing = imx_ocotp_set_imx6_timing, 499 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 500 }; 501 502 static const struct ocotp_params imx7d_params = { 503 .nregs = 64, 504 .bank_address_words = 4, 505 .set_timing = imx_ocotp_set_imx7_timing, 506 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 507 }; 508 509 static const struct ocotp_params imx7ulp_params = { 510 .nregs = 256, 511 .bank_address_words = 0, 512 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 513 }; 514 515 static const struct ocotp_params imx8mq_params = { 516 .nregs = 256, 517 .bank_address_words = 0, 518 .set_timing = imx_ocotp_set_imx6_timing, 519 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 520 }; 521 522 static const struct ocotp_params imx8mm_params = { 523 .nregs = 256, 524 .bank_address_words = 0, 525 .set_timing = imx_ocotp_set_imx6_timing, 526 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 527 }; 528 529 static const struct ocotp_params imx8mn_params = { 530 .nregs = 256, 531 .bank_address_words = 0, 532 .set_timing = imx_ocotp_set_imx6_timing, 533 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, 534 }; 535 536 static const struct ocotp_params imx8mp_params = { 537 .nregs = 384, 538 .bank_address_words = 0, 539 .set_timing = imx_ocotp_set_imx6_timing, 540 .ctrl = IMX_OCOTP_BM_CTRL_8MP, 541 }; 542 543 static const struct of_device_id imx_ocotp_dt_ids[] = { 544 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, 545 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, 546 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params }, 547 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params }, 548 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params }, 549 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params }, 550 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, 551 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, 552 { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params }, 553 { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params }, 554 { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params }, 555 { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params }, 556 { }, 557 }; 558 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); 559 560 static int imx_ocotp_probe(struct platform_device *pdev) 561 { 562 struct device *dev = &pdev->dev; 563 struct ocotp_priv *priv; 564 struct nvmem_device *nvmem; 565 566 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 567 if (!priv) 568 return -ENOMEM; 569 570 priv->dev = dev; 571 572 priv->base = devm_platform_ioremap_resource(pdev, 0); 573 if (IS_ERR(priv->base)) 574 return PTR_ERR(priv->base); 575 576 priv->clk = devm_clk_get(dev, NULL); 577 if (IS_ERR(priv->clk)) 578 return PTR_ERR(priv->clk); 579 580 priv->params = of_device_get_match_data(&pdev->dev); 581 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; 582 imx_ocotp_nvmem_config.dev = dev; 583 imx_ocotp_nvmem_config.priv = priv; 584 priv->config = &imx_ocotp_nvmem_config; 585 586 clk_prepare_enable(priv->clk); 587 imx_ocotp_clr_err_if_set(priv); 588 clk_disable_unprepare(priv->clk); 589 590 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config); 591 592 return PTR_ERR_OR_ZERO(nvmem); 593 } 594 595 static struct platform_driver imx_ocotp_driver = { 596 .probe = imx_ocotp_probe, 597 .driver = { 598 .name = "imx_ocotp", 599 .of_match_table = imx_ocotp_dt_ids, 600 }, 601 }; 602 module_platform_driver(imx_ocotp_driver); 603 604 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>"); 605 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver"); 606 MODULE_LICENSE("GPL v2"); 607