1 /* 2 * Copyright (C) 2016 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/nvmem-provider.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/platform_device.h> 22 23 /* 24 * # of tries for OTP Status. The time to execute a command varies. The slowest 25 * commands are writes which also vary based on the # of bits turned on. Writing 26 * 0xffffffff takes ~3800 us. 27 */ 28 #define OTPC_RETRIES 5000 29 30 /* Sequence to enable OTP program */ 31 #define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd } 32 33 /* OTPC Commands */ 34 #define OTPC_CMD_READ 0x0 35 #define OTPC_CMD_OTP_PROG_ENABLE 0x2 36 #define OTPC_CMD_OTP_PROG_DISABLE 0x3 37 #define OTPC_CMD_PROGRAM 0x8 38 39 /* OTPC Status Bits */ 40 #define OTPC_STAT_CMD_DONE BIT(1) 41 #define OTPC_STAT_PROG_OK BIT(2) 42 43 /* OTPC register definition */ 44 #define OTPC_MODE_REG_OFFSET 0x0 45 #define OTPC_MODE_REG_OTPC_MODE 0 46 #define OTPC_COMMAND_OFFSET 0x4 47 #define OTPC_COMMAND_COMMAND_WIDTH 6 48 #define OTPC_CMD_START_OFFSET 0x8 49 #define OTPC_CMD_START_START 0 50 #define OTPC_CPU_STATUS_OFFSET 0xc 51 #define OTPC_CPUADDR_REG_OFFSET 0x28 52 #define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16 53 #define OTPC_CPU_WRITE_REG_OFFSET 0x2c 54 55 #define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1) 56 #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1) 57 58 59 struct otpc_map { 60 /* in words. */ 61 u32 otpc_row_size; 62 /* 128 bit row / 4 words support. */ 63 u16 data_r_offset[4]; 64 /* 128 bit row / 4 words support. */ 65 u16 data_w_offset[4]; 66 }; 67 68 static struct otpc_map otp_map = { 69 .otpc_row_size = 1, 70 .data_r_offset = {0x10}, 71 .data_w_offset = {0x2c}, 72 }; 73 74 static struct otpc_map otp_map_v2 = { 75 .otpc_row_size = 2, 76 .data_r_offset = {0x10, 0x5c}, 77 .data_w_offset = {0x2c, 0x64}, 78 }; 79 80 struct otpc_priv { 81 struct device *dev; 82 void __iomem *base; 83 struct otpc_map *map; 84 struct nvmem_config *config; 85 }; 86 87 static inline void set_command(void __iomem *base, u32 command) 88 { 89 writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET); 90 } 91 92 static inline void set_cpu_address(void __iomem *base, u32 addr) 93 { 94 writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET); 95 } 96 97 static inline void set_start_bit(void __iomem *base) 98 { 99 writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET); 100 } 101 102 static inline void reset_start_bit(void __iomem *base) 103 { 104 writel(0, base + OTPC_CMD_START_OFFSET); 105 } 106 107 static inline void write_cpu_data(void __iomem *base, u32 value) 108 { 109 writel(value, base + OTPC_CPU_WRITE_REG_OFFSET); 110 } 111 112 static int poll_cpu_status(void __iomem *base, u32 value) 113 { 114 u32 status; 115 u32 retries; 116 117 for (retries = 0; retries < OTPC_RETRIES; retries++) { 118 status = readl(base + OTPC_CPU_STATUS_OFFSET); 119 if (status & value) 120 break; 121 udelay(1); 122 } 123 if (retries == OTPC_RETRIES) 124 return -EAGAIN; 125 126 return 0; 127 } 128 129 static int enable_ocotp_program(void __iomem *base) 130 { 131 static const u32 vals[] = OTPC_PROG_EN_SEQ; 132 int i; 133 int ret; 134 135 /* Write the magic sequence to enable programming */ 136 set_command(base, OTPC_CMD_OTP_PROG_ENABLE); 137 for (i = 0; i < ARRAY_SIZE(vals); i++) { 138 write_cpu_data(base, vals[i]); 139 set_start_bit(base); 140 ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE); 141 reset_start_bit(base); 142 if (ret) 143 return ret; 144 } 145 146 return poll_cpu_status(base, OTPC_STAT_PROG_OK); 147 } 148 149 static int disable_ocotp_program(void __iomem *base) 150 { 151 int ret; 152 153 set_command(base, OTPC_CMD_OTP_PROG_DISABLE); 154 set_start_bit(base); 155 ret = poll_cpu_status(base, OTPC_STAT_PROG_OK); 156 reset_start_bit(base); 157 158 return ret; 159 } 160 161 static int bcm_otpc_read(void *context, unsigned int offset, void *val, 162 size_t bytes) 163 { 164 struct otpc_priv *priv = context; 165 u32 *buf = val; 166 u32 bytes_read; 167 u32 address = offset / priv->config->word_size; 168 int i, ret; 169 170 for (bytes_read = 0; bytes_read < bytes;) { 171 set_command(priv->base, OTPC_CMD_READ); 172 set_cpu_address(priv->base, address++); 173 set_start_bit(priv->base); 174 ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE); 175 if (ret) { 176 dev_err(priv->dev, "otp read error: 0x%x", ret); 177 return -EIO; 178 } 179 180 for (i = 0; i < priv->map->otpc_row_size; i++) { 181 *buf++ = readl(priv->base + 182 priv->map->data_r_offset[i]); 183 bytes_read += sizeof(*buf); 184 } 185 186 reset_start_bit(priv->base); 187 } 188 189 return 0; 190 } 191 192 static int bcm_otpc_write(void *context, unsigned int offset, void *val, 193 size_t bytes) 194 { 195 struct otpc_priv *priv = context; 196 u32 *buf = val; 197 u32 bytes_written; 198 u32 address = offset / priv->config->word_size; 199 int i, ret; 200 201 if (offset % priv->config->word_size) 202 return -EINVAL; 203 204 ret = enable_ocotp_program(priv->base); 205 if (ret) 206 return -EIO; 207 208 for (bytes_written = 0; bytes_written < bytes;) { 209 set_command(priv->base, OTPC_CMD_PROGRAM); 210 set_cpu_address(priv->base, address++); 211 for (i = 0; i < priv->map->otpc_row_size; i++) { 212 writel(*buf, priv->base + priv->map->data_w_offset[i]); 213 buf++; 214 bytes_written += sizeof(*buf); 215 } 216 set_start_bit(priv->base); 217 ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE); 218 reset_start_bit(priv->base); 219 if (ret) { 220 dev_err(priv->dev, "otp write error: 0x%x", ret); 221 return -EIO; 222 } 223 } 224 225 disable_ocotp_program(priv->base); 226 227 return 0; 228 } 229 230 static struct nvmem_config bcm_otpc_nvmem_config = { 231 .name = "bcm-ocotp", 232 .read_only = false, 233 .word_size = 4, 234 .stride = 4, 235 .reg_read = bcm_otpc_read, 236 .reg_write = bcm_otpc_write, 237 }; 238 239 static const struct of_device_id bcm_otpc_dt_ids[] = { 240 { .compatible = "brcm,ocotp" }, 241 { .compatible = "brcm,ocotp-v2" }, 242 { }, 243 }; 244 MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids); 245 246 static int bcm_otpc_probe(struct platform_device *pdev) 247 { 248 struct device *dev = &pdev->dev; 249 struct device_node *dn = dev->of_node; 250 struct resource *res; 251 struct otpc_priv *priv; 252 struct nvmem_device *nvmem; 253 int err; 254 u32 num_words; 255 256 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 257 if (!priv) 258 return -ENOMEM; 259 260 if (of_device_is_compatible(dev->of_node, "brcm,ocotp")) 261 priv->map = &otp_map; 262 else if (of_device_is_compatible(dev->of_node, "brcm,ocotp-v2")) 263 priv->map = &otp_map_v2; 264 else { 265 dev_err(&pdev->dev, 266 "%s otpc config map not defined\n", __func__); 267 return -EINVAL; 268 } 269 270 /* Get OTP base address register. */ 271 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 272 priv->base = devm_ioremap_resource(dev, res); 273 if (IS_ERR(priv->base)) { 274 dev_err(dev, "unable to map I/O memory\n"); 275 return PTR_ERR(priv->base); 276 } 277 278 /* Enable CPU access to OTPC. */ 279 writel(readl(priv->base + OTPC_MODE_REG_OFFSET) | 280 BIT(OTPC_MODE_REG_OTPC_MODE), 281 priv->base + OTPC_MODE_REG_OFFSET); 282 reset_start_bit(priv->base); 283 284 /* Read size of memory in words. */ 285 err = of_property_read_u32(dn, "brcm,ocotp-size", &num_words); 286 if (err) { 287 dev_err(dev, "size parameter not specified\n"); 288 return -EINVAL; 289 } else if (num_words == 0) { 290 dev_err(dev, "size must be > 0\n"); 291 return -EINVAL; 292 } 293 294 bcm_otpc_nvmem_config.size = 4 * num_words; 295 bcm_otpc_nvmem_config.dev = dev; 296 bcm_otpc_nvmem_config.priv = priv; 297 298 if (of_device_is_compatible(dev->of_node, "brcm,ocotp-v2")) { 299 bcm_otpc_nvmem_config.word_size = 8; 300 bcm_otpc_nvmem_config.stride = 8; 301 } 302 303 priv->config = &bcm_otpc_nvmem_config; 304 305 nvmem = nvmem_register(&bcm_otpc_nvmem_config); 306 if (IS_ERR(nvmem)) { 307 dev_err(dev, "error registering nvmem config\n"); 308 return PTR_ERR(nvmem); 309 } 310 311 platform_set_drvdata(pdev, nvmem); 312 313 return 0; 314 } 315 316 static int bcm_otpc_remove(struct platform_device *pdev) 317 { 318 struct nvmem_device *nvmem = platform_get_drvdata(pdev); 319 320 return nvmem_unregister(nvmem); 321 } 322 323 static struct platform_driver bcm_otpc_driver = { 324 .probe = bcm_otpc_probe, 325 .remove = bcm_otpc_remove, 326 .driver = { 327 .name = "brcm-otpc", 328 .of_match_table = bcm_otpc_dt_ids, 329 }, 330 }; 331 module_platform_driver(bcm_otpc_driver); 332 333 MODULE_DESCRIPTION("Broadcom OTPC driver"); 334 MODULE_LICENSE("GPL v2"); 335